mastering_embedded_systems_diploma
stm32f103x6.h
Go to the documentation of this file.
1 
37 #ifndef __STM32F103x6_H
38 #define __STM32F103x6_H
39 
40 #ifdef __cplusplus
41  extern "C" {
42 #endif
43 
50 #define __CM3_REV 0x0200U
51  #define __MPU_PRESENT 0U
52 #define __NVIC_PRIO_BITS 4U
53 #define __Vendor_SysTickConfig 0U
69 typedef enum
70 {
71 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
72  NonMaskableInt_IRQn = -14,
73  HardFault_IRQn = -13,
74  MemoryManagement_IRQn = -12,
75  BusFault_IRQn = -11,
76  UsageFault_IRQn = -10,
77  SVCall_IRQn = -5,
78  DebugMonitor_IRQn = -4,
79  PendSV_IRQn = -2,
80  SysTick_IRQn = -1,
82 /****** STM32 specific Interrupt Numbers *********************************************************/
83  WWDG_IRQn = 0,
84  PVD_IRQn = 1,
85  TAMPER_IRQn = 2,
86  RTC_IRQn = 3,
87  FLASH_IRQn = 4,
88  RCC_IRQn = 5,
89  EXTI0_IRQn = 6,
90  EXTI1_IRQn = 7,
91  EXTI2_IRQn = 8,
92  EXTI3_IRQn = 9,
93  EXTI4_IRQn = 10,
94  DMA1_Channel1_IRQn = 11,
95  DMA1_Channel2_IRQn = 12,
96  DMA1_Channel3_IRQn = 13,
97  DMA1_Channel4_IRQn = 14,
98  DMA1_Channel5_IRQn = 15,
99  DMA1_Channel6_IRQn = 16,
100  DMA1_Channel7_IRQn = 17,
101  ADC1_2_IRQn = 18,
102  USB_HP_CAN1_TX_IRQn = 19,
103  USB_LP_CAN1_RX0_IRQn = 20,
104  CAN1_RX1_IRQn = 21,
105  CAN1_SCE_IRQn = 22,
106  EXTI9_5_IRQn = 23,
107  TIM1_BRK_IRQn = 24,
108  TIM1_UP_IRQn = 25,
109  TIM1_TRG_COM_IRQn = 26,
110  TIM1_CC_IRQn = 27,
111  TIM2_IRQn = 28,
112  TIM3_IRQn = 29,
113  I2C1_EV_IRQn = 31,
114  I2C1_ER_IRQn = 32,
115  SPI1_IRQn = 35,
116  USART1_IRQn = 37,
117  USART2_IRQn = 38,
118  EXTI15_10_IRQn = 40,
119  RTC_Alarm_IRQn = 41,
120  USBWakeUp_IRQn = 42,
121 } IRQn_Type;
122 
127 #include "core_cm3.h"
128 #include "system_stm32f1xx.h"
129 #include <stdint.h>
130 
139 typedef struct
140 {
141  __IO uint32_t SR;
142  __IO uint32_t CR1;
143  __IO uint32_t CR2;
144  __IO uint32_t SMPR1;
145  __IO uint32_t SMPR2;
146  __IO uint32_t JOFR1;
147  __IO uint32_t JOFR2;
148  __IO uint32_t JOFR3;
149  __IO uint32_t JOFR4;
150  __IO uint32_t HTR;
151  __IO uint32_t LTR;
152  __IO uint32_t SQR1;
153  __IO uint32_t SQR2;
154  __IO uint32_t SQR3;
155  __IO uint32_t JSQR;
156  __IO uint32_t JDR1;
157  __IO uint32_t JDR2;
158  __IO uint32_t JDR3;
159  __IO uint32_t JDR4;
160  __IO uint32_t DR;
161 } ADC_TypeDef;
162 
163 typedef struct
164 {
165  __IO uint32_t SR;
166  __IO uint32_t CR1;
167  __IO uint32_t CR2;
168  uint32_t RESERVED[16];
169  __IO uint32_t DR;
170 } ADC_Common_TypeDef;
171 
176 typedef struct
177 {
178  uint32_t RESERVED0;
179  __IO uint32_t DR1;
180  __IO uint32_t DR2;
181  __IO uint32_t DR3;
182  __IO uint32_t DR4;
183  __IO uint32_t DR5;
184  __IO uint32_t DR6;
185  __IO uint32_t DR7;
186  __IO uint32_t DR8;
187  __IO uint32_t DR9;
188  __IO uint32_t DR10;
189  __IO uint32_t RTCCR;
190  __IO uint32_t CR;
191  __IO uint32_t CSR;
192 } BKP_TypeDef;
193 
198 typedef struct
199 {
200  __IO uint32_t TIR;
201  __IO uint32_t TDTR;
202  __IO uint32_t TDLR;
203  __IO uint32_t TDHR;
204 } CAN_TxMailBox_TypeDef;
205 
210 typedef struct
211 {
212  __IO uint32_t RIR;
213  __IO uint32_t RDTR;
214  __IO uint32_t RDLR;
215  __IO uint32_t RDHR;
216 } CAN_FIFOMailBox_TypeDef;
217 
222 typedef struct
223 {
224  __IO uint32_t FR1;
225  __IO uint32_t FR2;
226 } CAN_FilterRegister_TypeDef;
227 
232 typedef struct
233 {
234  __IO uint32_t MCR;
235  __IO uint32_t MSR;
236  __IO uint32_t TSR;
237  __IO uint32_t RF0R;
238  __IO uint32_t RF1R;
239  __IO uint32_t IER;
240  __IO uint32_t ESR;
241  __IO uint32_t BTR;
242  uint32_t RESERVED0[88];
243  CAN_TxMailBox_TypeDef sTxMailBox[3];
244  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
245  uint32_t RESERVED1[12];
246  __IO uint32_t FMR;
247  __IO uint32_t FM1R;
248  uint32_t RESERVED2;
249  __IO uint32_t FS1R;
250  uint32_t RESERVED3;
251  __IO uint32_t FFA1R;
252  uint32_t RESERVED4;
253  __IO uint32_t FA1R;
254  uint32_t RESERVED5[8];
255  CAN_FilterRegister_TypeDef sFilterRegister[14];
256 } CAN_TypeDef;
257 
262 typedef struct
263 {
264  __IO uint32_t DR;
265  __IO uint8_t IDR;
266  uint8_t RESERVED0;
267  uint16_t RESERVED1;
268  __IO uint32_t CR;
269 } CRC_TypeDef;
270 
271 
276 typedef struct
277 {
278  __IO uint32_t IDCODE;
279  __IO uint32_t CR;
280 }DBGMCU_TypeDef;
281 
286 typedef struct
287 {
288  __IO uint32_t CCR;
289  __IO uint32_t CNDTR;
290  __IO uint32_t CPAR;
291  __IO uint32_t CMAR;
292 } DMA_Channel_TypeDef;
293 
294 typedef struct
295 {
296  __IO uint32_t ISR;
297  __IO uint32_t IFCR;
298 } DMA_TypeDef;
299 
300 
301 
306 typedef struct
307 {
308  __IO uint32_t IMR;
309  __IO uint32_t EMR;
310  __IO uint32_t RTSR;
311  __IO uint32_t FTSR;
312  __IO uint32_t SWIER;
313  __IO uint32_t PR;
314 } EXTI_TypeDef;
315 
320 typedef struct
321 {
322  __IO uint32_t ACR;
323  __IO uint32_t KEYR;
324  __IO uint32_t OPTKEYR;
325  __IO uint32_t SR;
326  __IO uint32_t CR;
327  __IO uint32_t AR;
328  __IO uint32_t RESERVED;
329  __IO uint32_t OBR;
330  __IO uint32_t WRPR;
331 } FLASH_TypeDef;
332 
337 typedef struct
338 {
339  __IO uint16_t RDP;
340  __IO uint16_t USER;
341  __IO uint16_t Data0;
342  __IO uint16_t Data1;
343  __IO uint16_t WRP0;
344  __IO uint16_t WRP1;
345  __IO uint16_t WRP2;
346  __IO uint16_t WRP3;
347 } OB_TypeDef;
348 
353 typedef struct
354 {
355  __IO uint32_t CRL;
356  __IO uint32_t CRH;
357  __IO uint32_t IDR;
358  __IO uint32_t ODR;
359  __IO uint32_t BSRR;
360  __IO uint32_t BRR;
361  __IO uint32_t LCKR;
362 } GPIO_TypeDef;
363 
368 typedef struct
369 {
370  __IO uint32_t EVCR;
371  __IO uint32_t MAPR;
372  __IO uint32_t EXTICR[4];
373  uint32_t RESERVED0;
374  __IO uint32_t MAPR2;
375 } AFIO_TypeDef;
380 typedef struct
381 {
382  __IO uint32_t CR1;
383  __IO uint32_t CR2;
384  __IO uint32_t OAR1;
385  __IO uint32_t OAR2;
386  __IO uint32_t DR;
387  __IO uint32_t SR1;
388  __IO uint32_t SR2;
389  __IO uint32_t CCR;
390  __IO uint32_t TRISE;
391 } I2C_TypeDef;
392 
397 typedef struct
398 {
399  __IO uint32_t KR;
400  __IO uint32_t PR;
401  __IO uint32_t RLR;
402  __IO uint32_t SR;
403 } IWDG_TypeDef;
404 
409 typedef struct
410 {
411  __IO uint32_t CR;
412  __IO uint32_t CSR;
413 } PWR_TypeDef;
414 
419 typedef struct
420 {
421  __IO uint32_t CR;
422  __IO uint32_t CFGR;
423  __IO uint32_t CIR;
424  __IO uint32_t APB2RSTR;
425  __IO uint32_t APB1RSTR;
426  __IO uint32_t AHBENR;
427  __IO uint32_t APB2ENR;
428  __IO uint32_t APB1ENR;
429  __IO uint32_t BDCR;
430  __IO uint32_t CSR;
431 
432 
433 } RCC_TypeDef;
434 
439 typedef struct
440 {
441  __IO uint32_t CRH;
442  __IO uint32_t CRL;
443  __IO uint32_t PRLH;
444  __IO uint32_t PRLL;
445  __IO uint32_t DIVH;
446  __IO uint32_t DIVL;
447  __IO uint32_t CNTH;
448  __IO uint32_t CNTL;
449  __IO uint32_t ALRH;
450  __IO uint32_t ALRL;
451 } RTC_TypeDef;
452 
457 typedef struct
458 {
459  __IO uint32_t CR1;
460  __IO uint32_t CR2;
461  __IO uint32_t SR;
462  __IO uint32_t DR;
463  __IO uint32_t CRCPR;
464  __IO uint32_t RXCRCR;
465  __IO uint32_t TXCRCR;
466  __IO uint32_t I2SCFGR;
467 } SPI_TypeDef;
468 
472 typedef struct
473 {
474  __IO uint32_t CR1;
475  __IO uint32_t CR2;
476  __IO uint32_t SMCR;
477  __IO uint32_t DIER;
478  __IO uint32_t SR;
479  __IO uint32_t EGR;
480  __IO uint32_t CCMR1;
481  __IO uint32_t CCMR2;
482  __IO uint32_t CCER;
483  __IO uint32_t CNT;
484  __IO uint32_t PSC;
485  __IO uint32_t ARR;
486  __IO uint32_t RCR;
487  __IO uint32_t CCR1;
488  __IO uint32_t CCR2;
489  __IO uint32_t CCR3;
490  __IO uint32_t CCR4;
491  __IO uint32_t BDTR;
492  __IO uint32_t DCR;
493  __IO uint32_t DMAR;
494  __IO uint32_t OR;
495 }TIM_TypeDef;
496 
497 
502 typedef struct
503 {
504  __IO uint32_t SR;
505  __IO uint32_t DR;
506  __IO uint32_t BRR;
507  __IO uint32_t CR1;
508  __IO uint32_t CR2;
509  __IO uint32_t CR3;
510  __IO uint32_t GTPR;
511 } USART_TypeDef;
512 
517 typedef struct
518 {
519  __IO uint16_t EP0R;
520  __IO uint16_t RESERVED0;
521  __IO uint16_t EP1R;
522  __IO uint16_t RESERVED1;
523  __IO uint16_t EP2R;
524  __IO uint16_t RESERVED2;
525  __IO uint16_t EP3R;
526  __IO uint16_t RESERVED3;
527  __IO uint16_t EP4R;
528  __IO uint16_t RESERVED4;
529  __IO uint16_t EP5R;
530  __IO uint16_t RESERVED5;
531  __IO uint16_t EP6R;
532  __IO uint16_t RESERVED6;
533  __IO uint16_t EP7R;
534  __IO uint16_t RESERVED7[17];
535  __IO uint16_t CNTR;
536  __IO uint16_t RESERVED8;
537  __IO uint16_t ISTR;
538  __IO uint16_t RESERVED9;
539  __IO uint16_t FNR;
540  __IO uint16_t RESERVEDA;
541  __IO uint16_t DADDR;
542  __IO uint16_t RESERVEDB;
543  __IO uint16_t BTABLE;
544  __IO uint16_t RESERVEDC;
545 } USB_TypeDef;
546 
547 
552 typedef struct
553 {
554  __IO uint32_t CR;
555  __IO uint32_t CFR;
556  __IO uint32_t SR;
557 } WWDG_TypeDef;
558 
568 #define FLASH_BASE 0x08000000UL
569 #define FLASH_BANK1_END 0x08007FFFUL
570 #define SRAM_BASE 0x20000000UL
571 #define PERIPH_BASE 0x40000000UL
573 #define SRAM_BB_BASE 0x22000000UL
574 #define PERIPH_BB_BASE 0x42000000UL
578 #define APB1PERIPH_BASE PERIPH_BASE
579 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
580 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
581 
582 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)
583 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)
584 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)
585 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)
586 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)
587 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)
588 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)
589 #define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL)
590 #define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL)
591 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)
592 #define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL)
593 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)
594 #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL)
595 #define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL)
596 #define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL)
597 #define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL)
598 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL)
599 #define ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL)
600 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)
601 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)
602 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)
603 
604 
605 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
606 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL)
607 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL)
608 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL)
609 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL)
610 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL)
611 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL)
612 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL)
613 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
614 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
615 
616 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL)
617 #define FLASHSIZE_BASE 0x1FFFF7E0UL
618 #define UID_BASE 0x1FFFF7E8UL
619 #define OB_BASE 0x1FFFF800UL
623 #define DBGMCU_BASE 0xE0042000UL
625 /* USB device FS */
626 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL)
627 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL)
638 #define TIM2 ((TIM_TypeDef *)TIM2_BASE)
639 #define TIM3 ((TIM_TypeDef *)TIM3_BASE)
640 #define RTC ((RTC_TypeDef *)RTC_BASE)
641 #define WWDG ((WWDG_TypeDef *)WWDG_BASE)
642 #define IWDG ((IWDG_TypeDef *)IWDG_BASE)
643 #define USART2 ((USART_TypeDef *)USART2_BASE)
644 #define I2C1 ((I2C_TypeDef *)I2C1_BASE)
645 #define USB ((USB_TypeDef *)USB_BASE)
646 #define CAN1 ((CAN_TypeDef *)CAN1_BASE)
647 #define BKP ((BKP_TypeDef *)BKP_BASE)
648 #define PWR ((PWR_TypeDef *)PWR_BASE)
649 #define AFIO ((AFIO_TypeDef *)AFIO_BASE)
650 #define EXTI ((EXTI_TypeDef *)EXTI_BASE)
651 #define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
652 #define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
653 #define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
654 #define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
655 #define ADC1 ((ADC_TypeDef *)ADC1_BASE)
656 #define ADC2 ((ADC_TypeDef *)ADC2_BASE)
657 #define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
658 #define TIM1 ((TIM_TypeDef *)TIM1_BASE)
659 #define SPI1 ((SPI_TypeDef *)SPI1_BASE)
660 #define USART1 ((USART_TypeDef *)USART1_BASE)
661 #define DMA1 ((DMA_TypeDef *)DMA1_BASE)
662 #define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
663 #define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
664 #define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
665 #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
666 #define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
667 #define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
668 #define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
669 #define RCC ((RCC_TypeDef *)RCC_BASE)
670 #define CRC ((CRC_TypeDef *)CRC_BASE)
671 #define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
672 #define OB ((OB_TypeDef *)OB_BASE)
673 #define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
674 
675 
687 #define LSI_STARTUP_TIME 85U
696 /******************************************************************************/
697 /* Peripheral Registers_Bits_Definition */
698 /******************************************************************************/
699 
700 /******************************************************************************/
701 /* */
702 /* CRC calculation unit (CRC) */
703 /* */
704 /******************************************************************************/
705 
706 /******************* Bit definition for CRC_DR register *********************/
707 #define CRC_DR_DR_Pos (0U)
708 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
709 #define CRC_DR_DR CRC_DR_DR_Msk
711 /******************* Bit definition for CRC_IDR register ********************/
712 #define CRC_IDR_IDR_Pos (0U)
713 #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)
714 #define CRC_IDR_IDR CRC_IDR_IDR_Msk
716 /******************** Bit definition for CRC_CR register ********************/
717 #define CRC_CR_RESET_Pos (0U)
718 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
719 #define CRC_CR_RESET CRC_CR_RESET_Msk
721 /******************************************************************************/
722 /* */
723 /* Power Control */
724 /* */
725 /******************************************************************************/
726 
727 /******************** Bit definition for PWR_CR register ********************/
728 #define PWR_CR_LPDS_Pos (0U)
729 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)
730 #define PWR_CR_LPDS PWR_CR_LPDS_Msk
731 #define PWR_CR_PDDS_Pos (1U)
732 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)
733 #define PWR_CR_PDDS PWR_CR_PDDS_Msk
734 #define PWR_CR_CWUF_Pos (2U)
735 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)
736 #define PWR_CR_CWUF PWR_CR_CWUF_Msk
737 #define PWR_CR_CSBF_Pos (3U)
738 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)
739 #define PWR_CR_CSBF PWR_CR_CSBF_Msk
740 #define PWR_CR_PVDE_Pos (4U)
741 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)
742 #define PWR_CR_PVDE PWR_CR_PVDE_Msk
744 #define PWR_CR_PLS_Pos (5U)
745 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)
746 #define PWR_CR_PLS PWR_CR_PLS_Msk
747 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)
748 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)
749 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)
752 #define PWR_CR_PLS_LEV0 0x00000000U
753 #define PWR_CR_PLS_LEV1 0x00000020U
754 #define PWR_CR_PLS_LEV2 0x00000040U
755 #define PWR_CR_PLS_LEV3 0x00000060U
756 #define PWR_CR_PLS_LEV4 0x00000080U
757 #define PWR_CR_PLS_LEV5 0x000000A0U
758 #define PWR_CR_PLS_LEV6 0x000000C0U
759 #define PWR_CR_PLS_LEV7 0x000000E0U
761 /* Legacy defines */
762 #define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
763 #define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
764 #define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
765 #define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
766 #define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
767 #define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
768 #define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
769 #define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
770 
771 #define PWR_CR_DBP_Pos (8U)
772 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)
773 #define PWR_CR_DBP PWR_CR_DBP_Msk
776 /******************* Bit definition for PWR_CSR register ********************/
777 #define PWR_CSR_WUF_Pos (0U)
778 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)
779 #define PWR_CSR_WUF PWR_CSR_WUF_Msk
780 #define PWR_CSR_SBF_Pos (1U)
781 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)
782 #define PWR_CSR_SBF PWR_CSR_SBF_Msk
783 #define PWR_CSR_PVDO_Pos (2U)
784 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)
785 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk
786 #define PWR_CSR_EWUP_Pos (8U)
787 #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)
788 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk
790 /******************************************************************************/
791 /* */
792 /* Backup registers */
793 /* */
794 /******************************************************************************/
795 
796 /******************* Bit definition for BKP_DR1 register ********************/
797 #define BKP_DR1_D_Pos (0U)
798 #define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos)
799 #define BKP_DR1_D BKP_DR1_D_Msk
801 /******************* Bit definition for BKP_DR2 register ********************/
802 #define BKP_DR2_D_Pos (0U)
803 #define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos)
804 #define BKP_DR2_D BKP_DR2_D_Msk
806 /******************* Bit definition for BKP_DR3 register ********************/
807 #define BKP_DR3_D_Pos (0U)
808 #define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos)
809 #define BKP_DR3_D BKP_DR3_D_Msk
811 /******************* Bit definition for BKP_DR4 register ********************/
812 #define BKP_DR4_D_Pos (0U)
813 #define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos)
814 #define BKP_DR4_D BKP_DR4_D_Msk
816 /******************* Bit definition for BKP_DR5 register ********************/
817 #define BKP_DR5_D_Pos (0U)
818 #define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos)
819 #define BKP_DR5_D BKP_DR5_D_Msk
821 /******************* Bit definition for BKP_DR6 register ********************/
822 #define BKP_DR6_D_Pos (0U)
823 #define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos)
824 #define BKP_DR6_D BKP_DR6_D_Msk
826 /******************* Bit definition for BKP_DR7 register ********************/
827 #define BKP_DR7_D_Pos (0U)
828 #define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos)
829 #define BKP_DR7_D BKP_DR7_D_Msk
831 /******************* Bit definition for BKP_DR8 register ********************/
832 #define BKP_DR8_D_Pos (0U)
833 #define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos)
834 #define BKP_DR8_D BKP_DR8_D_Msk
836 /******************* Bit definition for BKP_DR9 register ********************/
837 #define BKP_DR9_D_Pos (0U)
838 #define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos)
839 #define BKP_DR9_D BKP_DR9_D_Msk
841 /******************* Bit definition for BKP_DR10 register *******************/
842 #define BKP_DR10_D_Pos (0U)
843 #define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos)
844 #define BKP_DR10_D BKP_DR10_D_Msk
846 #define RTC_BKP_NUMBER 10
847 
848 /****************** Bit definition for BKP_RTCCR register *******************/
849 #define BKP_RTCCR_CAL_Pos (0U)
850 #define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos)
851 #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk
852 #define BKP_RTCCR_CCO_Pos (7U)
853 #define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos)
854 #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk
855 #define BKP_RTCCR_ASOE_Pos (8U)
856 #define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos)
857 #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk
858 #define BKP_RTCCR_ASOS_Pos (9U)
859 #define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos)
860 #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk
862 /******************** Bit definition for BKP_CR register ********************/
863 #define BKP_CR_TPE_Pos (0U)
864 #define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos)
865 #define BKP_CR_TPE BKP_CR_TPE_Msk
866 #define BKP_CR_TPAL_Pos (1U)
867 #define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos)
868 #define BKP_CR_TPAL BKP_CR_TPAL_Msk
870 /******************* Bit definition for BKP_CSR register ********************/
871 #define BKP_CSR_CTE_Pos (0U)
872 #define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos)
873 #define BKP_CSR_CTE BKP_CSR_CTE_Msk
874 #define BKP_CSR_CTI_Pos (1U)
875 #define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos)
876 #define BKP_CSR_CTI BKP_CSR_CTI_Msk
877 #define BKP_CSR_TPIE_Pos (2U)
878 #define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos)
879 #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk
880 #define BKP_CSR_TEF_Pos (8U)
881 #define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos)
882 #define BKP_CSR_TEF BKP_CSR_TEF_Msk
883 #define BKP_CSR_TIF_Pos (9U)
884 #define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos)
885 #define BKP_CSR_TIF BKP_CSR_TIF_Msk
887 /******************************************************************************/
888 /* */
889 /* Reset and Clock Control */
890 /* */
891 /******************************************************************************/
892 
893 /******************** Bit definition for RCC_CR register ********************/
894 #define RCC_CR_HSION_Pos (0U)
895 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
896 #define RCC_CR_HSION RCC_CR_HSION_Msk
897 #define RCC_CR_HSIRDY_Pos (1U)
898 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
899 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
900 #define RCC_CR_HSITRIM_Pos (3U)
901 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)
902 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk
903 #define RCC_CR_HSICAL_Pos (8U)
904 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)
905 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk
906 #define RCC_CR_HSEON_Pos (16U)
907 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
908 #define RCC_CR_HSEON RCC_CR_HSEON_Msk
909 #define RCC_CR_HSERDY_Pos (17U)
910 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
911 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
912 #define RCC_CR_HSEBYP_Pos (18U)
913 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
914 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
915 #define RCC_CR_CSSON_Pos (19U)
916 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)
917 #define RCC_CR_CSSON RCC_CR_CSSON_Msk
918 #define RCC_CR_PLLON_Pos (24U)
919 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
920 #define RCC_CR_PLLON RCC_CR_PLLON_Msk
921 #define RCC_CR_PLLRDY_Pos (25U)
922 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
923 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
926 /******************* Bit definition for RCC_CFGR register *******************/
927 
928 #define RCC_CFGR_SW_Pos (0U)
929 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)
930 #define RCC_CFGR_SW RCC_CFGR_SW_Msk
931 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
932 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
934 #define RCC_CFGR_SW_HSI 0x00000000U
935 #define RCC_CFGR_SW_HSE 0x00000001U
936 #define RCC_CFGR_SW_PLL 0x00000002U
939 #define RCC_CFGR_SWS_Pos (2U)
940 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)
941 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
942 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
943 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
945 #define RCC_CFGR_SWS_HSI 0x00000000U
946 #define RCC_CFGR_SWS_HSE 0x00000004U
947 #define RCC_CFGR_SWS_PLL 0x00000008U
950 #define RCC_CFGR_HPRE_Pos (4U)
951 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)
952 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk
953 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)
954 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)
955 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)
956 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)
958 #define RCC_CFGR_HPRE_DIV1 0x00000000U
959 #define RCC_CFGR_HPRE_DIV2 0x00000080U
960 #define RCC_CFGR_HPRE_DIV4 0x00000090U
961 #define RCC_CFGR_HPRE_DIV8 0x000000A0U
962 #define RCC_CFGR_HPRE_DIV16 0x000000B0U
963 #define RCC_CFGR_HPRE_DIV64 0x000000C0U
964 #define RCC_CFGR_HPRE_DIV128 0x000000D0U
965 #define RCC_CFGR_HPRE_DIV256 0x000000E0U
966 #define RCC_CFGR_HPRE_DIV512 0x000000F0U
969 #define RCC_CFGR_PPRE1_Pos (8U)
970 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)
971 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk
972 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)
973 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)
974 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)
976 #define RCC_CFGR_PPRE1_DIV1 0x00000000U
977 #define RCC_CFGR_PPRE1_DIV2 0x00000400U
978 #define RCC_CFGR_PPRE1_DIV4 0x00000500U
979 #define RCC_CFGR_PPRE1_DIV8 0x00000600U
980 #define RCC_CFGR_PPRE1_DIV16 0x00000700U
983 #define RCC_CFGR_PPRE2_Pos (11U)
984 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)
985 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk
986 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)
987 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)
988 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)
990 #define RCC_CFGR_PPRE2_DIV1 0x00000000U
991 #define RCC_CFGR_PPRE2_DIV2 0x00002000U
992 #define RCC_CFGR_PPRE2_DIV4 0x00002800U
993 #define RCC_CFGR_PPRE2_DIV8 0x00003000U
994 #define RCC_CFGR_PPRE2_DIV16 0x00003800U
997 #define RCC_CFGR_ADCPRE_Pos (14U)
998 #define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos)
999 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk
1000 #define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos)
1001 #define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos)
1003 #define RCC_CFGR_ADCPRE_DIV2 0x00000000U
1004 #define RCC_CFGR_ADCPRE_DIV4 0x00004000U
1005 #define RCC_CFGR_ADCPRE_DIV6 0x00008000U
1006 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U
1008 #define RCC_CFGR_PLLSRC_Pos (16U)
1009 #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos)
1010 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk
1012 #define RCC_CFGR_PLLXTPRE_Pos (17U)
1013 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos)
1014 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk
1017 #define RCC_CFGR_PLLMULL_Pos (18U)
1018 #define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos)
1019 #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk
1020 #define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos)
1021 #define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos)
1022 #define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos)
1023 #define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos)
1025 #define RCC_CFGR_PLLXTPRE_HSE 0x00000000U
1026 #define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U
1028 #define RCC_CFGR_PLLMULL2 0x00000000U
1029 #define RCC_CFGR_PLLMULL3_Pos (18U)
1030 #define RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos)
1031 #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk
1032 #define RCC_CFGR_PLLMULL4_Pos (19U)
1033 #define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos)
1034 #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk
1035 #define RCC_CFGR_PLLMULL5_Pos (18U)
1036 #define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos)
1037 #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk
1038 #define RCC_CFGR_PLLMULL6_Pos (20U)
1039 #define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos)
1040 #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk
1041 #define RCC_CFGR_PLLMULL7_Pos (18U)
1042 #define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos)
1043 #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk
1044 #define RCC_CFGR_PLLMULL8_Pos (19U)
1045 #define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos)
1046 #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk
1047 #define RCC_CFGR_PLLMULL9_Pos (18U)
1048 #define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos)
1049 #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk
1050 #define RCC_CFGR_PLLMULL10_Pos (21U)
1051 #define RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos)
1052 #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk
1053 #define RCC_CFGR_PLLMULL11_Pos (18U)
1054 #define RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos)
1055 #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk
1056 #define RCC_CFGR_PLLMULL12_Pos (19U)
1057 #define RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos)
1058 #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk
1059 #define RCC_CFGR_PLLMULL13_Pos (18U)
1060 #define RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos)
1061 #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk
1062 #define RCC_CFGR_PLLMULL14_Pos (20U)
1063 #define RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos)
1064 #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk
1065 #define RCC_CFGR_PLLMULL15_Pos (18U)
1066 #define RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos)
1067 #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk
1068 #define RCC_CFGR_PLLMULL16_Pos (19U)
1069 #define RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos)
1070 #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk
1071 #define RCC_CFGR_USBPRE_Pos (22U)
1072 #define RCC_CFGR_USBPRE_Msk (0x1UL << RCC_CFGR_USBPRE_Pos)
1073 #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk
1076 #define RCC_CFGR_MCO_Pos (24U)
1077 #define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos)
1078 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk
1079 #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos)
1080 #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos)
1081 #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos)
1083 #define RCC_CFGR_MCO_NOCLOCK 0x00000000U
1084 #define RCC_CFGR_MCO_SYSCLK 0x04000000U
1085 #define RCC_CFGR_MCO_HSI 0x05000000U
1086 #define RCC_CFGR_MCO_HSE 0x06000000U
1087 #define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U
1089  /* Reference defines */
1090  #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
1091  #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
1092  #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
1093  #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
1094  #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
1095  #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
1096  #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
1097  #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
1098  #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
1099 
1101 #define RCC_CIR_LSIRDYF_Pos (0U)
1102 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)
1103 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk
1104 #define RCC_CIR_LSERDYF_Pos (1U)
1105 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)
1106 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk
1107 #define RCC_CIR_HSIRDYF_Pos (2U)
1108 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)
1109 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk
1110 #define RCC_CIR_HSERDYF_Pos (3U)
1111 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)
1112 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk
1113 #define RCC_CIR_PLLRDYF_Pos (4U)
1114 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)
1115 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk
1116 #define RCC_CIR_CSSF_Pos (7U)
1117 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)
1118 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk
1119 #define RCC_CIR_LSIRDYIE_Pos (8U)
1120 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)
1121 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk
1122 #define RCC_CIR_LSERDYIE_Pos (9U)
1123 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)
1124 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk
1125 #define RCC_CIR_HSIRDYIE_Pos (10U)
1126 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)
1127 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk
1128 #define RCC_CIR_HSERDYIE_Pos (11U)
1129 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)
1130 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk
1131 #define RCC_CIR_PLLRDYIE_Pos (12U)
1132 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)
1133 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk
1134 #define RCC_CIR_LSIRDYC_Pos (16U)
1135 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)
1136 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk
1137 #define RCC_CIR_LSERDYC_Pos (17U)
1138 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)
1139 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk
1140 #define RCC_CIR_HSIRDYC_Pos (18U)
1141 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)
1142 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk
1143 #define RCC_CIR_HSERDYC_Pos (19U)
1144 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)
1145 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk
1146 #define RCC_CIR_PLLRDYC_Pos (20U)
1147 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)
1148 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk
1149 #define RCC_CIR_CSSC_Pos (23U)
1150 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)
1151 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk
1154 /***************** Bit definition for RCC_APB2RSTR register *****************/
1155 #define RCC_APB2RSTR_AFIORST_Pos (0U)
1156 #define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos)
1157 #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk
1158 #define RCC_APB2RSTR_IOPARST_Pos (2U)
1159 #define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos)
1160 #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk
1161 #define RCC_APB2RSTR_IOPBRST_Pos (3U)
1162 #define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos)
1163 #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk
1164 #define RCC_APB2RSTR_IOPCRST_Pos (4U)
1165 #define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos)
1166 #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk
1167 #define RCC_APB2RSTR_IOPDRST_Pos (5U)
1168 #define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos)
1169 #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk
1170 #define RCC_APB2RSTR_ADC1RST_Pos (9U)
1171 #define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos)
1172 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk
1174 #define RCC_APB2RSTR_ADC2RST_Pos (10U)
1175 #define RCC_APB2RSTR_ADC2RST_Msk (0x1UL << RCC_APB2RSTR_ADC2RST_Pos)
1176 #define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk
1178 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
1179 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
1180 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
1181 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
1182 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
1183 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
1184 #define RCC_APB2RSTR_USART1RST_Pos (14U)
1185 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
1186 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
1193 /***************** Bit definition for RCC_APB1RSTR register *****************/
1194 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
1195 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)
1196 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk
1197 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
1198 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)
1199 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk
1200 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
1201 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)
1202 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk
1203 #define RCC_APB1RSTR_USART2RST_Pos (17U)
1204 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)
1205 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk
1206 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
1207 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)
1208 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk
1210 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
1211 #define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)
1212 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk
1214 #define RCC_APB1RSTR_BKPRST_Pos (27U)
1215 #define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos)
1216 #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk
1217 #define RCC_APB1RSTR_PWRRST_Pos (28U)
1218 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)
1219 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk
1222 #define RCC_APB1RSTR_USBRST_Pos (23U)
1223 #define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos)
1224 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk
1231 /****************** Bit definition for RCC_AHBENR register ******************/
1232 #define RCC_AHBENR_DMA1EN_Pos (0U)
1233 #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos)
1234 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk
1235 #define RCC_AHBENR_SRAMEN_Pos (2U)
1236 #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos)
1237 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk
1238 #define RCC_AHBENR_FLITFEN_Pos (4U)
1239 #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos)
1240 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk
1241 #define RCC_AHBENR_CRCEN_Pos (6U)
1242 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos)
1243 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk
1248 /****************** Bit definition for RCC_APB2ENR register *****************/
1249 #define RCC_APB2ENR_AFIOEN_Pos (0U)
1250 #define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos)
1251 #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk
1252 #define RCC_APB2ENR_IOPAEN_Pos (2U)
1253 #define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos)
1254 #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk
1255 #define RCC_APB2ENR_IOPBEN_Pos (3U)
1256 #define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos)
1257 #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk
1258 #define RCC_APB2ENR_IOPCEN_Pos (4U)
1259 #define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos)
1260 #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk
1261 #define RCC_APB2ENR_IOPDEN_Pos (5U)
1262 #define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos)
1263 #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk
1264 #define RCC_APB2ENR_ADC1EN_Pos (9U)
1265 #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)
1266 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk
1268 #define RCC_APB2ENR_ADC2EN_Pos (10U)
1269 #define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)
1270 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk
1272 #define RCC_APB2ENR_TIM1EN_Pos (11U)
1273 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
1274 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
1275 #define RCC_APB2ENR_SPI1EN_Pos (12U)
1276 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
1277 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
1278 #define RCC_APB2ENR_USART1EN_Pos (14U)
1279 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
1280 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
1287 /***************** Bit definition for RCC_APB1ENR register ******************/
1288 #define RCC_APB1ENR_TIM2EN_Pos (0U)
1289 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)
1290 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk
1291 #define RCC_APB1ENR_TIM3EN_Pos (1U)
1292 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)
1293 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk
1294 #define RCC_APB1ENR_WWDGEN_Pos (11U)
1295 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)
1296 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk
1297 #define RCC_APB1ENR_USART2EN_Pos (17U)
1298 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)
1299 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk
1300 #define RCC_APB1ENR_I2C1EN_Pos (21U)
1301 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)
1302 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk
1304 #define RCC_APB1ENR_CAN1EN_Pos (25U)
1305 #define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)
1306 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk
1308 #define RCC_APB1ENR_BKPEN_Pos (27U)
1309 #define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos)
1310 #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk
1311 #define RCC_APB1ENR_PWREN_Pos (28U)
1312 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)
1313 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk
1316 #define RCC_APB1ENR_USBEN_Pos (23U)
1317 #define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos)
1318 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk
1325 /******************* Bit definition for RCC_BDCR register *******************/
1326 #define RCC_BDCR_LSEON_Pos (0U)
1327 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
1328 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
1329 #define RCC_BDCR_LSERDY_Pos (1U)
1330 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
1331 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
1332 #define RCC_BDCR_LSEBYP_Pos (2U)
1333 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
1334 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
1336 #define RCC_BDCR_RTCSEL_Pos (8U)
1337 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
1338 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
1339 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
1340 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
1343 #define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U
1344 #define RCC_BDCR_RTCSEL_LSE 0x00000100U
1345 #define RCC_BDCR_RTCSEL_LSI 0x00000200U
1346 #define RCC_BDCR_RTCSEL_HSE 0x00000300U
1348 #define RCC_BDCR_RTCEN_Pos (15U)
1349 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
1350 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
1351 #define RCC_BDCR_BDRST_Pos (16U)
1352 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
1353 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
1355 /******************* Bit definition for RCC_CSR register ********************/
1356 #define RCC_CSR_LSION_Pos (0U)
1357 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
1358 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
1359 #define RCC_CSR_LSIRDY_Pos (1U)
1360 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
1361 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
1362 #define RCC_CSR_RMVF_Pos (24U)
1363 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)
1364 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk
1365 #define RCC_CSR_PINRSTF_Pos (26U)
1366 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)
1367 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk
1368 #define RCC_CSR_PORRSTF_Pos (27U)
1369 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)
1370 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk
1371 #define RCC_CSR_SFTRSTF_Pos (28U)
1372 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)
1373 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk
1374 #define RCC_CSR_IWDGRSTF_Pos (29U)
1375 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)
1376 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk
1377 #define RCC_CSR_WWDGRSTF_Pos (30U)
1378 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)
1379 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk
1380 #define RCC_CSR_LPWRRSTF_Pos (31U)
1381 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)
1382 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk
1386 /******************************************************************************/
1387 /* */
1388 /* General Purpose and Alternate Function I/O */
1389 /* */
1390 /******************************************************************************/
1391 
1392 /******************* Bit definition for GPIO_CRL register *******************/
1393 #define GPIO_CRL_MODE_Pos (0U)
1394 #define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos)
1395 #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk
1397 #define GPIO_CRL_MODE0_Pos (0U)
1398 #define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos)
1399 #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk
1400 #define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos)
1401 #define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos)
1403 #define GPIO_CRL_MODE1_Pos (4U)
1404 #define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos)
1405 #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk
1406 #define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos)
1407 #define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos)
1409 #define GPIO_CRL_MODE2_Pos (8U)
1410 #define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos)
1411 #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk
1412 #define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos)
1413 #define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos)
1415 #define GPIO_CRL_MODE3_Pos (12U)
1416 #define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos)
1417 #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk
1418 #define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos)
1419 #define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos)
1421 #define GPIO_CRL_MODE4_Pos (16U)
1422 #define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos)
1423 #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk
1424 #define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos)
1425 #define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos)
1427 #define GPIO_CRL_MODE5_Pos (20U)
1428 #define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos)
1429 #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk
1430 #define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos)
1431 #define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos)
1433 #define GPIO_CRL_MODE6_Pos (24U)
1434 #define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos)
1435 #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk
1436 #define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos)
1437 #define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos)
1439 #define GPIO_CRL_MODE7_Pos (28U)
1440 #define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos)
1441 #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk
1442 #define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos)
1443 #define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos)
1445 #define GPIO_CRL_CNF_Pos (2U)
1446 #define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos)
1447 #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk
1449 #define GPIO_CRL_CNF0_Pos (2U)
1450 #define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos)
1451 #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk
1452 #define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos)
1453 #define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos)
1455 #define GPIO_CRL_CNF1_Pos (6U)
1456 #define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos)
1457 #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk
1458 #define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos)
1459 #define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos)
1461 #define GPIO_CRL_CNF2_Pos (10U)
1462 #define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos)
1463 #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk
1464 #define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos)
1465 #define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos)
1467 #define GPIO_CRL_CNF3_Pos (14U)
1468 #define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos)
1469 #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk
1470 #define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos)
1471 #define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos)
1473 #define GPIO_CRL_CNF4_Pos (18U)
1474 #define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos)
1475 #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk
1476 #define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos)
1477 #define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos)
1479 #define GPIO_CRL_CNF5_Pos (22U)
1480 #define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos)
1481 #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk
1482 #define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos)
1483 #define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos)
1485 #define GPIO_CRL_CNF6_Pos (26U)
1486 #define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos)
1487 #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk
1488 #define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos)
1489 #define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos)
1491 #define GPIO_CRL_CNF7_Pos (30U)
1492 #define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos)
1493 #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk
1494 #define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos)
1495 #define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos)
1497 /******************* Bit definition for GPIO_CRH register *******************/
1498 #define GPIO_CRH_MODE_Pos (0U)
1499 #define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos)
1500 #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk
1502 #define GPIO_CRH_MODE8_Pos (0U)
1503 #define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos)
1504 #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk
1505 #define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos)
1506 #define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos)
1508 #define GPIO_CRH_MODE9_Pos (4U)
1509 #define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos)
1510 #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk
1511 #define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos)
1512 #define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos)
1514 #define GPIO_CRH_MODE10_Pos (8U)
1515 #define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos)
1516 #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk
1517 #define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos)
1518 #define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos)
1520 #define GPIO_CRH_MODE11_Pos (12U)
1521 #define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos)
1522 #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk
1523 #define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos)
1524 #define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos)
1526 #define GPIO_CRH_MODE12_Pos (16U)
1527 #define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos)
1528 #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk
1529 #define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos)
1530 #define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos)
1532 #define GPIO_CRH_MODE13_Pos (20U)
1533 #define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos)
1534 #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk
1535 #define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos)
1536 #define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos)
1538 #define GPIO_CRH_MODE14_Pos (24U)
1539 #define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos)
1540 #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk
1541 #define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos)
1542 #define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos)
1544 #define GPIO_CRH_MODE15_Pos (28U)
1545 #define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos)
1546 #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk
1547 #define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos)
1548 #define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos)
1550 #define GPIO_CRH_CNF_Pos (2U)
1551 #define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos)
1552 #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk
1554 #define GPIO_CRH_CNF8_Pos (2U)
1555 #define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos)
1556 #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk
1557 #define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos)
1558 #define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos)
1560 #define GPIO_CRH_CNF9_Pos (6U)
1561 #define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos)
1562 #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk
1563 #define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos)
1564 #define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos)
1566 #define GPIO_CRH_CNF10_Pos (10U)
1567 #define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos)
1568 #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk
1569 #define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos)
1570 #define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos)
1572 #define GPIO_CRH_CNF11_Pos (14U)
1573 #define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos)
1574 #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk
1575 #define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos)
1576 #define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos)
1578 #define GPIO_CRH_CNF12_Pos (18U)
1579 #define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos)
1580 #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk
1581 #define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos)
1582 #define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos)
1584 #define GPIO_CRH_CNF13_Pos (22U)
1585 #define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos)
1586 #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk
1587 #define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos)
1588 #define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos)
1590 #define GPIO_CRH_CNF14_Pos (26U)
1591 #define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos)
1592 #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk
1593 #define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos)
1594 #define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos)
1596 #define GPIO_CRH_CNF15_Pos (30U)
1597 #define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos)
1598 #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk
1599 #define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos)
1600 #define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos)
1603 #define GPIO_IDR_IDR0_Pos (0U)
1604 #define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos)
1605 #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk
1606 #define GPIO_IDR_IDR1_Pos (1U)
1607 #define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos)
1608 #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk
1609 #define GPIO_IDR_IDR2_Pos (2U)
1610 #define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos)
1611 #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk
1612 #define GPIO_IDR_IDR3_Pos (3U)
1613 #define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos)
1614 #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk
1615 #define GPIO_IDR_IDR4_Pos (4U)
1616 #define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos)
1617 #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk
1618 #define GPIO_IDR_IDR5_Pos (5U)
1619 #define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos)
1620 #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk
1621 #define GPIO_IDR_IDR6_Pos (6U)
1622 #define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos)
1623 #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk
1624 #define GPIO_IDR_IDR7_Pos (7U)
1625 #define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos)
1626 #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk
1627 #define GPIO_IDR_IDR8_Pos (8U)
1628 #define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos)
1629 #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk
1630 #define GPIO_IDR_IDR9_Pos (9U)
1631 #define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos)
1632 #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk
1633 #define GPIO_IDR_IDR10_Pos (10U)
1634 #define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos)
1635 #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk
1636 #define GPIO_IDR_IDR11_Pos (11U)
1637 #define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos)
1638 #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk
1639 #define GPIO_IDR_IDR12_Pos (12U)
1640 #define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos)
1641 #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk
1642 #define GPIO_IDR_IDR13_Pos (13U)
1643 #define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos)
1644 #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk
1645 #define GPIO_IDR_IDR14_Pos (14U)
1646 #define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos)
1647 #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk
1648 #define GPIO_IDR_IDR15_Pos (15U)
1649 #define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos)
1650 #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk
1652 /******************* Bit definition for GPIO_ODR register *******************/
1653 #define GPIO_ODR_ODR0_Pos (0U)
1654 #define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos)
1655 #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk
1656 #define GPIO_ODR_ODR1_Pos (1U)
1657 #define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos)
1658 #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk
1659 #define GPIO_ODR_ODR2_Pos (2U)
1660 #define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos)
1661 #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk
1662 #define GPIO_ODR_ODR3_Pos (3U)
1663 #define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos)
1664 #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk
1665 #define GPIO_ODR_ODR4_Pos (4U)
1666 #define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos)
1667 #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk
1668 #define GPIO_ODR_ODR5_Pos (5U)
1669 #define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos)
1670 #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk
1671 #define GPIO_ODR_ODR6_Pos (6U)
1672 #define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos)
1673 #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk
1674 #define GPIO_ODR_ODR7_Pos (7U)
1675 #define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos)
1676 #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk
1677 #define GPIO_ODR_ODR8_Pos (8U)
1678 #define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos)
1679 #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk
1680 #define GPIO_ODR_ODR9_Pos (9U)
1681 #define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos)
1682 #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk
1683 #define GPIO_ODR_ODR10_Pos (10U)
1684 #define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos)
1685 #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk
1686 #define GPIO_ODR_ODR11_Pos (11U)
1687 #define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos)
1688 #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk
1689 #define GPIO_ODR_ODR12_Pos (12U)
1690 #define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos)
1691 #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk
1692 #define GPIO_ODR_ODR13_Pos (13U)
1693 #define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos)
1694 #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk
1695 #define GPIO_ODR_ODR14_Pos (14U)
1696 #define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos)
1697 #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk
1698 #define GPIO_ODR_ODR15_Pos (15U)
1699 #define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos)
1700 #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk
1702 /****************** Bit definition for GPIO_BSRR register *******************/
1703 #define GPIO_BSRR_BS0_Pos (0U)
1704 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
1705 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
1706 #define GPIO_BSRR_BS1_Pos (1U)
1707 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
1708 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
1709 #define GPIO_BSRR_BS2_Pos (2U)
1710 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
1711 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
1712 #define GPIO_BSRR_BS3_Pos (3U)
1713 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
1714 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
1715 #define GPIO_BSRR_BS4_Pos (4U)
1716 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
1717 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
1718 #define GPIO_BSRR_BS5_Pos (5U)
1719 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
1720 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
1721 #define GPIO_BSRR_BS6_Pos (6U)
1722 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
1723 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
1724 #define GPIO_BSRR_BS7_Pos (7U)
1725 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
1726 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
1727 #define GPIO_BSRR_BS8_Pos (8U)
1728 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
1729 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
1730 #define GPIO_BSRR_BS9_Pos (9U)
1731 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
1732 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
1733 #define GPIO_BSRR_BS10_Pos (10U)
1734 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
1735 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
1736 #define GPIO_BSRR_BS11_Pos (11U)
1737 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
1738 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
1739 #define GPIO_BSRR_BS12_Pos (12U)
1740 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
1741 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
1742 #define GPIO_BSRR_BS13_Pos (13U)
1743 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
1744 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
1745 #define GPIO_BSRR_BS14_Pos (14U)
1746 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
1747 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
1748 #define GPIO_BSRR_BS15_Pos (15U)
1749 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
1750 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
1752 #define GPIO_BSRR_BR0_Pos (16U)
1753 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
1754 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
1755 #define GPIO_BSRR_BR1_Pos (17U)
1756 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
1757 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
1758 #define GPIO_BSRR_BR2_Pos (18U)
1759 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
1760 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
1761 #define GPIO_BSRR_BR3_Pos (19U)
1762 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
1763 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
1764 #define GPIO_BSRR_BR4_Pos (20U)
1765 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
1766 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
1767 #define GPIO_BSRR_BR5_Pos (21U)
1768 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
1769 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
1770 #define GPIO_BSRR_BR6_Pos (22U)
1771 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
1772 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
1773 #define GPIO_BSRR_BR7_Pos (23U)
1774 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
1775 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
1776 #define GPIO_BSRR_BR8_Pos (24U)
1777 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
1778 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
1779 #define GPIO_BSRR_BR9_Pos (25U)
1780 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
1781 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
1782 #define GPIO_BSRR_BR10_Pos (26U)
1783 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
1784 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
1785 #define GPIO_BSRR_BR11_Pos (27U)
1786 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
1787 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
1788 #define GPIO_BSRR_BR12_Pos (28U)
1789 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
1790 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
1791 #define GPIO_BSRR_BR13_Pos (29U)
1792 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
1793 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
1794 #define GPIO_BSRR_BR14_Pos (30U)
1795 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
1796 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
1797 #define GPIO_BSRR_BR15_Pos (31U)
1798 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
1799 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
1801 /******************* Bit definition for GPIO_BRR register *******************/
1802 #define GPIO_BRR_BR0_Pos (0U)
1803 #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos)
1804 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk
1805 #define GPIO_BRR_BR1_Pos (1U)
1806 #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos)
1807 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk
1808 #define GPIO_BRR_BR2_Pos (2U)
1809 #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos)
1810 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk
1811 #define GPIO_BRR_BR3_Pos (3U)
1812 #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos)
1813 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk
1814 #define GPIO_BRR_BR4_Pos (4U)
1815 #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos)
1816 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk
1817 #define GPIO_BRR_BR5_Pos (5U)
1818 #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos)
1819 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk
1820 #define GPIO_BRR_BR6_Pos (6U)
1821 #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos)
1822 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk
1823 #define GPIO_BRR_BR7_Pos (7U)
1824 #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos)
1825 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk
1826 #define GPIO_BRR_BR8_Pos (8U)
1827 #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos)
1828 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk
1829 #define GPIO_BRR_BR9_Pos (9U)
1830 #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos)
1831 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk
1832 #define GPIO_BRR_BR10_Pos (10U)
1833 #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos)
1834 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk
1835 #define GPIO_BRR_BR11_Pos (11U)
1836 #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos)
1837 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk
1838 #define GPIO_BRR_BR12_Pos (12U)
1839 #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos)
1840 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk
1841 #define GPIO_BRR_BR13_Pos (13U)
1842 #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos)
1843 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk
1844 #define GPIO_BRR_BR14_Pos (14U)
1845 #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos)
1846 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk
1847 #define GPIO_BRR_BR15_Pos (15U)
1848 #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos)
1849 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk
1851 /****************** Bit definition for GPIO_LCKR register *******************/
1852 #define GPIO_LCKR_LCK0_Pos (0U)
1853 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
1854 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
1855 #define GPIO_LCKR_LCK1_Pos (1U)
1856 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
1857 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
1858 #define GPIO_LCKR_LCK2_Pos (2U)
1859 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
1860 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
1861 #define GPIO_LCKR_LCK3_Pos (3U)
1862 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
1863 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
1864 #define GPIO_LCKR_LCK4_Pos (4U)
1865 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
1866 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
1867 #define GPIO_LCKR_LCK5_Pos (5U)
1868 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
1869 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
1870 #define GPIO_LCKR_LCK6_Pos (6U)
1871 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
1872 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
1873 #define GPIO_LCKR_LCK7_Pos (7U)
1874 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
1875 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
1876 #define GPIO_LCKR_LCK8_Pos (8U)
1877 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
1878 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
1879 #define GPIO_LCKR_LCK9_Pos (9U)
1880 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
1881 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
1882 #define GPIO_LCKR_LCK10_Pos (10U)
1883 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
1884 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
1885 #define GPIO_LCKR_LCK11_Pos (11U)
1886 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
1887 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
1888 #define GPIO_LCKR_LCK12_Pos (12U)
1889 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
1890 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
1891 #define GPIO_LCKR_LCK13_Pos (13U)
1892 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
1893 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
1894 #define GPIO_LCKR_LCK14_Pos (14U)
1895 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
1896 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
1897 #define GPIO_LCKR_LCK15_Pos (15U)
1898 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
1899 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
1900 #define GPIO_LCKR_LCKK_Pos (16U)
1901 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
1902 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
1904 /*----------------------------------------------------------------------------*/
1905 
1906 /****************** Bit definition for AFIO_EVCR register *******************/
1907 #define AFIO_EVCR_PIN_Pos (0U)
1908 #define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos)
1909 #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk
1910 #define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos)
1911 #define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos)
1912 #define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos)
1913 #define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos)
1916 #define AFIO_EVCR_PIN_PX0 0x00000000U
1917 #define AFIO_EVCR_PIN_PX1_Pos (0U)
1918 #define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos)
1919 #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk
1920 #define AFIO_EVCR_PIN_PX2_Pos (1U)
1921 #define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos)
1922 #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk
1923 #define AFIO_EVCR_PIN_PX3_Pos (0U)
1924 #define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos)
1925 #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk
1926 #define AFIO_EVCR_PIN_PX4_Pos (2U)
1927 #define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos)
1928 #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk
1929 #define AFIO_EVCR_PIN_PX5_Pos (0U)
1930 #define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos)
1931 #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk
1932 #define AFIO_EVCR_PIN_PX6_Pos (1U)
1933 #define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos)
1934 #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk
1935 #define AFIO_EVCR_PIN_PX7_Pos (0U)
1936 #define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos)
1937 #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk
1938 #define AFIO_EVCR_PIN_PX8_Pos (3U)
1939 #define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos)
1940 #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk
1941 #define AFIO_EVCR_PIN_PX9_Pos (0U)
1942 #define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos)
1943 #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk
1944 #define AFIO_EVCR_PIN_PX10_Pos (1U)
1945 #define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos)
1946 #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk
1947 #define AFIO_EVCR_PIN_PX11_Pos (0U)
1948 #define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos)
1949 #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk
1950 #define AFIO_EVCR_PIN_PX12_Pos (2U)
1951 #define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos)
1952 #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk
1953 #define AFIO_EVCR_PIN_PX13_Pos (0U)
1954 #define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos)
1955 #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk
1956 #define AFIO_EVCR_PIN_PX14_Pos (1U)
1957 #define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos)
1958 #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk
1959 #define AFIO_EVCR_PIN_PX15_Pos (0U)
1960 #define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos)
1961 #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk
1963 #define AFIO_EVCR_PORT_Pos (4U)
1964 #define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos)
1965 #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk
1966 #define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos)
1967 #define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos)
1968 #define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos)
1971 #define AFIO_EVCR_PORT_PA 0x00000000
1972 #define AFIO_EVCR_PORT_PB_Pos (4U)
1973 #define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos)
1974 #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk
1975 #define AFIO_EVCR_PORT_PC_Pos (5U)
1976 #define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos)
1977 #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk
1978 #define AFIO_EVCR_PORT_PD_Pos (4U)
1979 #define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos)
1980 #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk
1981 #define AFIO_EVCR_PORT_PE_Pos (6U)
1982 #define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos)
1983 #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk
1985 #define AFIO_EVCR_EVOE_Pos (7U)
1986 #define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos)
1987 #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk
1989 /****************** Bit definition for AFIO_MAPR register *******************/
1990 #define AFIO_MAPR_SPI1_REMAP_Pos (0U)
1991 #define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos)
1992 #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk
1993 #define AFIO_MAPR_I2C1_REMAP_Pos (1U)
1994 #define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos)
1995 #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk
1996 #define AFIO_MAPR_USART1_REMAP_Pos (2U)
1997 #define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos)
1998 #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk
1999 #define AFIO_MAPR_USART2_REMAP_Pos (3U)
2000 #define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos)
2001 #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk
2004 #define AFIO_MAPR_TIM1_REMAP_Pos (6U)
2005 #define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos)
2006 #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk
2007 #define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos)
2008 #define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos)
2011 #define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U
2012 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
2013 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos)
2014 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk
2015 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
2016 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos)
2017 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk
2019 #define AFIO_MAPR_TIM2_REMAP_Pos (8U)
2020 #define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos)
2021 #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk
2022 #define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos)
2023 #define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos)
2026 #define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U
2027 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
2028 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos)
2029 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk
2030 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
2031 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos)
2032 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk
2033 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
2034 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos)
2035 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk
2037 #define AFIO_MAPR_TIM3_REMAP_Pos (10U)
2038 #define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos)
2039 #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk
2040 #define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos)
2041 #define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos)
2044 #define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U
2045 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
2046 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos)
2047 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk
2048 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
2049 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos)
2050 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk
2053 #define AFIO_MAPR_CAN_REMAP_Pos (13U)
2054 #define AFIO_MAPR_CAN_REMAP_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_Pos)
2055 #define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk
2056 #define AFIO_MAPR_CAN_REMAP_0 (0x1UL << AFIO_MAPR_CAN_REMAP_Pos)
2057 #define AFIO_MAPR_CAN_REMAP_1 (0x2UL << AFIO_MAPR_CAN_REMAP_Pos)
2060 #define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U
2061 #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
2062 #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos)
2063 #define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk
2064 #define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
2065 #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos)
2066 #define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk
2068 #define AFIO_MAPR_PD01_REMAP_Pos (15U)
2069 #define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos)
2070 #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk
2073 #define AFIO_MAPR_SWJ_CFG_Pos (24U)
2074 #define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos)
2075 #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk
2076 #define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos)
2077 #define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos)
2078 #define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos)
2080 #define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U
2081 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
2082 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos)
2083 #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk
2084 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
2085 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos)
2086 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk
2087 #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
2088 #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos)
2089 #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk
2092 /***************** Bit definition for AFIO_EXTICR1 register *****************/
2093 #define AFIO_EXTICR1_EXTI0_Pos (0U)
2094 #define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos)
2095 #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk
2096 #define AFIO_EXTICR1_EXTI1_Pos (4U)
2097 #define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos)
2098 #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk
2099 #define AFIO_EXTICR1_EXTI2_Pos (8U)
2100 #define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos)
2101 #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk
2102 #define AFIO_EXTICR1_EXTI3_Pos (12U)
2103 #define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos)
2104 #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk
2107 #define AFIO_EXTICR1_EXTI0_PA 0x00000000U
2108 #define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
2109 #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos)
2110 #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk
2111 #define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
2112 #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos)
2113 #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk
2114 #define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
2115 #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos)
2116 #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk
2117 #define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
2118 #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos)
2119 #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk
2120 #define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
2121 #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos)
2122 #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk
2123 #define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
2124 #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos)
2125 #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk
2128 #define AFIO_EXTICR1_EXTI1_PA 0x00000000U
2129 #define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
2130 #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos)
2131 #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk
2132 #define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
2133 #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos)
2134 #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk
2135 #define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
2136 #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos)
2137 #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk
2138 #define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
2139 #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos)
2140 #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk
2141 #define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
2142 #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos)
2143 #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk
2144 #define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
2145 #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos)
2146 #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk
2149 #define AFIO_EXTICR1_EXTI2_PA 0x00000000U
2150 #define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
2151 #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos)
2152 #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk
2153 #define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
2154 #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos)
2155 #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk
2156 #define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
2157 #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos)
2158 #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk
2159 #define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
2160 #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos)
2161 #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk
2162 #define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
2163 #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos)
2164 #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk
2165 #define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
2166 #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos)
2167 #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk
2170 #define AFIO_EXTICR1_EXTI3_PA 0x00000000U
2171 #define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
2172 #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos)
2173 #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk
2174 #define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
2175 #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos)
2176 #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk
2177 #define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
2178 #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos)
2179 #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk
2180 #define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
2181 #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos)
2182 #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk
2183 #define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
2184 #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos)
2185 #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk
2186 #define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
2187 #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos)
2188 #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk
2190 /***************** Bit definition for AFIO_EXTICR2 register *****************/
2191 #define AFIO_EXTICR2_EXTI4_Pos (0U)
2192 #define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos)
2193 #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk
2194 #define AFIO_EXTICR2_EXTI5_Pos (4U)
2195 #define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos)
2196 #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk
2197 #define AFIO_EXTICR2_EXTI6_Pos (8U)
2198 #define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos)
2199 #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk
2200 #define AFIO_EXTICR2_EXTI7_Pos (12U)
2201 #define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos)
2202 #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk
2205 #define AFIO_EXTICR2_EXTI4_PA 0x00000000U
2206 #define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
2207 #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos)
2208 #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk
2209 #define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
2210 #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos)
2211 #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk
2212 #define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
2213 #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos)
2214 #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk
2215 #define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
2216 #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos)
2217 #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk
2218 #define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
2219 #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos)
2220 #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk
2221 #define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
2222 #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos)
2223 #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk
2225 /* EXTI5 configuration */
2226 #define AFIO_EXTICR2_EXTI5_PA 0x00000000U
2227 #define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
2228 #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos)
2229 #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk
2230 #define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
2231 #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos)
2232 #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk
2233 #define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
2234 #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos)
2235 #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk
2236 #define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
2237 #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos)
2238 #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk
2239 #define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
2240 #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos)
2241 #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk
2242 #define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
2243 #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos)
2244 #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk
2247 #define AFIO_EXTICR2_EXTI6_PA 0x00000000U
2248 #define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
2249 #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos)
2250 #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk
2251 #define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
2252 #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos)
2253 #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk
2254 #define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
2255 #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos)
2256 #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk
2257 #define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
2258 #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos)
2259 #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk
2260 #define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
2261 #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos)
2262 #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk
2263 #define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
2264 #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos)
2265 #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk
2268 #define AFIO_EXTICR2_EXTI7_PA 0x00000000U
2269 #define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
2270 #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos)
2271 #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk
2272 #define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
2273 #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos)
2274 #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk
2275 #define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
2276 #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos)
2277 #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk
2278 #define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
2279 #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos)
2280 #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk
2281 #define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
2282 #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos)
2283 #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk
2284 #define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
2285 #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos)
2286 #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk
2288 /***************** Bit definition for AFIO_EXTICR3 register *****************/
2289 #define AFIO_EXTICR3_EXTI8_Pos (0U)
2290 #define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos)
2291 #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk
2292 #define AFIO_EXTICR3_EXTI9_Pos (4U)
2293 #define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos)
2294 #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk
2295 #define AFIO_EXTICR3_EXTI10_Pos (8U)
2296 #define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos)
2297 #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk
2298 #define AFIO_EXTICR3_EXTI11_Pos (12U)
2299 #define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos)
2300 #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk
2303 #define AFIO_EXTICR3_EXTI8_PA 0x00000000U
2304 #define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
2305 #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos)
2306 #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk
2307 #define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
2308 #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos)
2309 #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk
2310 #define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
2311 #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos)
2312 #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk
2313 #define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
2314 #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos)
2315 #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk
2316 #define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
2317 #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos)
2318 #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk
2319 #define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
2320 #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos)
2321 #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk
2324 #define AFIO_EXTICR3_EXTI9_PA 0x00000000U
2325 #define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
2326 #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos)
2327 #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk
2328 #define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
2329 #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos)
2330 #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk
2331 #define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
2332 #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos)
2333 #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk
2334 #define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
2335 #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos)
2336 #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk
2337 #define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
2338 #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos)
2339 #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk
2340 #define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
2341 #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos)
2342 #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk
2345 #define AFIO_EXTICR3_EXTI10_PA 0x00000000U
2346 #define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
2347 #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos)
2348 #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk
2349 #define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
2350 #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos)
2351 #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk
2352 #define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
2353 #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos)
2354 #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk
2355 #define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
2356 #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos)
2357 #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk
2358 #define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
2359 #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos)
2360 #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk
2361 #define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
2362 #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos)
2363 #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk
2366 #define AFIO_EXTICR3_EXTI11_PA 0x00000000U
2367 #define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
2368 #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos)
2369 #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk
2370 #define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
2371 #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos)
2372 #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk
2373 #define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
2374 #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos)
2375 #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk
2376 #define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
2377 #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos)
2378 #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk
2379 #define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
2380 #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos)
2381 #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk
2382 #define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
2383 #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos)
2384 #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk
2386 /***************** Bit definition for AFIO_EXTICR4 register *****************/
2387 #define AFIO_EXTICR4_EXTI12_Pos (0U)
2388 #define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos)
2389 #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk
2390 #define AFIO_EXTICR4_EXTI13_Pos (4U)
2391 #define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos)
2392 #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk
2393 #define AFIO_EXTICR4_EXTI14_Pos (8U)
2394 #define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos)
2395 #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk
2396 #define AFIO_EXTICR4_EXTI15_Pos (12U)
2397 #define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos)
2398 #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk
2400 /* EXTI12 configuration */
2401 #define AFIO_EXTICR4_EXTI12_PA 0x00000000U
2402 #define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
2403 #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos)
2404 #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk
2405 #define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
2406 #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos)
2407 #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk
2408 #define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
2409 #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos)
2410 #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk
2411 #define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
2412 #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos)
2413 #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk
2414 #define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
2415 #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos)
2416 #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk
2417 #define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
2418 #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos)
2419 #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk
2421 /* EXTI13 configuration */
2422 #define AFIO_EXTICR4_EXTI13_PA 0x00000000U
2423 #define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
2424 #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos)
2425 #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk
2426 #define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
2427 #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos)
2428 #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk
2429 #define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
2430 #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos)
2431 #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk
2432 #define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
2433 #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos)
2434 #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk
2435 #define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
2436 #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos)
2437 #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk
2438 #define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
2439 #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos)
2440 #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk
2443 #define AFIO_EXTICR4_EXTI14_PA 0x00000000U
2444 #define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
2445 #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos)
2446 #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk
2447 #define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
2448 #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos)
2449 #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk
2450 #define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
2451 #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos)
2452 #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk
2453 #define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
2454 #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos)
2455 #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk
2456 #define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
2457 #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos)
2458 #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk
2459 #define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
2460 #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos)
2461 #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk
2464 #define AFIO_EXTICR4_EXTI15_PA 0x00000000U
2465 #define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
2466 #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos)
2467 #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk
2468 #define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
2469 #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos)
2470 #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk
2471 #define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
2472 #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos)
2473 #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk
2474 #define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
2475 #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos)
2476 #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk
2477 #define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
2478 #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos)
2479 #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk
2480 #define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
2481 #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos)
2482 #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk
2484 /****************** Bit definition for AFIO_MAPR2 register ******************/
2485 
2486 
2487 
2488 /******************************************************************************/
2489 /* */
2490 /* External Interrupt/Event Controller */
2491 /* */
2492 /******************************************************************************/
2493 
2494 /******************* Bit definition for EXTI_IMR register *******************/
2495 #define EXTI_IMR_MR0_Pos (0U)
2496 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)
2497 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk
2498 #define EXTI_IMR_MR1_Pos (1U)
2499 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)
2500 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk
2501 #define EXTI_IMR_MR2_Pos (2U)
2502 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)
2503 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk
2504 #define EXTI_IMR_MR3_Pos (3U)
2505 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)
2506 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk
2507 #define EXTI_IMR_MR4_Pos (4U)
2508 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)
2509 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk
2510 #define EXTI_IMR_MR5_Pos (5U)
2511 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)
2512 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk
2513 #define EXTI_IMR_MR6_Pos (6U)
2514 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)
2515 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk
2516 #define EXTI_IMR_MR7_Pos (7U)
2517 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)
2518 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk
2519 #define EXTI_IMR_MR8_Pos (8U)
2520 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)
2521 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk
2522 #define EXTI_IMR_MR9_Pos (9U)
2523 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)
2524 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk
2525 #define EXTI_IMR_MR10_Pos (10U)
2526 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)
2527 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk
2528 #define EXTI_IMR_MR11_Pos (11U)
2529 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)
2530 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk
2531 #define EXTI_IMR_MR12_Pos (12U)
2532 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)
2533 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk
2534 #define EXTI_IMR_MR13_Pos (13U)
2535 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)
2536 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk
2537 #define EXTI_IMR_MR14_Pos (14U)
2538 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)
2539 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk
2540 #define EXTI_IMR_MR15_Pos (15U)
2541 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)
2542 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk
2543 #define EXTI_IMR_MR16_Pos (16U)
2544 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)
2545 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk
2546 #define EXTI_IMR_MR17_Pos (17U)
2547 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)
2548 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk
2549 #define EXTI_IMR_MR18_Pos (18U)
2550 #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)
2551 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk
2553 /* References Defines */
2554 #define EXTI_IMR_IM0 EXTI_IMR_MR0
2555 #define EXTI_IMR_IM1 EXTI_IMR_MR1
2556 #define EXTI_IMR_IM2 EXTI_IMR_MR2
2557 #define EXTI_IMR_IM3 EXTI_IMR_MR3
2558 #define EXTI_IMR_IM4 EXTI_IMR_MR4
2559 #define EXTI_IMR_IM5 EXTI_IMR_MR5
2560 #define EXTI_IMR_IM6 EXTI_IMR_MR6
2561 #define EXTI_IMR_IM7 EXTI_IMR_MR7
2562 #define EXTI_IMR_IM8 EXTI_IMR_MR8
2563 #define EXTI_IMR_IM9 EXTI_IMR_MR9
2564 #define EXTI_IMR_IM10 EXTI_IMR_MR10
2565 #define EXTI_IMR_IM11 EXTI_IMR_MR11
2566 #define EXTI_IMR_IM12 EXTI_IMR_MR12
2567 #define EXTI_IMR_IM13 EXTI_IMR_MR13
2568 #define EXTI_IMR_IM14 EXTI_IMR_MR14
2569 #define EXTI_IMR_IM15 EXTI_IMR_MR15
2570 #define EXTI_IMR_IM16 EXTI_IMR_MR16
2571 #define EXTI_IMR_IM17 EXTI_IMR_MR17
2572 #define EXTI_IMR_IM18 EXTI_IMR_MR18
2573 #define EXTI_IMR_IM 0x0007FFFFU
2575 /******************* Bit definition for EXTI_EMR register *******************/
2576 #define EXTI_EMR_MR0_Pos (0U)
2577 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)
2578 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk
2579 #define EXTI_EMR_MR1_Pos (1U)
2580 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)
2581 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk
2582 #define EXTI_EMR_MR2_Pos (2U)
2583 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)
2584 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk
2585 #define EXTI_EMR_MR3_Pos (3U)
2586 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)
2587 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk
2588 #define EXTI_EMR_MR4_Pos (4U)
2589 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)
2590 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk
2591 #define EXTI_EMR_MR5_Pos (5U)
2592 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)
2593 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk
2594 #define EXTI_EMR_MR6_Pos (6U)
2595 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)
2596 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk
2597 #define EXTI_EMR_MR7_Pos (7U)
2598 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)
2599 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk
2600 #define EXTI_EMR_MR8_Pos (8U)
2601 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)
2602 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk
2603 #define EXTI_EMR_MR9_Pos (9U)
2604 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)
2605 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk
2606 #define EXTI_EMR_MR10_Pos (10U)
2607 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)
2608 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk
2609 #define EXTI_EMR_MR11_Pos (11U)
2610 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)
2611 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk
2612 #define EXTI_EMR_MR12_Pos (12U)
2613 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)
2614 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk
2615 #define EXTI_EMR_MR13_Pos (13U)
2616 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)
2617 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk
2618 #define EXTI_EMR_MR14_Pos (14U)
2619 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)
2620 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk
2621 #define EXTI_EMR_MR15_Pos (15U)
2622 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)
2623 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk
2624 #define EXTI_EMR_MR16_Pos (16U)
2625 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)
2626 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk
2627 #define EXTI_EMR_MR17_Pos (17U)
2628 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)
2629 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk
2630 #define EXTI_EMR_MR18_Pos (18U)
2631 #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)
2632 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk
2634 /* References Defines */
2635 #define EXTI_EMR_EM0 EXTI_EMR_MR0
2636 #define EXTI_EMR_EM1 EXTI_EMR_MR1
2637 #define EXTI_EMR_EM2 EXTI_EMR_MR2
2638 #define EXTI_EMR_EM3 EXTI_EMR_MR3
2639 #define EXTI_EMR_EM4 EXTI_EMR_MR4
2640 #define EXTI_EMR_EM5 EXTI_EMR_MR5
2641 #define EXTI_EMR_EM6 EXTI_EMR_MR6
2642 #define EXTI_EMR_EM7 EXTI_EMR_MR7
2643 #define EXTI_EMR_EM8 EXTI_EMR_MR8
2644 #define EXTI_EMR_EM9 EXTI_EMR_MR9
2645 #define EXTI_EMR_EM10 EXTI_EMR_MR10
2646 #define EXTI_EMR_EM11 EXTI_EMR_MR11
2647 #define EXTI_EMR_EM12 EXTI_EMR_MR12
2648 #define EXTI_EMR_EM13 EXTI_EMR_MR13
2649 #define EXTI_EMR_EM14 EXTI_EMR_MR14
2650 #define EXTI_EMR_EM15 EXTI_EMR_MR15
2651 #define EXTI_EMR_EM16 EXTI_EMR_MR16
2652 #define EXTI_EMR_EM17 EXTI_EMR_MR17
2653 #define EXTI_EMR_EM18 EXTI_EMR_MR18
2654 
2655 /****************** Bit definition for EXTI_RTSR register *******************/
2656 #define EXTI_RTSR_TR0_Pos (0U)
2657 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)
2658 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk
2659 #define EXTI_RTSR_TR1_Pos (1U)
2660 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)
2661 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk
2662 #define EXTI_RTSR_TR2_Pos (2U)
2663 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)
2664 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk
2665 #define EXTI_RTSR_TR3_Pos (3U)
2666 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)
2667 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk
2668 #define EXTI_RTSR_TR4_Pos (4U)
2669 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)
2670 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk
2671 #define EXTI_RTSR_TR5_Pos (5U)
2672 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)
2673 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk
2674 #define EXTI_RTSR_TR6_Pos (6U)
2675 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)
2676 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk
2677 #define EXTI_RTSR_TR7_Pos (7U)
2678 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)
2679 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk
2680 #define EXTI_RTSR_TR8_Pos (8U)
2681 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)
2682 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk
2683 #define EXTI_RTSR_TR9_Pos (9U)
2684 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)
2685 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk
2686 #define EXTI_RTSR_TR10_Pos (10U)
2687 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)
2688 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk
2689 #define EXTI_RTSR_TR11_Pos (11U)
2690 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)
2691 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk
2692 #define EXTI_RTSR_TR12_Pos (12U)
2693 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)
2694 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk
2695 #define EXTI_RTSR_TR13_Pos (13U)
2696 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)
2697 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk
2698 #define EXTI_RTSR_TR14_Pos (14U)
2699 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)
2700 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk
2701 #define EXTI_RTSR_TR15_Pos (15U)
2702 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)
2703 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk
2704 #define EXTI_RTSR_TR16_Pos (16U)
2705 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)
2706 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk
2707 #define EXTI_RTSR_TR17_Pos (17U)
2708 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)
2709 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk
2710 #define EXTI_RTSR_TR18_Pos (18U)
2711 #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)
2712 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk
2714 /* References Defines */
2715 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
2716 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
2717 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
2718 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
2719 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
2720 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
2721 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
2722 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
2723 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
2724 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
2725 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
2726 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
2727 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
2728 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
2729 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
2730 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
2731 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
2732 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
2733 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
2734 
2735 /****************** Bit definition for EXTI_FTSR register *******************/
2736 #define EXTI_FTSR_TR0_Pos (0U)
2737 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)
2738 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk
2739 #define EXTI_FTSR_TR1_Pos (1U)
2740 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)
2741 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk
2742 #define EXTI_FTSR_TR2_Pos (2U)
2743 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)
2744 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk
2745 #define EXTI_FTSR_TR3_Pos (3U)
2746 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)
2747 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk
2748 #define EXTI_FTSR_TR4_Pos (4U)
2749 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)
2750 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk
2751 #define EXTI_FTSR_TR5_Pos (5U)
2752 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)
2753 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk
2754 #define EXTI_FTSR_TR6_Pos (6U)
2755 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)
2756 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk
2757 #define EXTI_FTSR_TR7_Pos (7U)
2758 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)
2759 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk
2760 #define EXTI_FTSR_TR8_Pos (8U)
2761 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)
2762 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk
2763 #define EXTI_FTSR_TR9_Pos (9U)
2764 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)
2765 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk
2766 #define EXTI_FTSR_TR10_Pos (10U)
2767 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)
2768 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk
2769 #define EXTI_FTSR_TR11_Pos (11U)
2770 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)
2771 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk
2772 #define EXTI_FTSR_TR12_Pos (12U)
2773 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)
2774 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk
2775 #define EXTI_FTSR_TR13_Pos (13U)
2776 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)
2777 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk
2778 #define EXTI_FTSR_TR14_Pos (14U)
2779 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)
2780 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk
2781 #define EXTI_FTSR_TR15_Pos (15U)
2782 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)
2783 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk
2784 #define EXTI_FTSR_TR16_Pos (16U)
2785 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)
2786 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk
2787 #define EXTI_FTSR_TR17_Pos (17U)
2788 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)
2789 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk
2790 #define EXTI_FTSR_TR18_Pos (18U)
2791 #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)
2792 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk
2794 /* References Defines */
2795 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
2796 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
2797 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
2798 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
2799 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
2800 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
2801 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
2802 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
2803 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
2804 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
2805 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
2806 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
2807 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
2808 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
2809 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
2810 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
2811 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
2812 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
2813 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
2814 
2815 /****************** Bit definition for EXTI_SWIER register ******************/
2816 #define EXTI_SWIER_SWIER0_Pos (0U)
2817 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)
2818 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk
2819 #define EXTI_SWIER_SWIER1_Pos (1U)
2820 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)
2821 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk
2822 #define EXTI_SWIER_SWIER2_Pos (2U)
2823 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)
2824 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk
2825 #define EXTI_SWIER_SWIER3_Pos (3U)
2826 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)
2827 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk
2828 #define EXTI_SWIER_SWIER4_Pos (4U)
2829 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)
2830 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk
2831 #define EXTI_SWIER_SWIER5_Pos (5U)
2832 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)
2833 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk
2834 #define EXTI_SWIER_SWIER6_Pos (6U)
2835 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)
2836 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk
2837 #define EXTI_SWIER_SWIER7_Pos (7U)
2838 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)
2839 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk
2840 #define EXTI_SWIER_SWIER8_Pos (8U)
2841 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)
2842 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk
2843 #define EXTI_SWIER_SWIER9_Pos (9U)
2844 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)
2845 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk
2846 #define EXTI_SWIER_SWIER10_Pos (10U)
2847 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)
2848 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk
2849 #define EXTI_SWIER_SWIER11_Pos (11U)
2850 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)
2851 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk
2852 #define EXTI_SWIER_SWIER12_Pos (12U)
2853 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)
2854 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk
2855 #define EXTI_SWIER_SWIER13_Pos (13U)
2856 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)
2857 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk
2858 #define EXTI_SWIER_SWIER14_Pos (14U)
2859 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)
2860 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk
2861 #define EXTI_SWIER_SWIER15_Pos (15U)
2862 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)
2863 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk
2864 #define EXTI_SWIER_SWIER16_Pos (16U)
2865 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)
2866 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk
2867 #define EXTI_SWIER_SWIER17_Pos (17U)
2868 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)
2869 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk
2870 #define EXTI_SWIER_SWIER18_Pos (18U)
2871 #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)
2872 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk
2874 /* References Defines */
2875 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
2876 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
2877 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
2878 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
2879 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
2880 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
2881 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
2882 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
2883 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
2884 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
2885 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
2886 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
2887 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
2888 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
2889 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
2890 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
2891 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
2892 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
2893 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
2894 
2895 /******************* Bit definition for EXTI_PR register ********************/
2896 #define EXTI_PR_PR0_Pos (0U)
2897 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)
2898 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk
2899 #define EXTI_PR_PR1_Pos (1U)
2900 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)
2901 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk
2902 #define EXTI_PR_PR2_Pos (2U)
2903 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)
2904 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk
2905 #define EXTI_PR_PR3_Pos (3U)
2906 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)
2907 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk
2908 #define EXTI_PR_PR4_Pos (4U)
2909 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)
2910 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk
2911 #define EXTI_PR_PR5_Pos (5U)
2912 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)
2913 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk
2914 #define EXTI_PR_PR6_Pos (6U)
2915 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)
2916 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk
2917 #define EXTI_PR_PR7_Pos (7U)
2918 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)
2919 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk
2920 #define EXTI_PR_PR8_Pos (8U)
2921 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)
2922 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk
2923 #define EXTI_PR_PR9_Pos (9U)
2924 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)
2925 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk
2926 #define EXTI_PR_PR10_Pos (10U)
2927 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)
2928 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk
2929 #define EXTI_PR_PR11_Pos (11U)
2930 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)
2931 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk
2932 #define EXTI_PR_PR12_Pos (12U)
2933 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)
2934 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk
2935 #define EXTI_PR_PR13_Pos (13U)
2936 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)
2937 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk
2938 #define EXTI_PR_PR14_Pos (14U)
2939 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)
2940 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk
2941 #define EXTI_PR_PR15_Pos (15U)
2942 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)
2943 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk
2944 #define EXTI_PR_PR16_Pos (16U)
2945 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)
2946 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk
2947 #define EXTI_PR_PR17_Pos (17U)
2948 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)
2949 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk
2950 #define EXTI_PR_PR18_Pos (18U)
2951 #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)
2952 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk
2954 /* References Defines */
2955 #define EXTI_PR_PIF0 EXTI_PR_PR0
2956 #define EXTI_PR_PIF1 EXTI_PR_PR1
2957 #define EXTI_PR_PIF2 EXTI_PR_PR2
2958 #define EXTI_PR_PIF3 EXTI_PR_PR3
2959 #define EXTI_PR_PIF4 EXTI_PR_PR4
2960 #define EXTI_PR_PIF5 EXTI_PR_PR5
2961 #define EXTI_PR_PIF6 EXTI_PR_PR6
2962 #define EXTI_PR_PIF7 EXTI_PR_PR7
2963 #define EXTI_PR_PIF8 EXTI_PR_PR8
2964 #define EXTI_PR_PIF9 EXTI_PR_PR9
2965 #define EXTI_PR_PIF10 EXTI_PR_PR10
2966 #define EXTI_PR_PIF11 EXTI_PR_PR11
2967 #define EXTI_PR_PIF12 EXTI_PR_PR12
2968 #define EXTI_PR_PIF13 EXTI_PR_PR13
2969 #define EXTI_PR_PIF14 EXTI_PR_PR14
2970 #define EXTI_PR_PIF15 EXTI_PR_PR15
2971 #define EXTI_PR_PIF16 EXTI_PR_PR16
2972 #define EXTI_PR_PIF17 EXTI_PR_PR17
2973 #define EXTI_PR_PIF18 EXTI_PR_PR18
2974 
2975 /******************************************************************************/
2976 /* */
2977 /* DMA Controller */
2978 /* */
2979 /******************************************************************************/
2980 
2981 /******************* Bit definition for DMA_ISR register ********************/
2982 #define DMA_ISR_GIF1_Pos (0U)
2983 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)
2984 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk
2985 #define DMA_ISR_TCIF1_Pos (1U)
2986 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)
2987 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk
2988 #define DMA_ISR_HTIF1_Pos (2U)
2989 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)
2990 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk
2991 #define DMA_ISR_TEIF1_Pos (3U)
2992 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)
2993 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk
2994 #define DMA_ISR_GIF2_Pos (4U)
2995 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)
2996 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk
2997 #define DMA_ISR_TCIF2_Pos (5U)
2998 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)
2999 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk
3000 #define DMA_ISR_HTIF2_Pos (6U)
3001 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)
3002 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk
3003 #define DMA_ISR_TEIF2_Pos (7U)
3004 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)
3005 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk
3006 #define DMA_ISR_GIF3_Pos (8U)
3007 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)
3008 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk
3009 #define DMA_ISR_TCIF3_Pos (9U)
3010 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)
3011 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk
3012 #define DMA_ISR_HTIF3_Pos (10U)
3013 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)
3014 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk
3015 #define DMA_ISR_TEIF3_Pos (11U)
3016 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)
3017 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk
3018 #define DMA_ISR_GIF4_Pos (12U)
3019 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)
3020 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk
3021 #define DMA_ISR_TCIF4_Pos (13U)
3022 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)
3023 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk
3024 #define DMA_ISR_HTIF4_Pos (14U)
3025 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)
3026 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk
3027 #define DMA_ISR_TEIF4_Pos (15U)
3028 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)
3029 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk
3030 #define DMA_ISR_GIF5_Pos (16U)
3031 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)
3032 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk
3033 #define DMA_ISR_TCIF5_Pos (17U)
3034 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)
3035 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk
3036 #define DMA_ISR_HTIF5_Pos (18U)
3037 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)
3038 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk
3039 #define DMA_ISR_TEIF5_Pos (19U)
3040 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)
3041 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk
3042 #define DMA_ISR_GIF6_Pos (20U)
3043 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)
3044 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk
3045 #define DMA_ISR_TCIF6_Pos (21U)
3046 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)
3047 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk
3048 #define DMA_ISR_HTIF6_Pos (22U)
3049 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)
3050 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk
3051 #define DMA_ISR_TEIF6_Pos (23U)
3052 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)
3053 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk
3054 #define DMA_ISR_GIF7_Pos (24U)
3055 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)
3056 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk
3057 #define DMA_ISR_TCIF7_Pos (25U)
3058 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)
3059 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk
3060 #define DMA_ISR_HTIF7_Pos (26U)
3061 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)
3062 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk
3063 #define DMA_ISR_TEIF7_Pos (27U)
3064 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)
3065 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk
3067 /******************* Bit definition for DMA_IFCR register *******************/
3068 #define DMA_IFCR_CGIF1_Pos (0U)
3069 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)
3070 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk
3071 #define DMA_IFCR_CTCIF1_Pos (1U)
3072 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)
3073 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk
3074 #define DMA_IFCR_CHTIF1_Pos (2U)
3075 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)
3076 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk
3077 #define DMA_IFCR_CTEIF1_Pos (3U)
3078 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)
3079 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk
3080 #define DMA_IFCR_CGIF2_Pos (4U)
3081 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)
3082 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk
3083 #define DMA_IFCR_CTCIF2_Pos (5U)
3084 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)
3085 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk
3086 #define DMA_IFCR_CHTIF2_Pos (6U)
3087 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)
3088 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk
3089 #define DMA_IFCR_CTEIF2_Pos (7U)
3090 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)
3091 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk
3092 #define DMA_IFCR_CGIF3_Pos (8U)
3093 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)
3094 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk
3095 #define DMA_IFCR_CTCIF3_Pos (9U)
3096 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)
3097 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk
3098 #define DMA_IFCR_CHTIF3_Pos (10U)
3099 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)
3100 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk
3101 #define DMA_IFCR_CTEIF3_Pos (11U)
3102 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)
3103 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk
3104 #define DMA_IFCR_CGIF4_Pos (12U)
3105 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)
3106 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk
3107 #define DMA_IFCR_CTCIF4_Pos (13U)
3108 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)
3109 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk
3110 #define DMA_IFCR_CHTIF4_Pos (14U)
3111 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)
3112 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk
3113 #define DMA_IFCR_CTEIF4_Pos (15U)
3114 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)
3115 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk
3116 #define DMA_IFCR_CGIF5_Pos (16U)
3117 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)
3118 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk
3119 #define DMA_IFCR_CTCIF5_Pos (17U)
3120 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)
3121 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk
3122 #define DMA_IFCR_CHTIF5_Pos (18U)
3123 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)
3124 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk
3125 #define DMA_IFCR_CTEIF5_Pos (19U)
3126 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)
3127 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk
3128 #define DMA_IFCR_CGIF6_Pos (20U)
3129 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)
3130 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk
3131 #define DMA_IFCR_CTCIF6_Pos (21U)
3132 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)
3133 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk
3134 #define DMA_IFCR_CHTIF6_Pos (22U)
3135 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)
3136 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk
3137 #define DMA_IFCR_CTEIF6_Pos (23U)
3138 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)
3139 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk
3140 #define DMA_IFCR_CGIF7_Pos (24U)
3141 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)
3142 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk
3143 #define DMA_IFCR_CTCIF7_Pos (25U)
3144 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)
3145 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk
3146 #define DMA_IFCR_CHTIF7_Pos (26U)
3147 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)
3148 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk
3149 #define DMA_IFCR_CTEIF7_Pos (27U)
3150 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)
3151 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk
3153 /******************* Bit definition for DMA_CCR register *******************/
3154 #define DMA_CCR_EN_Pos (0U)
3155 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)
3156 #define DMA_CCR_EN DMA_CCR_EN_Msk
3157 #define DMA_CCR_TCIE_Pos (1U)
3158 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)
3159 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk
3160 #define DMA_CCR_HTIE_Pos (2U)
3161 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)
3162 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk
3163 #define DMA_CCR_TEIE_Pos (3U)
3164 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)
3165 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk
3166 #define DMA_CCR_DIR_Pos (4U)
3167 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)
3168 #define DMA_CCR_DIR DMA_CCR_DIR_Msk
3169 #define DMA_CCR_CIRC_Pos (5U)
3170 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)
3171 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk
3172 #define DMA_CCR_PINC_Pos (6U)
3173 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)
3174 #define DMA_CCR_PINC DMA_CCR_PINC_Msk
3175 #define DMA_CCR_MINC_Pos (7U)
3176 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)
3177 #define DMA_CCR_MINC DMA_CCR_MINC_Msk
3179 #define DMA_CCR_PSIZE_Pos (8U)
3180 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)
3181 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk
3182 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)
3183 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)
3185 #define DMA_CCR_MSIZE_Pos (10U)
3186 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)
3187 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk
3188 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)
3189 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)
3191 #define DMA_CCR_PL_Pos (12U)
3192 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)
3193 #define DMA_CCR_PL DMA_CCR_PL_Msk
3194 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)
3195 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)
3197 #define DMA_CCR_MEM2MEM_Pos (14U)
3198 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)
3199 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk
3201 /****************** Bit definition for DMA_CNDTR register ******************/
3202 #define DMA_CNDTR_NDT_Pos (0U)
3203 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)
3204 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk
3206 /****************** Bit definition for DMA_CPAR register *******************/
3207 #define DMA_CPAR_PA_Pos (0U)
3208 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)
3209 #define DMA_CPAR_PA DMA_CPAR_PA_Msk
3211 /****************** Bit definition for DMA_CMAR register *******************/
3212 #define DMA_CMAR_MA_Pos (0U)
3213 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)
3214 #define DMA_CMAR_MA DMA_CMAR_MA_Msk
3216 /******************************************************************************/
3217 /* */
3218 /* Analog to Digital Converter (ADC) */
3219 /* */
3220 /******************************************************************************/
3221 
3222 /*
3223  * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
3224  */
3225 #define ADC_MULTIMODE_SUPPORT
3227 /******************** Bit definition for ADC_SR register ********************/
3228 #define ADC_SR_AWD_Pos (0U)
3229 #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)
3230 #define ADC_SR_AWD ADC_SR_AWD_Msk
3231 #define ADC_SR_EOS_Pos (1U)
3232 #define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos)
3233 #define ADC_SR_EOS ADC_SR_EOS_Msk
3234 #define ADC_SR_JEOS_Pos (2U)
3235 #define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos)
3236 #define ADC_SR_JEOS ADC_SR_JEOS_Msk
3237 #define ADC_SR_JSTRT_Pos (3U)
3238 #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)
3239 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk
3240 #define ADC_SR_STRT_Pos (4U)
3241 #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)
3242 #define ADC_SR_STRT ADC_SR_STRT_Msk
3244 /* Legacy defines */
3245 #define ADC_SR_EOC (ADC_SR_EOS)
3246 #define ADC_SR_JEOC (ADC_SR_JEOS)
3247 
3248 /******************* Bit definition for ADC_CR1 register ********************/
3249 #define ADC_CR1_AWDCH_Pos (0U)
3250 #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)
3251 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk
3252 #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)
3253 #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)
3254 #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)
3255 #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)
3256 #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)
3258 #define ADC_CR1_EOSIE_Pos (5U)
3259 #define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos)
3260 #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk
3261 #define ADC_CR1_AWDIE_Pos (6U)
3262 #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)
3263 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk
3264 #define ADC_CR1_JEOSIE_Pos (7U)
3265 #define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos)
3266 #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk
3267 #define ADC_CR1_SCAN_Pos (8U)
3268 #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)
3269 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk
3270 #define ADC_CR1_AWDSGL_Pos (9U)
3271 #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)
3272 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk
3273 #define ADC_CR1_JAUTO_Pos (10U)
3274 #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)
3275 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk
3276 #define ADC_CR1_DISCEN_Pos (11U)
3277 #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)
3278 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk
3279 #define ADC_CR1_JDISCEN_Pos (12U)
3280 #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)
3281 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk
3283 #define ADC_CR1_DISCNUM_Pos (13U)
3284 #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)
3285 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk
3286 #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)
3287 #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)
3288 #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)
3290 #define ADC_CR1_DUALMOD_Pos (16U)
3291 #define ADC_CR1_DUALMOD_Msk (0xFUL << ADC_CR1_DUALMOD_Pos)
3292 #define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk
3293 #define ADC_CR1_DUALMOD_0 (0x1UL << ADC_CR1_DUALMOD_Pos)
3294 #define ADC_CR1_DUALMOD_1 (0x2UL << ADC_CR1_DUALMOD_Pos)
3295 #define ADC_CR1_DUALMOD_2 (0x4UL << ADC_CR1_DUALMOD_Pos)
3296 #define ADC_CR1_DUALMOD_3 (0x8UL << ADC_CR1_DUALMOD_Pos)
3298 #define ADC_CR1_JAWDEN_Pos (22U)
3299 #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)
3300 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk
3301 #define ADC_CR1_AWDEN_Pos (23U)
3302 #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)
3303 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk
3305 /* Legacy defines */
3306 #define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
3307 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
3308 
3309 /******************* Bit definition for ADC_CR2 register ********************/
3310 #define ADC_CR2_ADON_Pos (0U)
3311 #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)
3312 #define ADC_CR2_ADON ADC_CR2_ADON_Msk
3313 #define ADC_CR2_CONT_Pos (1U)
3314 #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)
3315 #define ADC_CR2_CONT ADC_CR2_CONT_Msk
3316 #define ADC_CR2_CAL_Pos (2U)
3317 #define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos)
3318 #define ADC_CR2_CAL ADC_CR2_CAL_Msk
3319 #define ADC_CR2_RSTCAL_Pos (3U)
3320 #define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos)
3321 #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk
3322 #define ADC_CR2_DMA_Pos (8U)
3323 #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)
3324 #define ADC_CR2_DMA ADC_CR2_DMA_Msk
3325 #define ADC_CR2_ALIGN_Pos (11U)
3326 #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)
3327 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk
3329 #define ADC_CR2_JEXTSEL_Pos (12U)
3330 #define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos)
3331 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk
3332 #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)
3333 #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)
3334 #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)
3336 #define ADC_CR2_JEXTTRIG_Pos (15U)
3337 #define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos)
3338 #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk
3340 #define ADC_CR2_EXTSEL_Pos (17U)
3341 #define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos)
3342 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk
3343 #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)
3344 #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)
3345 #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)
3347 #define ADC_CR2_EXTTRIG_Pos (20U)
3348 #define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos)
3349 #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk
3350 #define ADC_CR2_JSWSTART_Pos (21U)
3351 #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)
3352 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk
3353 #define ADC_CR2_SWSTART_Pos (22U)
3354 #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)
3355 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk
3356 #define ADC_CR2_TSVREFE_Pos (23U)
3357 #define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos)
3358 #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk
3360 /****************** Bit definition for ADC_SMPR1 register *******************/
3361 #define ADC_SMPR1_SMP10_Pos (0U)
3362 #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)
3363 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk
3364 #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)
3365 #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)
3366 #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)
3368 #define ADC_SMPR1_SMP11_Pos (3U)
3369 #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)
3370 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk
3371 #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)
3372 #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)
3373 #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)
3375 #define ADC_SMPR1_SMP12_Pos (6U)
3376 #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)
3377 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk
3378 #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)
3379 #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)
3380 #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)
3382 #define ADC_SMPR1_SMP13_Pos (9U)
3383 #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)
3384 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk
3385 #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)
3386 #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)
3387 #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)
3389 #define ADC_SMPR1_SMP14_Pos (12U)
3390 #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)
3391 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk
3392 #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)
3393 #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)
3394 #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)
3396 #define ADC_SMPR1_SMP15_Pos (15U)
3397 #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)
3398 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk
3399 #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)
3400 #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)
3401 #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)
3403 #define ADC_SMPR1_SMP16_Pos (18U)
3404 #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)
3405 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk
3406 #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)
3407 #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)
3408 #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)
3410 #define ADC_SMPR1_SMP17_Pos (21U)
3411 #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)
3412 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk
3413 #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)
3414 #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)
3415 #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)
3417 /****************** Bit definition for ADC_SMPR2 register *******************/
3418 #define ADC_SMPR2_SMP0_Pos (0U)
3419 #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)
3420 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk
3421 #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)
3422 #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)
3423 #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)
3425 #define ADC_SMPR2_SMP1_Pos (3U)
3426 #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)
3427 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk
3428 #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)
3429 #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)
3430 #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)
3432 #define ADC_SMPR2_SMP2_Pos (6U)
3433 #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)
3434 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk
3435 #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)
3436 #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)
3437 #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)
3439 #define ADC_SMPR2_SMP3_Pos (9U)
3440 #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)
3441 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk
3442 #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)
3443 #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)
3444 #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)
3446 #define ADC_SMPR2_SMP4_Pos (12U)
3447 #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)
3448 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk
3449 #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)
3450 #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)
3451 #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)
3453 #define ADC_SMPR2_SMP5_Pos (15U)
3454 #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)
3455 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk
3456 #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)
3457 #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)
3458 #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)
3460 #define ADC_SMPR2_SMP6_Pos (18U)
3461 #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)
3462 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk
3463 #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)
3464 #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)
3465 #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)
3467 #define ADC_SMPR2_SMP7_Pos (21U)
3468 #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)
3469 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk
3470 #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)
3471 #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)
3472 #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)
3474 #define ADC_SMPR2_SMP8_Pos (24U)
3475 #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)
3476 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk
3477 #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)
3478 #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)
3479 #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)
3481 #define ADC_SMPR2_SMP9_Pos (27U)
3482 #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)
3483 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk
3484 #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)
3485 #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)
3486 #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)
3488 /****************** Bit definition for ADC_JOFR1 register *******************/
3489 #define ADC_JOFR1_JOFFSET1_Pos (0U)
3490 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)
3491 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk
3493 /****************** Bit definition for ADC_JOFR2 register *******************/
3494 #define ADC_JOFR2_JOFFSET2_Pos (0U)
3495 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)
3496 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk
3498 /****************** Bit definition for ADC_JOFR3 register *******************/
3499 #define ADC_JOFR3_JOFFSET3_Pos (0U)
3500 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)
3501 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk
3503 /****************** Bit definition for ADC_JOFR4 register *******************/
3504 #define ADC_JOFR4_JOFFSET4_Pos (0U)
3505 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)
3506 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk
3508 /******************* Bit definition for ADC_HTR register ********************/
3509 #define ADC_HTR_HT_Pos (0U)
3510 #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)
3511 #define ADC_HTR_HT ADC_HTR_HT_Msk
3513 /******************* Bit definition for ADC_LTR register ********************/
3514 #define ADC_LTR_LT_Pos (0U)
3515 #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)
3516 #define ADC_LTR_LT ADC_LTR_LT_Msk
3518 /******************* Bit definition for ADC_SQR1 register *******************/
3519 #define ADC_SQR1_SQ13_Pos (0U)
3520 #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)
3521 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk
3522 #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)
3523 #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)
3524 #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)
3525 #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)
3526 #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)
3528 #define ADC_SQR1_SQ14_Pos (5U)
3529 #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)
3530 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk
3531 #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)
3532 #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)
3533 #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)
3534 #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)
3535 #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)
3537 #define ADC_SQR1_SQ15_Pos (10U)
3538 #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)
3539 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk
3540 #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)
3541 #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)
3542 #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)
3543 #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)
3544 #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)
3546 #define ADC_SQR1_SQ16_Pos (15U)
3547 #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)
3548 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk
3549 #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)
3550 #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)
3551 #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)
3552 #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)
3553 #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)
3555 #define ADC_SQR1_L_Pos (20U)
3556 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
3557 #define ADC_SQR1_L ADC_SQR1_L_Msk
3558 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
3559 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
3560 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
3561 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
3563 /******************* Bit definition for ADC_SQR2 register *******************/
3564 #define ADC_SQR2_SQ7_Pos (0U)
3565 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
3566 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
3567 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
3568 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
3569 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
3570 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
3571 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
3573 #define ADC_SQR2_SQ8_Pos (5U)
3574 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
3575 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
3576 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
3577 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
3578 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
3579 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
3580 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
3582 #define ADC_SQR2_SQ9_Pos (10U)
3583 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
3584 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
3585 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
3586 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
3587 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
3588 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
3589 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
3591 #define ADC_SQR2_SQ10_Pos (15U)
3592 #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)
3593 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk
3594 #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)
3595 #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)
3596 #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)
3597 #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)
3598 #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)
3600 #define ADC_SQR2_SQ11_Pos (20U)
3601 #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)
3602 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk
3603 #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)
3604 #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)
3605 #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)
3606 #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)
3607 #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)
3609 #define ADC_SQR2_SQ12_Pos (25U)
3610 #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)
3611 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk
3612 #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)
3613 #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)
3614 #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)
3615 #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)
3616 #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)
3618 /******************* Bit definition for ADC_SQR3 register *******************/
3619 #define ADC_SQR3_SQ1_Pos (0U)
3620 #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)
3621 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk
3622 #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)
3623 #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)
3624 #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)
3625 #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)
3626 #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)
3628 #define ADC_SQR3_SQ2_Pos (5U)
3629 #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)
3630 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk
3631 #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)
3632 #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)
3633 #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)
3634 #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)
3635 #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)
3637 #define ADC_SQR3_SQ3_Pos (10U)
3638 #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)
3639 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk
3640 #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)
3641 #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)
3642 #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)
3643 #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)
3644 #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)
3646 #define ADC_SQR3_SQ4_Pos (15U)
3647 #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)
3648 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk
3649 #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)
3650 #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)
3651 #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)
3652 #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)
3653 #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)
3655 #define ADC_SQR3_SQ5_Pos (20U)
3656 #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)
3657 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk
3658 #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)
3659 #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)
3660 #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)
3661 #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)
3662 #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)
3664 #define ADC_SQR3_SQ6_Pos (25U)
3665 #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)
3666 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk
3667 #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)
3668 #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)
3669 #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)
3670 #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)
3671 #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)
3673 /******************* Bit definition for ADC_JSQR register *******************/
3674 #define ADC_JSQR_JSQ1_Pos (0U)
3675 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
3676 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
3677 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
3678 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
3679 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
3680 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
3681 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
3683 #define ADC_JSQR_JSQ2_Pos (5U)
3684 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
3685 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
3686 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
3687 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
3688 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
3689 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
3690 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
3692 #define ADC_JSQR_JSQ3_Pos (10U)
3693 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
3694 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
3695 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
3696 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
3697 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
3698 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
3699 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
3701 #define ADC_JSQR_JSQ4_Pos (15U)
3702 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
3703 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
3704 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
3705 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
3706 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
3707 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
3708 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
3710 #define ADC_JSQR_JL_Pos (20U)
3711 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
3712 #define ADC_JSQR_JL ADC_JSQR_JL_Msk
3713 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
3714 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
3716 /******************* Bit definition for ADC_JDR1 register *******************/
3717 #define ADC_JDR1_JDATA_Pos (0U)
3718 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)
3719 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
3721 /******************* Bit definition for ADC_JDR2 register *******************/
3722 #define ADC_JDR2_JDATA_Pos (0U)
3723 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)
3724 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
3726 /******************* Bit definition for ADC_JDR3 register *******************/
3727 #define ADC_JDR3_JDATA_Pos (0U)
3728 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)
3729 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
3731 /******************* Bit definition for ADC_JDR4 register *******************/
3732 #define ADC_JDR4_JDATA_Pos (0U)
3733 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)
3734 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
3736 /******************** Bit definition for ADC_DR register ********************/
3737 #define ADC_DR_DATA_Pos (0U)
3738 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)
3739 #define ADC_DR_DATA ADC_DR_DATA_Msk
3740 #define ADC_DR_ADC2DATA_Pos (16U)
3741 #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)
3742 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk
3745 /*****************************************************************************/
3746 /* */
3747 /* Timers (TIM) */
3748 /* */
3749 /*****************************************************************************/
3750 /******************* Bit definition for TIM_CR1 register *******************/
3751 #define TIM_CR1_CEN_Pos (0U)
3752 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
3753 #define TIM_CR1_CEN TIM_CR1_CEN_Msk
3754 #define TIM_CR1_UDIS_Pos (1U)
3755 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
3756 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
3757 #define TIM_CR1_URS_Pos (2U)
3758 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
3759 #define TIM_CR1_URS TIM_CR1_URS_Msk
3760 #define TIM_CR1_OPM_Pos (3U)
3761 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
3762 #define TIM_CR1_OPM TIM_CR1_OPM_Msk
3763 #define TIM_CR1_DIR_Pos (4U)
3764 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
3765 #define TIM_CR1_DIR TIM_CR1_DIR_Msk
3767 #define TIM_CR1_CMS_Pos (5U)
3768 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
3769 #define TIM_CR1_CMS TIM_CR1_CMS_Msk
3770 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
3771 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
3773 #define TIM_CR1_ARPE_Pos (7U)
3774 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
3775 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
3777 #define TIM_CR1_CKD_Pos (8U)
3778 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
3779 #define TIM_CR1_CKD TIM_CR1_CKD_Msk
3780 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
3781 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
3783 /******************* Bit definition for TIM_CR2 register *******************/
3784 #define TIM_CR2_CCPC_Pos (0U)
3785 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
3786 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
3787 #define TIM_CR2_CCUS_Pos (2U)
3788 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
3789 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
3790 #define TIM_CR2_CCDS_Pos (3U)
3791 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
3792 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
3794 #define TIM_CR2_MMS_Pos (4U)
3795 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
3796 #define TIM_CR2_MMS TIM_CR2_MMS_Msk
3797 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
3798 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
3799 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
3801 #define TIM_CR2_TI1S_Pos (7U)
3802 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
3803 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
3804 #define TIM_CR2_OIS1_Pos (8U)
3805 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
3806 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
3807 #define TIM_CR2_OIS1N_Pos (9U)
3808 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
3809 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
3810 #define TIM_CR2_OIS2_Pos (10U)
3811 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
3812 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
3813 #define TIM_CR2_OIS2N_Pos (11U)
3814 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
3815 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
3816 #define TIM_CR2_OIS3_Pos (12U)
3817 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
3818 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
3819 #define TIM_CR2_OIS3N_Pos (13U)
3820 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
3821 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
3822 #define TIM_CR2_OIS4_Pos (14U)
3823 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
3824 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
3826 /******************* Bit definition for TIM_SMCR register ******************/
3827 #define TIM_SMCR_SMS_Pos (0U)
3828 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)
3829 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
3830 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)
3831 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)
3832 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)
3834 #define TIM_SMCR_TS_Pos (4U)
3835 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)
3836 #define TIM_SMCR_TS TIM_SMCR_TS_Msk
3837 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)
3838 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)
3839 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)
3841 #define TIM_SMCR_MSM_Pos (7U)
3842 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
3843 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
3845 #define TIM_SMCR_ETF_Pos (8U)
3846 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
3847 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
3848 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
3849 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
3850 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
3851 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
3853 #define TIM_SMCR_ETPS_Pos (12U)
3854 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
3855 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
3856 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
3857 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
3859 #define TIM_SMCR_ECE_Pos (14U)
3860 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
3861 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
3862 #define TIM_SMCR_ETP_Pos (15U)
3863 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
3864 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
3866 /******************* Bit definition for TIM_DIER register ******************/
3867 #define TIM_DIER_UIE_Pos (0U)
3868 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
3869 #define TIM_DIER_UIE TIM_DIER_UIE_Msk
3870 #define TIM_DIER_CC1IE_Pos (1U)
3871 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
3872 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
3873 #define TIM_DIER_CC2IE_Pos (2U)
3874 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
3875 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
3876 #define TIM_DIER_CC3IE_Pos (3U)
3877 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
3878 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
3879 #define TIM_DIER_CC4IE_Pos (4U)
3880 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
3881 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
3882 #define TIM_DIER_COMIE_Pos (5U)
3883 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
3884 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
3885 #define TIM_DIER_TIE_Pos (6U)
3886 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
3887 #define TIM_DIER_TIE TIM_DIER_TIE_Msk
3888 #define TIM_DIER_BIE_Pos (7U)
3889 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
3890 #define TIM_DIER_BIE TIM_DIER_BIE_Msk
3891 #define TIM_DIER_UDE_Pos (8U)
3892 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
3893 #define TIM_DIER_UDE TIM_DIER_UDE_Msk
3894 #define TIM_DIER_CC1DE_Pos (9U)
3895 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
3896 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
3897 #define TIM_DIER_CC2DE_Pos (10U)
3898 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
3899 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
3900 #define TIM_DIER_CC3DE_Pos (11U)
3901 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
3902 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
3903 #define TIM_DIER_CC4DE_Pos (12U)
3904 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
3905 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
3906 #define TIM_DIER_COMDE_Pos (13U)
3907 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
3908 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
3909 #define TIM_DIER_TDE_Pos (14U)
3910 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
3911 #define TIM_DIER_TDE TIM_DIER_TDE_Msk
3913 /******************** Bit definition for TIM_SR register *******************/
3914 #define TIM_SR_UIF_Pos (0U)
3915 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
3916 #define TIM_SR_UIF TIM_SR_UIF_Msk
3917 #define TIM_SR_CC1IF_Pos (1U)
3918 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
3919 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
3920 #define TIM_SR_CC2IF_Pos (2U)
3921 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
3922 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
3923 #define TIM_SR_CC3IF_Pos (3U)
3924 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
3925 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
3926 #define TIM_SR_CC4IF_Pos (4U)
3927 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
3928 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
3929 #define TIM_SR_COMIF_Pos (5U)
3930 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
3931 #define TIM_SR_COMIF TIM_SR_COMIF_Msk
3932 #define TIM_SR_TIF_Pos (6U)
3933 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
3934 #define TIM_SR_TIF TIM_SR_TIF_Msk
3935 #define TIM_SR_BIF_Pos (7U)
3936 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
3937 #define TIM_SR_BIF TIM_SR_BIF_Msk
3938 #define TIM_SR_CC1OF_Pos (9U)
3939 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
3940 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
3941 #define TIM_SR_CC2OF_Pos (10U)
3942 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
3943 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
3944 #define TIM_SR_CC3OF_Pos (11U)
3945 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
3946 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
3947 #define TIM_SR_CC4OF_Pos (12U)
3948 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
3949 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
3951 /******************* Bit definition for TIM_EGR register *******************/
3952 #define TIM_EGR_UG_Pos (0U)
3953 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
3954 #define TIM_EGR_UG TIM_EGR_UG_Msk
3955 #define TIM_EGR_CC1G_Pos (1U)
3956 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
3957 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
3958 #define TIM_EGR_CC2G_Pos (2U)
3959 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
3960 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
3961 #define TIM_EGR_CC3G_Pos (3U)
3962 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
3963 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
3964 #define TIM_EGR_CC4G_Pos (4U)
3965 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
3966 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
3967 #define TIM_EGR_COMG_Pos (5U)
3968 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
3969 #define TIM_EGR_COMG TIM_EGR_COMG_Msk
3970 #define TIM_EGR_TG_Pos (6U)
3971 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
3972 #define TIM_EGR_TG TIM_EGR_TG_Msk
3973 #define TIM_EGR_BG_Pos (7U)
3974 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
3975 #define TIM_EGR_BG TIM_EGR_BG_Msk
3977 /****************** Bit definition for TIM_CCMR1 register ******************/
3978 #define TIM_CCMR1_CC1S_Pos (0U)
3979 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
3980 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
3981 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
3982 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
3984 #define TIM_CCMR1_OC1FE_Pos (2U)
3985 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
3986 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
3987 #define TIM_CCMR1_OC1PE_Pos (3U)
3988 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
3989 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
3991 #define TIM_CCMR1_OC1M_Pos (4U)
3992 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)
3993 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
3994 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)
3995 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)
3996 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)
3998 #define TIM_CCMR1_OC1CE_Pos (7U)
3999 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
4000 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
4002 #define TIM_CCMR1_CC2S_Pos (8U)
4003 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
4004 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
4005 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
4006 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
4008 #define TIM_CCMR1_OC2FE_Pos (10U)
4009 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
4010 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
4011 #define TIM_CCMR1_OC2PE_Pos (11U)
4012 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
4013 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
4015 #define TIM_CCMR1_OC2M_Pos (12U)
4016 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)
4017 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
4018 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)
4019 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)
4020 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)
4022 #define TIM_CCMR1_OC2CE_Pos (15U)
4023 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
4024 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
4026 /*---------------------------------------------------------------------------*/
4027 
4028 #define TIM_CCMR1_IC1PSC_Pos (2U)
4029 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
4030 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
4031 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
4032 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
4034 #define TIM_CCMR1_IC1F_Pos (4U)
4035 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
4036 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
4037 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
4038 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
4039 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
4040 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
4042 #define TIM_CCMR1_IC2PSC_Pos (10U)
4043 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
4044 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
4045 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
4046 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
4048 #define TIM_CCMR1_IC2F_Pos (12U)
4049 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
4050 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
4051 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
4052 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
4053 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
4054 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
4056 /****************** Bit definition for TIM_CCMR2 register ******************/
4057 #define TIM_CCMR2_CC3S_Pos (0U)
4058 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
4059 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
4060 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
4061 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
4063 #define TIM_CCMR2_OC3FE_Pos (2U)
4064 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
4065 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
4066 #define TIM_CCMR2_OC3PE_Pos (3U)
4067 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
4068 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
4070 #define TIM_CCMR2_OC3M_Pos (4U)
4071 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)
4072 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
4073 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
4074 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
4075 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
4077 #define TIM_CCMR2_OC3CE_Pos (7U)
4078 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
4079 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
4081 #define TIM_CCMR2_CC4S_Pos (8U)
4082 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
4083 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
4084 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
4085 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
4087 #define TIM_CCMR2_OC4FE_Pos (10U)
4088 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
4089 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
4090 #define TIM_CCMR2_OC4PE_Pos (11U)
4091 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
4092 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
4094 #define TIM_CCMR2_OC4M_Pos (12U)
4095 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)
4096 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
4097 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
4098 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
4099 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
4101 #define TIM_CCMR2_OC4CE_Pos (15U)
4102 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
4103 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
4105 /*---------------------------------------------------------------------------*/
4106 
4107 #define TIM_CCMR2_IC3PSC_Pos (2U)
4108 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
4109 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
4110 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
4111 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
4113 #define TIM_CCMR2_IC3F_Pos (4U)
4114 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
4115 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
4116 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
4117 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
4118 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
4119 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
4121 #define TIM_CCMR2_IC4PSC_Pos (10U)
4122 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
4123 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
4124 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
4125 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
4127 #define TIM_CCMR2_IC4F_Pos (12U)
4128 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
4129 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
4130 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
4131 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
4132 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
4133 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
4135 /******************* Bit definition for TIM_CCER register ******************/
4136 #define TIM_CCER_CC1E_Pos (0U)
4137 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
4138 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
4139 #define TIM_CCER_CC1P_Pos (1U)
4140 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
4141 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
4142 #define TIM_CCER_CC1NE_Pos (2U)
4143 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
4144 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
4145 #define TIM_CCER_CC1NP_Pos (3U)
4146 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
4147 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
4148 #define TIM_CCER_CC2E_Pos (4U)
4149 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
4150 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
4151 #define TIM_CCER_CC2P_Pos (5U)
4152 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
4153 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
4154 #define TIM_CCER_CC2NE_Pos (6U)
4155 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
4156 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
4157 #define TIM_CCER_CC2NP_Pos (7U)
4158 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
4159 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
4160 #define TIM_CCER_CC3E_Pos (8U)
4161 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
4162 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
4163 #define TIM_CCER_CC3P_Pos (9U)
4164 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
4165 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
4166 #define TIM_CCER_CC3NE_Pos (10U)
4167 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
4168 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
4169 #define TIM_CCER_CC3NP_Pos (11U)
4170 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
4171 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
4172 #define TIM_CCER_CC4E_Pos (12U)
4173 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
4174 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
4175 #define TIM_CCER_CC4P_Pos (13U)
4176 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
4177 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
4179 /******************* Bit definition for TIM_CNT register *******************/
4180 #define TIM_CNT_CNT_Pos (0U)
4181 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
4182 #define TIM_CNT_CNT TIM_CNT_CNT_Msk
4184 /******************* Bit definition for TIM_PSC register *******************/
4185 #define TIM_PSC_PSC_Pos (0U)
4186 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
4187 #define TIM_PSC_PSC TIM_PSC_PSC_Msk
4189 /******************* Bit definition for TIM_ARR register *******************/
4190 #define TIM_ARR_ARR_Pos (0U)
4191 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
4192 #define TIM_ARR_ARR TIM_ARR_ARR_Msk
4194 /******************* Bit definition for TIM_RCR register *******************/
4195 #define TIM_RCR_REP_Pos (0U)
4196 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
4197 #define TIM_RCR_REP TIM_RCR_REP_Msk
4199 /******************* Bit definition for TIM_CCR1 register ******************/
4200 #define TIM_CCR1_CCR1_Pos (0U)
4201 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
4202 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
4204 /******************* Bit definition for TIM_CCR2 register ******************/
4205 #define TIM_CCR2_CCR2_Pos (0U)
4206 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
4207 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
4209 /******************* Bit definition for TIM_CCR3 register ******************/
4210 #define TIM_CCR3_CCR3_Pos (0U)
4211 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
4212 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
4214 /******************* Bit definition for TIM_CCR4 register ******************/
4215 #define TIM_CCR4_CCR4_Pos (0U)
4216 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
4217 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
4219 /******************* Bit definition for TIM_BDTR register ******************/
4220 #define TIM_BDTR_DTG_Pos (0U)
4221 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
4222 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
4223 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
4224 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
4225 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
4226 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
4227 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
4228 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
4229 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
4230 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
4232 #define TIM_BDTR_LOCK_Pos (8U)
4233 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
4234 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
4235 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
4236 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
4238 #define TIM_BDTR_OSSI_Pos (10U)
4239 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
4240 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
4241 #define TIM_BDTR_OSSR_Pos (11U)
4242 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
4243 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
4244 #define TIM_BDTR_BKE_Pos (12U)
4245 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
4246 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
4247 #define TIM_BDTR_BKP_Pos (13U)
4248 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
4249 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
4250 #define TIM_BDTR_AOE_Pos (14U)
4251 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
4252 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
4253 #define TIM_BDTR_MOE_Pos (15U)
4254 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
4255 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
4257 /******************* Bit definition for TIM_DCR register *******************/
4258 #define TIM_DCR_DBA_Pos (0U)
4259 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
4260 #define TIM_DCR_DBA TIM_DCR_DBA_Msk
4261 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
4262 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
4263 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
4264 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
4265 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
4267 #define TIM_DCR_DBL_Pos (8U)
4268 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
4269 #define TIM_DCR_DBL TIM_DCR_DBL_Msk
4270 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
4271 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
4272 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
4273 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
4274 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
4276 /******************* Bit definition for TIM_DMAR register ******************/
4277 #define TIM_DMAR_DMAB_Pos (0U)
4278 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
4279 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
4281 /******************************************************************************/
4282 /* */
4283 /* Real-Time Clock */
4284 /* */
4285 /******************************************************************************/
4286 
4287 /******************* Bit definition for RTC_CRH register ********************/
4288 #define RTC_CRH_SECIE_Pos (0U)
4289 #define RTC_CRH_SECIE_Msk (0x1UL << RTC_CRH_SECIE_Pos)
4290 #define RTC_CRH_SECIE RTC_CRH_SECIE_Msk
4291 #define RTC_CRH_ALRIE_Pos (1U)
4292 #define RTC_CRH_ALRIE_Msk (0x1UL << RTC_CRH_ALRIE_Pos)
4293 #define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk
4294 #define RTC_CRH_OWIE_Pos (2U)
4295 #define RTC_CRH_OWIE_Msk (0x1UL << RTC_CRH_OWIE_Pos)
4296 #define RTC_CRH_OWIE RTC_CRH_OWIE_Msk
4298 /******************* Bit definition for RTC_CRL register ********************/
4299 #define RTC_CRL_SECF_Pos (0U)
4300 #define RTC_CRL_SECF_Msk (0x1UL << RTC_CRL_SECF_Pos)
4301 #define RTC_CRL_SECF RTC_CRL_SECF_Msk
4302 #define RTC_CRL_ALRF_Pos (1U)
4303 #define RTC_CRL_ALRF_Msk (0x1UL << RTC_CRL_ALRF_Pos)
4304 #define RTC_CRL_ALRF RTC_CRL_ALRF_Msk
4305 #define RTC_CRL_OWF_Pos (2U)
4306 #define RTC_CRL_OWF_Msk (0x1UL << RTC_CRL_OWF_Pos)
4307 #define RTC_CRL_OWF RTC_CRL_OWF_Msk
4308 #define RTC_CRL_RSF_Pos (3U)
4309 #define RTC_CRL_RSF_Msk (0x1UL << RTC_CRL_RSF_Pos)
4310 #define RTC_CRL_RSF RTC_CRL_RSF_Msk
4311 #define RTC_CRL_CNF_Pos (4U)
4312 #define RTC_CRL_CNF_Msk (0x1UL << RTC_CRL_CNF_Pos)
4313 #define RTC_CRL_CNF RTC_CRL_CNF_Msk
4314 #define RTC_CRL_RTOFF_Pos (5U)
4315 #define RTC_CRL_RTOFF_Msk (0x1UL << RTC_CRL_RTOFF_Pos)
4316 #define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk
4318 /******************* Bit definition for RTC_PRLH register *******************/
4319 #define RTC_PRLH_PRL_Pos (0U)
4320 #define RTC_PRLH_PRL_Msk (0xFUL << RTC_PRLH_PRL_Pos)
4321 #define RTC_PRLH_PRL RTC_PRLH_PRL_Msk
4323 /******************* Bit definition for RTC_PRLL register *******************/
4324 #define RTC_PRLL_PRL_Pos (0U)
4325 #define RTC_PRLL_PRL_Msk (0xFFFFUL << RTC_PRLL_PRL_Pos)
4326 #define RTC_PRLL_PRL RTC_PRLL_PRL_Msk
4328 /******************* Bit definition for RTC_DIVH register *******************/
4329 #define RTC_DIVH_RTC_DIV_Pos (0U)
4330 #define RTC_DIVH_RTC_DIV_Msk (0xFUL << RTC_DIVH_RTC_DIV_Pos)
4331 #define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk
4333 /******************* Bit definition for RTC_DIVL register *******************/
4334 #define RTC_DIVL_RTC_DIV_Pos (0U)
4335 #define RTC_DIVL_RTC_DIV_Msk (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos)
4336 #define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk
4338 /******************* Bit definition for RTC_CNTH register *******************/
4339 #define RTC_CNTH_RTC_CNT_Pos (0U)
4340 #define RTC_CNTH_RTC_CNT_Msk (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos)
4341 #define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk
4343 /******************* Bit definition for RTC_CNTL register *******************/
4344 #define RTC_CNTL_RTC_CNT_Pos (0U)
4345 #define RTC_CNTL_RTC_CNT_Msk (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos)
4346 #define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk
4348 /******************* Bit definition for RTC_ALRH register *******************/
4349 #define RTC_ALRH_RTC_ALR_Pos (0U)
4350 #define RTC_ALRH_RTC_ALR_Msk (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos)
4351 #define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk
4353 /******************* Bit definition for RTC_ALRL register *******************/
4354 #define RTC_ALRL_RTC_ALR_Pos (0U)
4355 #define RTC_ALRL_RTC_ALR_Msk (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos)
4356 #define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk
4358 /******************************************************************************/
4359 /* */
4360 /* Independent WATCHDOG (IWDG) */
4361 /* */
4362 /******************************************************************************/
4363 
4364 /******************* Bit definition for IWDG_KR register ********************/
4365 #define IWDG_KR_KEY_Pos (0U)
4366 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
4367 #define IWDG_KR_KEY IWDG_KR_KEY_Msk
4369 /******************* Bit definition for IWDG_PR register ********************/
4370 #define IWDG_PR_PR_Pos (0U)
4371 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
4372 #define IWDG_PR_PR IWDG_PR_PR_Msk
4373 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
4374 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
4375 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
4377 /******************* Bit definition for IWDG_RLR register *******************/
4378 #define IWDG_RLR_RL_Pos (0U)
4379 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
4380 #define IWDG_RLR_RL IWDG_RLR_RL_Msk
4382 /******************* Bit definition for IWDG_SR register ********************/
4383 #define IWDG_SR_PVU_Pos (0U)
4384 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
4385 #define IWDG_SR_PVU IWDG_SR_PVU_Msk
4386 #define IWDG_SR_RVU_Pos (1U)
4387 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
4388 #define IWDG_SR_RVU IWDG_SR_RVU_Msk
4390 /******************************************************************************/
4391 /* */
4392 /* Window WATCHDOG (WWDG) */
4393 /* */
4394 /******************************************************************************/
4395 
4396 /******************* Bit definition for WWDG_CR register ********************/
4397 #define WWDG_CR_T_Pos (0U)
4398 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
4399 #define WWDG_CR_T WWDG_CR_T_Msk
4400 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
4401 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
4402 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
4403 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
4404 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
4405 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
4406 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
4408 /* Legacy defines */
4409 #define WWDG_CR_T0 WWDG_CR_T_0
4410 #define WWDG_CR_T1 WWDG_CR_T_1
4411 #define WWDG_CR_T2 WWDG_CR_T_2
4412 #define WWDG_CR_T3 WWDG_CR_T_3
4413 #define WWDG_CR_T4 WWDG_CR_T_4
4414 #define WWDG_CR_T5 WWDG_CR_T_5
4415 #define WWDG_CR_T6 WWDG_CR_T_6
4416 
4417 #define WWDG_CR_WDGA_Pos (7U)
4418 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
4419 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
4421 /******************* Bit definition for WWDG_CFR register *******************/
4422 #define WWDG_CFR_W_Pos (0U)
4423 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
4424 #define WWDG_CFR_W WWDG_CFR_W_Msk
4425 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
4426 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
4427 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
4428 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
4429 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
4430 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
4431 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
4433 /* Legacy defines */
4434 #define WWDG_CFR_W0 WWDG_CFR_W_0
4435 #define WWDG_CFR_W1 WWDG_CFR_W_1
4436 #define WWDG_CFR_W2 WWDG_CFR_W_2
4437 #define WWDG_CFR_W3 WWDG_CFR_W_3
4438 #define WWDG_CFR_W4 WWDG_CFR_W_4
4439 #define WWDG_CFR_W5 WWDG_CFR_W_5
4440 #define WWDG_CFR_W6 WWDG_CFR_W_6
4441 
4442 #define WWDG_CFR_WDGTB_Pos (7U)
4443 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)
4444 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
4445 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
4446 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
4448 /* Legacy defines */
4449 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
4450 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
4451 
4452 #define WWDG_CFR_EWI_Pos (9U)
4453 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
4454 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
4456 /******************* Bit definition for WWDG_SR register ********************/
4457 #define WWDG_SR_EWIF_Pos (0U)
4458 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
4459 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
4461 /******************************************************************************/
4462 /* */
4463 /* USB Device FS */
4464 /* */
4465 /******************************************************************************/
4466 
4468 #define USB_EP0R USB_BASE
4469 #define USB_EP1R (USB_BASE + 0x00000004)
4470 #define USB_EP2R (USB_BASE + 0x00000008)
4471 #define USB_EP3R (USB_BASE + 0x0000000C)
4472 #define USB_EP4R (USB_BASE + 0x00000010)
4473 #define USB_EP5R (USB_BASE + 0x00000014)
4474 #define USB_EP6R (USB_BASE + 0x00000018)
4475 #define USB_EP7R (USB_BASE + 0x0000001C)
4477 /* bit positions */
4478 #define USB_EP_CTR_RX_Pos (15U)
4479 #define USB_EP_CTR_RX_Msk (0x1UL << USB_EP_CTR_RX_Pos)
4480 #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk
4481 #define USB_EP_DTOG_RX_Pos (14U)
4482 #define USB_EP_DTOG_RX_Msk (0x1UL << USB_EP_DTOG_RX_Pos)
4483 #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk
4484 #define USB_EPRX_STAT_Pos (12U)
4485 #define USB_EPRX_STAT_Msk (0x3UL << USB_EPRX_STAT_Pos)
4486 #define USB_EPRX_STAT USB_EPRX_STAT_Msk
4487 #define USB_EP_SETUP_Pos (11U)
4488 #define USB_EP_SETUP_Msk (0x1UL << USB_EP_SETUP_Pos)
4489 #define USB_EP_SETUP USB_EP_SETUP_Msk
4490 #define USB_EP_T_FIELD_Pos (9U)
4491 #define USB_EP_T_FIELD_Msk (0x3UL << USB_EP_T_FIELD_Pos)
4492 #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk
4493 #define USB_EP_KIND_Pos (8U)
4494 #define USB_EP_KIND_Msk (0x1UL << USB_EP_KIND_Pos)
4495 #define USB_EP_KIND USB_EP_KIND_Msk
4496 #define USB_EP_CTR_TX_Pos (7U)
4497 #define USB_EP_CTR_TX_Msk (0x1UL << USB_EP_CTR_TX_Pos)
4498 #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk
4499 #define USB_EP_DTOG_TX_Pos (6U)
4500 #define USB_EP_DTOG_TX_Msk (0x1UL << USB_EP_DTOG_TX_Pos)
4501 #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk
4502 #define USB_EPTX_STAT_Pos (4U)
4503 #define USB_EPTX_STAT_Msk (0x3UL << USB_EPTX_STAT_Pos)
4504 #define USB_EPTX_STAT USB_EPTX_STAT_Msk
4505 #define USB_EPADDR_FIELD_Pos (0U)
4506 #define USB_EPADDR_FIELD_Msk (0xFUL << USB_EPADDR_FIELD_Pos)
4507 #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk
4509 /* EndPoint REGister MASK (no toggle fields) */
4510 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
4511 
4512 #define USB_EP_TYPE_MASK_Pos (9U)
4513 #define USB_EP_TYPE_MASK_Msk (0x3UL << USB_EP_TYPE_MASK_Pos)
4514 #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk
4515 #define USB_EP_BULK 0x00000000U
4516 #define USB_EP_CONTROL 0x00000200U
4517 #define USB_EP_ISOCHRONOUS 0x00000400U
4518 #define USB_EP_INTERRUPT 0x00000600U
4519 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
4520 
4521 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK)
4523 #define USB_EP_TX_DIS 0x00000000U
4524 #define USB_EP_TX_STALL 0x00000010U
4525 #define USB_EP_TX_NAK 0x00000020U
4526 #define USB_EP_TX_VALID 0x00000030U
4527 #define USB_EPTX_DTOG1 0x00000010U
4528 #define USB_EPTX_DTOG2 0x00000020U
4529 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
4530 
4531 #define USB_EP_RX_DIS 0x00000000U
4532 #define USB_EP_RX_STALL 0x00001000U
4533 #define USB_EP_RX_NAK 0x00002000U
4534 #define USB_EP_RX_VALID 0x00003000U
4535 #define USB_EPRX_DTOG1 0x00001000U
4536 #define USB_EPRX_DTOG2 0x00002000U
4537 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
4538 
4539 /******************* Bit definition for USB_EP0R register *******************/
4540 #define USB_EP0R_EA_Pos (0U)
4541 #define USB_EP0R_EA_Msk (0xFUL << USB_EP0R_EA_Pos)
4542 #define USB_EP0R_EA USB_EP0R_EA_Msk
4544 #define USB_EP0R_STAT_TX_Pos (4U)
4545 #define USB_EP0R_STAT_TX_Msk (0x3UL << USB_EP0R_STAT_TX_Pos)
4546 #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk
4547 #define USB_EP0R_STAT_TX_0 (0x1UL << USB_EP0R_STAT_TX_Pos)
4548 #define USB_EP0R_STAT_TX_1 (0x2UL << USB_EP0R_STAT_TX_Pos)
4550 #define USB_EP0R_DTOG_TX_Pos (6U)
4551 #define USB_EP0R_DTOG_TX_Msk (0x1UL << USB_EP0R_DTOG_TX_Pos)
4552 #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk
4553 #define USB_EP0R_CTR_TX_Pos (7U)
4554 #define USB_EP0R_CTR_TX_Msk (0x1UL << USB_EP0R_CTR_TX_Pos)
4555 #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk
4556 #define USB_EP0R_EP_KIND_Pos (8U)
4557 #define USB_EP0R_EP_KIND_Msk (0x1UL << USB_EP0R_EP_KIND_Pos)
4558 #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk
4560 #define USB_EP0R_EP_TYPE_Pos (9U)
4561 #define USB_EP0R_EP_TYPE_Msk (0x3UL << USB_EP0R_EP_TYPE_Pos)
4562 #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk
4563 #define USB_EP0R_EP_TYPE_0 (0x1UL << USB_EP0R_EP_TYPE_Pos)
4564 #define USB_EP0R_EP_TYPE_1 (0x2UL << USB_EP0R_EP_TYPE_Pos)
4566 #define USB_EP0R_SETUP_Pos (11U)
4567 #define USB_EP0R_SETUP_Msk (0x1UL << USB_EP0R_SETUP_Pos)
4568 #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk
4570 #define USB_EP0R_STAT_RX_Pos (12U)
4571 #define USB_EP0R_STAT_RX_Msk (0x3UL << USB_EP0R_STAT_RX_Pos)
4572 #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk
4573 #define USB_EP0R_STAT_RX_0 (0x1UL << USB_EP0R_STAT_RX_Pos)
4574 #define USB_EP0R_STAT_RX_1 (0x2UL << USB_EP0R_STAT_RX_Pos)
4576 #define USB_EP0R_DTOG_RX_Pos (14U)
4577 #define USB_EP0R_DTOG_RX_Msk (0x1UL << USB_EP0R_DTOG_RX_Pos)
4578 #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk
4579 #define USB_EP0R_CTR_RX_Pos (15U)
4580 #define USB_EP0R_CTR_RX_Msk (0x1UL << USB_EP0R_CTR_RX_Pos)
4581 #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk
4583 /******************* Bit definition for USB_EP1R register *******************/
4584 #define USB_EP1R_EA_Pos (0U)
4585 #define USB_EP1R_EA_Msk (0xFUL << USB_EP1R_EA_Pos)
4586 #define USB_EP1R_EA USB_EP1R_EA_Msk
4588 #define USB_EP1R_STAT_TX_Pos (4U)
4589 #define USB_EP1R_STAT_TX_Msk (0x3UL << USB_EP1R_STAT_TX_Pos)
4590 #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk
4591 #define USB_EP1R_STAT_TX_0 (0x1UL << USB_EP1R_STAT_TX_Pos)
4592 #define USB_EP1R_STAT_TX_1 (0x2UL << USB_EP1R_STAT_TX_Pos)
4594 #define USB_EP1R_DTOG_TX_Pos (6U)
4595 #define USB_EP1R_DTOG_TX_Msk (0x1UL << USB_EP1R_DTOG_TX_Pos)
4596 #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk
4597 #define USB_EP1R_CTR_TX_Pos (7U)
4598 #define USB_EP1R_CTR_TX_Msk (0x1UL << USB_EP1R_CTR_TX_Pos)
4599 #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk
4600 #define USB_EP1R_EP_KIND_Pos (8U)
4601 #define USB_EP1R_EP_KIND_Msk (0x1UL << USB_EP1R_EP_KIND_Pos)
4602 #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk
4604 #define USB_EP1R_EP_TYPE_Pos (9U)
4605 #define USB_EP1R_EP_TYPE_Msk (0x3UL << USB_EP1R_EP_TYPE_Pos)
4606 #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk
4607 #define USB_EP1R_EP_TYPE_0 (0x1UL << USB_EP1R_EP_TYPE_Pos)
4608 #define USB_EP1R_EP_TYPE_1 (0x2UL << USB_EP1R_EP_TYPE_Pos)
4610 #define USB_EP1R_SETUP_Pos (11U)
4611 #define USB_EP1R_SETUP_Msk (0x1UL << USB_EP1R_SETUP_Pos)
4612 #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk
4614 #define USB_EP1R_STAT_RX_Pos (12U)
4615 #define USB_EP1R_STAT_RX_Msk (0x3UL << USB_EP1R_STAT_RX_Pos)
4616 #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk
4617 #define USB_EP1R_STAT_RX_0 (0x1UL << USB_EP1R_STAT_RX_Pos)
4618 #define USB_EP1R_STAT_RX_1 (0x2UL << USB_EP1R_STAT_RX_Pos)
4620 #define USB_EP1R_DTOG_RX_Pos (14U)
4621 #define USB_EP1R_DTOG_RX_Msk (0x1UL << USB_EP1R_DTOG_RX_Pos)
4622 #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk
4623 #define USB_EP1R_CTR_RX_Pos (15U)
4624 #define USB_EP1R_CTR_RX_Msk (0x1UL << USB_EP1R_CTR_RX_Pos)
4625 #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk
4627 /******************* Bit definition for USB_EP2R register *******************/
4628 #define USB_EP2R_EA_Pos (0U)
4629 #define USB_EP2R_EA_Msk (0xFUL << USB_EP2R_EA_Pos)
4630 #define USB_EP2R_EA USB_EP2R_EA_Msk
4632 #define USB_EP2R_STAT_TX_Pos (4U)
4633 #define USB_EP2R_STAT_TX_Msk (0x3UL << USB_EP2R_STAT_TX_Pos)
4634 #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk
4635 #define USB_EP2R_STAT_TX_0 (0x1UL << USB_EP2R_STAT_TX_Pos)
4636 #define USB_EP2R_STAT_TX_1 (0x2UL << USB_EP2R_STAT_TX_Pos)
4638 #define USB_EP2R_DTOG_TX_Pos (6U)
4639 #define USB_EP2R_DTOG_TX_Msk (0x1UL << USB_EP2R_DTOG_TX_Pos)
4640 #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk
4641 #define USB_EP2R_CTR_TX_Pos (7U)
4642 #define USB_EP2R_CTR_TX_Msk (0x1UL << USB_EP2R_CTR_TX_Pos)
4643 #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk
4644 #define USB_EP2R_EP_KIND_Pos (8U)
4645 #define USB_EP2R_EP_KIND_Msk (0x1UL << USB_EP2R_EP_KIND_Pos)
4646 #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk
4648 #define USB_EP2R_EP_TYPE_Pos (9U)
4649 #define USB_EP2R_EP_TYPE_Msk (0x3UL << USB_EP2R_EP_TYPE_Pos)
4650 #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk
4651 #define USB_EP2R_EP_TYPE_0 (0x1UL << USB_EP2R_EP_TYPE_Pos)
4652 #define USB_EP2R_EP_TYPE_1 (0x2UL << USB_EP2R_EP_TYPE_Pos)
4654 #define USB_EP2R_SETUP_Pos (11U)
4655 #define USB_EP2R_SETUP_Msk (0x1UL << USB_EP2R_SETUP_Pos)
4656 #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk
4658 #define USB_EP2R_STAT_RX_Pos (12U)
4659 #define USB_EP2R_STAT_RX_Msk (0x3UL << USB_EP2R_STAT_RX_Pos)
4660 #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk
4661 #define USB_EP2R_STAT_RX_0 (0x1UL << USB_EP2R_STAT_RX_Pos)
4662 #define USB_EP2R_STAT_RX_1 (0x2UL << USB_EP2R_STAT_RX_Pos)
4664 #define USB_EP2R_DTOG_RX_Pos (14U)
4665 #define USB_EP2R_DTOG_RX_Msk (0x1UL << USB_EP2R_DTOG_RX_Pos)
4666 #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk
4667 #define USB_EP2R_CTR_RX_Pos (15U)
4668 #define USB_EP2R_CTR_RX_Msk (0x1UL << USB_EP2R_CTR_RX_Pos)
4669 #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk
4671 /******************* Bit definition for USB_EP3R register *******************/
4672 #define USB_EP3R_EA_Pos (0U)
4673 #define USB_EP3R_EA_Msk (0xFUL << USB_EP3R_EA_Pos)
4674 #define USB_EP3R_EA USB_EP3R_EA_Msk
4676 #define USB_EP3R_STAT_TX_Pos (4U)
4677 #define USB_EP3R_STAT_TX_Msk (0x3UL << USB_EP3R_STAT_TX_Pos)
4678 #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk
4679 #define USB_EP3R_STAT_TX_0 (0x1UL << USB_EP3R_STAT_TX_Pos)
4680 #define USB_EP3R_STAT_TX_1 (0x2UL << USB_EP3R_STAT_TX_Pos)
4682 #define USB_EP3R_DTOG_TX_Pos (6U)
4683 #define USB_EP3R_DTOG_TX_Msk (0x1UL << USB_EP3R_DTOG_TX_Pos)
4684 #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk
4685 #define USB_EP3R_CTR_TX_Pos (7U)
4686 #define USB_EP3R_CTR_TX_Msk (0x1UL << USB_EP3R_CTR_TX_Pos)
4687 #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk
4688 #define USB_EP3R_EP_KIND_Pos (8U)
4689 #define USB_EP3R_EP_KIND_Msk (0x1UL << USB_EP3R_EP_KIND_Pos)
4690 #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk
4692 #define USB_EP3R_EP_TYPE_Pos (9U)
4693 #define USB_EP3R_EP_TYPE_Msk (0x3UL << USB_EP3R_EP_TYPE_Pos)
4694 #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk
4695 #define USB_EP3R_EP_TYPE_0 (0x1UL << USB_EP3R_EP_TYPE_Pos)
4696 #define USB_EP3R_EP_TYPE_1 (0x2UL << USB_EP3R_EP_TYPE_Pos)
4698 #define USB_EP3R_SETUP_Pos (11U)
4699 #define USB_EP3R_SETUP_Msk (0x1UL << USB_EP3R_SETUP_Pos)
4700 #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk
4702 #define USB_EP3R_STAT_RX_Pos (12U)
4703 #define USB_EP3R_STAT_RX_Msk (0x3UL << USB_EP3R_STAT_RX_Pos)
4704 #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk
4705 #define USB_EP3R_STAT_RX_0 (0x1UL << USB_EP3R_STAT_RX_Pos)
4706 #define USB_EP3R_STAT_RX_1 (0x2UL << USB_EP3R_STAT_RX_Pos)
4708 #define USB_EP3R_DTOG_RX_Pos (14U)
4709 #define USB_EP3R_DTOG_RX_Msk (0x1UL << USB_EP3R_DTOG_RX_Pos)
4710 #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk
4711 #define USB_EP3R_CTR_RX_Pos (15U)
4712 #define USB_EP3R_CTR_RX_Msk (0x1UL << USB_EP3R_CTR_RX_Pos)
4713 #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk
4715 /******************* Bit definition for USB_EP4R register *******************/
4716 #define USB_EP4R_EA_Pos (0U)
4717 #define USB_EP4R_EA_Msk (0xFUL << USB_EP4R_EA_Pos)
4718 #define USB_EP4R_EA USB_EP4R_EA_Msk
4720 #define USB_EP4R_STAT_TX_Pos (4U)
4721 #define USB_EP4R_STAT_TX_Msk (0x3UL << USB_EP4R_STAT_TX_Pos)
4722 #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk
4723 #define USB_EP4R_STAT_TX_0 (0x1UL << USB_EP4R_STAT_TX_Pos)
4724 #define USB_EP4R_STAT_TX_1 (0x2UL << USB_EP4R_STAT_TX_Pos)
4726 #define USB_EP4R_DTOG_TX_Pos (6U)
4727 #define USB_EP4R_DTOG_TX_Msk (0x1UL << USB_EP4R_DTOG_TX_Pos)
4728 #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk
4729 #define USB_EP4R_CTR_TX_Pos (7U)
4730 #define USB_EP4R_CTR_TX_Msk (0x1UL << USB_EP4R_CTR_TX_Pos)
4731 #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk
4732 #define USB_EP4R_EP_KIND_Pos (8U)
4733 #define USB_EP4R_EP_KIND_Msk (0x1UL << USB_EP4R_EP_KIND_Pos)
4734 #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk
4736 #define USB_EP4R_EP_TYPE_Pos (9U)
4737 #define USB_EP4R_EP_TYPE_Msk (0x3UL << USB_EP4R_EP_TYPE_Pos)
4738 #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk
4739 #define USB_EP4R_EP_TYPE_0 (0x1UL << USB_EP4R_EP_TYPE_Pos)
4740 #define USB_EP4R_EP_TYPE_1 (0x2UL << USB_EP4R_EP_TYPE_Pos)
4742 #define USB_EP4R_SETUP_Pos (11U)
4743 #define USB_EP4R_SETUP_Msk (0x1UL << USB_EP4R_SETUP_Pos)
4744 #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk
4746 #define USB_EP4R_STAT_RX_Pos (12U)
4747 #define USB_EP4R_STAT_RX_Msk (0x3UL << USB_EP4R_STAT_RX_Pos)
4748 #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk
4749 #define USB_EP4R_STAT_RX_0 (0x1UL << USB_EP4R_STAT_RX_Pos)
4750 #define USB_EP4R_STAT_RX_1 (0x2UL << USB_EP4R_STAT_RX_Pos)
4752 #define USB_EP4R_DTOG_RX_Pos (14U)
4753 #define USB_EP4R_DTOG_RX_Msk (0x1UL << USB_EP4R_DTOG_RX_Pos)
4754 #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk
4755 #define USB_EP4R_CTR_RX_Pos (15U)
4756 #define USB_EP4R_CTR_RX_Msk (0x1UL << USB_EP4R_CTR_RX_Pos)
4757 #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk
4759 /******************* Bit definition for USB_EP5R register *******************/
4760 #define USB_EP5R_EA_Pos (0U)
4761 #define USB_EP5R_EA_Msk (0xFUL << USB_EP5R_EA_Pos)
4762 #define USB_EP5R_EA USB_EP5R_EA_Msk
4764 #define USB_EP5R_STAT_TX_Pos (4U)
4765 #define USB_EP5R_STAT_TX_Msk (0x3UL << USB_EP5R_STAT_TX_Pos)
4766 #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk
4767 #define USB_EP5R_STAT_TX_0 (0x1UL << USB_EP5R_STAT_TX_Pos)
4768 #define USB_EP5R_STAT_TX_1 (0x2UL << USB_EP5R_STAT_TX_Pos)
4770 #define USB_EP5R_DTOG_TX_Pos (6U)
4771 #define USB_EP5R_DTOG_TX_Msk (0x1UL << USB_EP5R_DTOG_TX_Pos)
4772 #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk
4773 #define USB_EP5R_CTR_TX_Pos (7U)
4774 #define USB_EP5R_CTR_TX_Msk (0x1UL << USB_EP5R_CTR_TX_Pos)
4775 #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk
4776 #define USB_EP5R_EP_KIND_Pos (8U)
4777 #define USB_EP5R_EP_KIND_Msk (0x1UL << USB_EP5R_EP_KIND_Pos)
4778 #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk
4780 #define USB_EP5R_EP_TYPE_Pos (9U)
4781 #define USB_EP5R_EP_TYPE_Msk (0x3UL << USB_EP5R_EP_TYPE_Pos)
4782 #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk
4783 #define USB_EP5R_EP_TYPE_0 (0x1UL << USB_EP5R_EP_TYPE_Pos)
4784 #define USB_EP5R_EP_TYPE_1 (0x2UL << USB_EP5R_EP_TYPE_Pos)
4786 #define USB_EP5R_SETUP_Pos (11U)
4787 #define USB_EP5R_SETUP_Msk (0x1UL << USB_EP5R_SETUP_Pos)
4788 #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk
4790 #define USB_EP5R_STAT_RX_Pos (12U)
4791 #define USB_EP5R_STAT_RX_Msk (0x3UL << USB_EP5R_STAT_RX_Pos)
4792 #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk
4793 #define USB_EP5R_STAT_RX_0 (0x1UL << USB_EP5R_STAT_RX_Pos)
4794 #define USB_EP5R_STAT_RX_1 (0x2UL << USB_EP5R_STAT_RX_Pos)
4796 #define USB_EP5R_DTOG_RX_Pos (14U)
4797 #define USB_EP5R_DTOG_RX_Msk (0x1UL << USB_EP5R_DTOG_RX_Pos)
4798 #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk
4799 #define USB_EP5R_CTR_RX_Pos (15U)
4800 #define USB_EP5R_CTR_RX_Msk (0x1UL << USB_EP5R_CTR_RX_Pos)
4801 #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk
4803 /******************* Bit definition for USB_EP6R register *******************/
4804 #define USB_EP6R_EA_Pos (0U)
4805 #define USB_EP6R_EA_Msk (0xFUL << USB_EP6R_EA_Pos)
4806 #define USB_EP6R_EA USB_EP6R_EA_Msk
4808 #define USB_EP6R_STAT_TX_Pos (4U)
4809 #define USB_EP6R_STAT_TX_Msk (0x3UL << USB_EP6R_STAT_TX_Pos)
4810 #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk
4811 #define USB_EP6R_STAT_TX_0 (0x1UL << USB_EP6R_STAT_TX_Pos)
4812 #define USB_EP6R_STAT_TX_1 (0x2UL << USB_EP6R_STAT_TX_Pos)
4814 #define USB_EP6R_DTOG_TX_Pos (6U)
4815 #define USB_EP6R_DTOG_TX_Msk (0x1UL << USB_EP6R_DTOG_TX_Pos)
4816 #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk
4817 #define USB_EP6R_CTR_TX_Pos (7U)
4818 #define USB_EP6R_CTR_TX_Msk (0x1UL << USB_EP6R_CTR_TX_Pos)
4819 #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk
4820 #define USB_EP6R_EP_KIND_Pos (8U)
4821 #define USB_EP6R_EP_KIND_Msk (0x1UL << USB_EP6R_EP_KIND_Pos)
4822 #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk
4824 #define USB_EP6R_EP_TYPE_Pos (9U)
4825 #define USB_EP6R_EP_TYPE_Msk (0x3UL << USB_EP6R_EP_TYPE_Pos)
4826 #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk
4827 #define USB_EP6R_EP_TYPE_0 (0x1UL << USB_EP6R_EP_TYPE_Pos)
4828 #define USB_EP6R_EP_TYPE_1 (0x2UL << USB_EP6R_EP_TYPE_Pos)
4830 #define USB_EP6R_SETUP_Pos (11U)
4831 #define USB_EP6R_SETUP_Msk (0x1UL << USB_EP6R_SETUP_Pos)
4832 #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk
4834 #define USB_EP6R_STAT_RX_Pos (12U)
4835 #define USB_EP6R_STAT_RX_Msk (0x3UL << USB_EP6R_STAT_RX_Pos)
4836 #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk
4837 #define USB_EP6R_STAT_RX_0 (0x1UL << USB_EP6R_STAT_RX_Pos)
4838 #define USB_EP6R_STAT_RX_1 (0x2UL << USB_EP6R_STAT_RX_Pos)
4840 #define USB_EP6R_DTOG_RX_Pos (14U)
4841 #define USB_EP6R_DTOG_RX_Msk (0x1UL << USB_EP6R_DTOG_RX_Pos)
4842 #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk
4843 #define USB_EP6R_CTR_RX_Pos (15U)
4844 #define USB_EP6R_CTR_RX_Msk (0x1UL << USB_EP6R_CTR_RX_Pos)
4845 #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk
4847 /******************* Bit definition for USB_EP7R register *******************/
4848 #define USB_EP7R_EA_Pos (0U)
4849 #define USB_EP7R_EA_Msk (0xFUL << USB_EP7R_EA_Pos)
4850 #define USB_EP7R_EA USB_EP7R_EA_Msk
4852 #define USB_EP7R_STAT_TX_Pos (4U)
4853 #define USB_EP7R_STAT_TX_Msk (0x3UL << USB_EP7R_STAT_TX_Pos)
4854 #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk
4855 #define USB_EP7R_STAT_TX_0 (0x1UL << USB_EP7R_STAT_TX_Pos)
4856 #define USB_EP7R_STAT_TX_1 (0x2UL << USB_EP7R_STAT_TX_Pos)
4858 #define USB_EP7R_DTOG_TX_Pos (6U)
4859 #define USB_EP7R_DTOG_TX_Msk (0x1UL << USB_EP7R_DTOG_TX_Pos)
4860 #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk
4861 #define USB_EP7R_CTR_TX_Pos (7U)
4862 #define USB_EP7R_CTR_TX_Msk (0x1UL << USB_EP7R_CTR_TX_Pos)
4863 #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk
4864 #define USB_EP7R_EP_KIND_Pos (8U)
4865 #define USB_EP7R_EP_KIND_Msk (0x1UL << USB_EP7R_EP_KIND_Pos)
4866 #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk
4868 #define USB_EP7R_EP_TYPE_Pos (9U)
4869 #define USB_EP7R_EP_TYPE_Msk (0x3UL << USB_EP7R_EP_TYPE_Pos)
4870 #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk
4871 #define USB_EP7R_EP_TYPE_0 (0x1UL << USB_EP7R_EP_TYPE_Pos)
4872 #define USB_EP7R_EP_TYPE_1 (0x2UL << USB_EP7R_EP_TYPE_Pos)
4874 #define USB_EP7R_SETUP_Pos (11U)
4875 #define USB_EP7R_SETUP_Msk (0x1UL << USB_EP7R_SETUP_Pos)
4876 #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk
4878 #define USB_EP7R_STAT_RX_Pos (12U)
4879 #define USB_EP7R_STAT_RX_Msk (0x3UL << USB_EP7R_STAT_RX_Pos)
4880 #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk
4881 #define USB_EP7R_STAT_RX_0 (0x1UL << USB_EP7R_STAT_RX_Pos)
4882 #define USB_EP7R_STAT_RX_1 (0x2UL << USB_EP7R_STAT_RX_Pos)
4884 #define USB_EP7R_DTOG_RX_Pos (14U)
4885 #define USB_EP7R_DTOG_RX_Msk (0x1UL << USB_EP7R_DTOG_RX_Pos)
4886 #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk
4887 #define USB_EP7R_CTR_RX_Pos (15U)
4888 #define USB_EP7R_CTR_RX_Msk (0x1UL << USB_EP7R_CTR_RX_Pos)
4889 #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk
4892 /******************* Bit definition for USB_CNTR register *******************/
4893 #define USB_CNTR_FRES_Pos (0U)
4894 #define USB_CNTR_FRES_Msk (0x1UL << USB_CNTR_FRES_Pos)
4895 #define USB_CNTR_FRES USB_CNTR_FRES_Msk
4896 #define USB_CNTR_PDWN_Pos (1U)
4897 #define USB_CNTR_PDWN_Msk (0x1UL << USB_CNTR_PDWN_Pos)
4898 #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk
4899 #define USB_CNTR_LP_MODE_Pos (2U)
4900 #define USB_CNTR_LP_MODE_Msk (0x1UL << USB_CNTR_LP_MODE_Pos)
4901 #define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk
4902 #define USB_CNTR_FSUSP_Pos (3U)
4903 #define USB_CNTR_FSUSP_Msk (0x1UL << USB_CNTR_FSUSP_Pos)
4904 #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk
4905 #define USB_CNTR_RESUME_Pos (4U)
4906 #define USB_CNTR_RESUME_Msk (0x1UL << USB_CNTR_RESUME_Pos)
4907 #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk
4908 #define USB_CNTR_ESOFM_Pos (8U)
4909 #define USB_CNTR_ESOFM_Msk (0x1UL << USB_CNTR_ESOFM_Pos)
4910 #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk
4911 #define USB_CNTR_SOFM_Pos (9U)
4912 #define USB_CNTR_SOFM_Msk (0x1UL << USB_CNTR_SOFM_Pos)
4913 #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk
4914 #define USB_CNTR_RESETM_Pos (10U)
4915 #define USB_CNTR_RESETM_Msk (0x1UL << USB_CNTR_RESETM_Pos)
4916 #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk
4917 #define USB_CNTR_SUSPM_Pos (11U)
4918 #define USB_CNTR_SUSPM_Msk (0x1UL << USB_CNTR_SUSPM_Pos)
4919 #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk
4920 #define USB_CNTR_WKUPM_Pos (12U)
4921 #define USB_CNTR_WKUPM_Msk (0x1UL << USB_CNTR_WKUPM_Pos)
4922 #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk
4923 #define USB_CNTR_ERRM_Pos (13U)
4924 #define USB_CNTR_ERRM_Msk (0x1UL << USB_CNTR_ERRM_Pos)
4925 #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk
4926 #define USB_CNTR_PMAOVRM_Pos (14U)
4927 #define USB_CNTR_PMAOVRM_Msk (0x1UL << USB_CNTR_PMAOVRM_Pos)
4928 #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk
4929 #define USB_CNTR_CTRM_Pos (15U)
4930 #define USB_CNTR_CTRM_Msk (0x1UL << USB_CNTR_CTRM_Pos)
4931 #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk
4933 /******************* Bit definition for USB_ISTR register *******************/
4934 #define USB_ISTR_EP_ID_Pos (0U)
4935 #define USB_ISTR_EP_ID_Msk (0xFUL << USB_ISTR_EP_ID_Pos)
4936 #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk
4937 #define USB_ISTR_DIR_Pos (4U)
4938 #define USB_ISTR_DIR_Msk (0x1UL << USB_ISTR_DIR_Pos)
4939 #define USB_ISTR_DIR USB_ISTR_DIR_Msk
4940 #define USB_ISTR_ESOF_Pos (8U)
4941 #define USB_ISTR_ESOF_Msk (0x1UL << USB_ISTR_ESOF_Pos)
4942 #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk
4943 #define USB_ISTR_SOF_Pos (9U)
4944 #define USB_ISTR_SOF_Msk (0x1UL << USB_ISTR_SOF_Pos)
4945 #define USB_ISTR_SOF USB_ISTR_SOF_Msk
4946 #define USB_ISTR_RESET_Pos (10U)
4947 #define USB_ISTR_RESET_Msk (0x1UL << USB_ISTR_RESET_Pos)
4948 #define USB_ISTR_RESET USB_ISTR_RESET_Msk
4949 #define USB_ISTR_SUSP_Pos (11U)
4950 #define USB_ISTR_SUSP_Msk (0x1UL << USB_ISTR_SUSP_Pos)
4951 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk
4952 #define USB_ISTR_WKUP_Pos (12U)
4953 #define USB_ISTR_WKUP_Msk (0x1UL << USB_ISTR_WKUP_Pos)
4954 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk
4955 #define USB_ISTR_ERR_Pos (13U)
4956 #define USB_ISTR_ERR_Msk (0x1UL << USB_ISTR_ERR_Pos)
4957 #define USB_ISTR_ERR USB_ISTR_ERR_Msk
4958 #define USB_ISTR_PMAOVR_Pos (14U)
4959 #define USB_ISTR_PMAOVR_Msk (0x1UL << USB_ISTR_PMAOVR_Pos)
4960 #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk
4961 #define USB_ISTR_CTR_Pos (15U)
4962 #define USB_ISTR_CTR_Msk (0x1UL << USB_ISTR_CTR_Pos)
4963 #define USB_ISTR_CTR USB_ISTR_CTR_Msk
4965 /******************* Bit definition for USB_FNR register ********************/
4966 #define USB_FNR_FN_Pos (0U)
4967 #define USB_FNR_FN_Msk (0x7FFUL << USB_FNR_FN_Pos)
4968 #define USB_FNR_FN USB_FNR_FN_Msk
4969 #define USB_FNR_LSOF_Pos (11U)
4970 #define USB_FNR_LSOF_Msk (0x3UL << USB_FNR_LSOF_Pos)
4971 #define USB_FNR_LSOF USB_FNR_LSOF_Msk
4972 #define USB_FNR_LCK_Pos (13U)
4973 #define USB_FNR_LCK_Msk (0x1UL << USB_FNR_LCK_Pos)
4974 #define USB_FNR_LCK USB_FNR_LCK_Msk
4975 #define USB_FNR_RXDM_Pos (14U)
4976 #define USB_FNR_RXDM_Msk (0x1UL << USB_FNR_RXDM_Pos)
4977 #define USB_FNR_RXDM USB_FNR_RXDM_Msk
4978 #define USB_FNR_RXDP_Pos (15U)
4979 #define USB_FNR_RXDP_Msk (0x1UL << USB_FNR_RXDP_Pos)
4980 #define USB_FNR_RXDP USB_FNR_RXDP_Msk
4982 /****************** Bit definition for USB_DADDR register *******************/
4983 #define USB_DADDR_ADD_Pos (0U)
4984 #define USB_DADDR_ADD_Msk (0x7FUL << USB_DADDR_ADD_Pos)
4985 #define USB_DADDR_ADD USB_DADDR_ADD_Msk
4986 #define USB_DADDR_ADD0_Pos (0U)
4987 #define USB_DADDR_ADD0_Msk (0x1UL << USB_DADDR_ADD0_Pos)
4988 #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk
4989 #define USB_DADDR_ADD1_Pos (1U)
4990 #define USB_DADDR_ADD1_Msk (0x1UL << USB_DADDR_ADD1_Pos)
4991 #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk
4992 #define USB_DADDR_ADD2_Pos (2U)
4993 #define USB_DADDR_ADD2_Msk (0x1UL << USB_DADDR_ADD2_Pos)
4994 #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk
4995 #define USB_DADDR_ADD3_Pos (3U)
4996 #define USB_DADDR_ADD3_Msk (0x1UL << USB_DADDR_ADD3_Pos)
4997 #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk
4998 #define USB_DADDR_ADD4_Pos (4U)
4999 #define USB_DADDR_ADD4_Msk (0x1UL << USB_DADDR_ADD4_Pos)
5000 #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk
5001 #define USB_DADDR_ADD5_Pos (5U)
5002 #define USB_DADDR_ADD5_Msk (0x1UL << USB_DADDR_ADD5_Pos)
5003 #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk
5004 #define USB_DADDR_ADD6_Pos (6U)
5005 #define USB_DADDR_ADD6_Msk (0x1UL << USB_DADDR_ADD6_Pos)
5006 #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk
5008 #define USB_DADDR_EF_Pos (7U)
5009 #define USB_DADDR_EF_Msk (0x1UL << USB_DADDR_EF_Pos)
5010 #define USB_DADDR_EF USB_DADDR_EF_Msk
5012 /****************** Bit definition for USB_BTABLE register ******************/
5013 #define USB_BTABLE_BTABLE_Pos (3U)
5014 #define USB_BTABLE_BTABLE_Msk (0x1FFFUL << USB_BTABLE_BTABLE_Pos)
5015 #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk
5018 /***************** Bit definition for USB_ADDR0_TX register *****************/
5019 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
5020 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos)
5021 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk
5023 /***************** Bit definition for USB_ADDR1_TX register *****************/
5024 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
5025 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos)
5026 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk
5028 /***************** Bit definition for USB_ADDR2_TX register *****************/
5029 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
5030 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos)
5031 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk
5033 /***************** Bit definition for USB_ADDR3_TX register *****************/
5034 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
5035 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos)
5036 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk
5038 /***************** Bit definition for USB_ADDR4_TX register *****************/
5039 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
5040 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos)
5041 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk
5043 /***************** Bit definition for USB_ADDR5_TX register *****************/
5044 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
5045 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos)
5046 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk
5048 /***************** Bit definition for USB_ADDR6_TX register *****************/
5049 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
5050 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos)
5051 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk
5053 /***************** Bit definition for USB_ADDR7_TX register *****************/
5054 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
5055 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos)
5056 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk
5058 /*----------------------------------------------------------------------------*/
5059 
5060 /***************** Bit definition for USB_COUNT0_TX register ****************/
5061 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
5062 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos)
5063 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk
5065 /***************** Bit definition for USB_COUNT1_TX register ****************/
5066 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
5067 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos)
5068 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk
5070 /***************** Bit definition for USB_COUNT2_TX register ****************/
5071 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
5072 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos)
5073 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk
5075 /***************** Bit definition for USB_COUNT3_TX register ****************/
5076 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
5077 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos)
5078 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk
5080 /***************** Bit definition for USB_COUNT4_TX register ****************/
5081 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
5082 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos)
5083 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk
5085 /***************** Bit definition for USB_COUNT5_TX register ****************/
5086 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
5087 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos)
5088 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk
5090 /***************** Bit definition for USB_COUNT6_TX register ****************/
5091 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
5092 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos)
5093 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk
5095 /***************** Bit definition for USB_COUNT7_TX register ****************/
5096 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
5097 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos)
5098 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk
5100 /*----------------------------------------------------------------------------*/
5101 
5102 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
5103 #define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU
5105 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
5106 #define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U
5108 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
5109 #define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU
5111 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
5112 #define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U
5114 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
5115 #define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU
5117 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
5118 #define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U
5120 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
5121 #define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU
5123 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
5124 #define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U
5126 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
5127 #define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU
5129 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
5130 #define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U
5132 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
5133 #define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU
5135 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
5136 #define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U
5138 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
5139 #define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU
5141 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
5142 #define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U
5144 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
5145 #define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU
5147 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
5148 #define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U
5150 /*----------------------------------------------------------------------------*/
5151 
5152 /***************** Bit definition for USB_ADDR0_RX register *****************/
5153 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
5154 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos)
5155 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk
5157 /***************** Bit definition for USB_ADDR1_RX register *****************/
5158 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
5159 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos)
5160 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk
5162 /***************** Bit definition for USB_ADDR2_RX register *****************/
5163 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
5164 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos)
5165 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk
5167 /***************** Bit definition for USB_ADDR3_RX register *****************/
5168 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
5169 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos)
5170 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk
5172 /***************** Bit definition for USB_ADDR4_RX register *****************/
5173 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
5174 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos)
5175 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk
5177 /***************** Bit definition for USB_ADDR5_RX register *****************/
5178 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
5179 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos)
5180 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk
5182 /***************** Bit definition for USB_ADDR6_RX register *****************/
5183 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
5184 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos)
5185 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk
5187 /***************** Bit definition for USB_ADDR7_RX register *****************/
5188 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
5189 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos)
5190 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk
5192 /*----------------------------------------------------------------------------*/
5193 
5194 /***************** Bit definition for USB_COUNT0_RX register ****************/
5195 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
5196 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos)
5197 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk
5199 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
5200 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos)
5201 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk
5202 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos)
5203 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos)
5204 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos)
5205 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos)
5206 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos)
5208 #define USB_COUNT0_RX_BLSIZE_Pos (15U)
5209 #define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos)
5210 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk
5212 /***************** Bit definition for USB_COUNT1_RX register ****************/
5213 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
5214 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos)
5215 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk
5217 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
5218 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos)
5219 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk
5220 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos)
5221 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos)
5222 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos)
5223 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos)
5224 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos)
5226 #define USB_COUNT1_RX_BLSIZE_Pos (15U)
5227 #define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos)
5228 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk
5230 /***************** Bit definition for USB_COUNT2_RX register ****************/
5231 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
5232 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos)
5233 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk
5235 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
5236 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos)
5237 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk
5238 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos)
5239 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos)
5240 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos)
5241 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos)
5242 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos)
5244 #define USB_COUNT2_RX_BLSIZE_Pos (15U)
5245 #define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos)
5246 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk
5248 /***************** Bit definition for USB_COUNT3_RX register ****************/
5249 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
5250 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos)
5251 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk
5253 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
5254 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos)
5255 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk
5256 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos)
5257 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos)
5258 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos)
5259 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos)
5260 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos)
5262 #define USB_COUNT3_RX_BLSIZE_Pos (15U)
5263 #define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos)
5264 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk
5266 /***************** Bit definition for USB_COUNT4_RX register ****************/
5267 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
5268 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos)
5269 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk
5271 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
5272 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos)
5273 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk
5274 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos)
5275 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos)
5276 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos)
5277 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos)
5278 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos)
5280 #define USB_COUNT4_RX_BLSIZE_Pos (15U)
5281 #define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos)
5282 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk
5284 /***************** Bit definition for USB_COUNT5_RX register ****************/
5285 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
5286 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos)
5287 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk
5289 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
5290 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos)
5291 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk
5292 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos)
5293 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos)
5294 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos)
5295 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos)
5296 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos)
5298 #define USB_COUNT5_RX_BLSIZE_Pos (15U)
5299 #define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos)
5300 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk
5302 /***************** Bit definition for USB_COUNT6_RX register ****************/
5303 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
5304 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos)
5305 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk
5307 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
5308 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos)
5309 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk
5310 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos)
5311 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos)
5312 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos)
5313 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos)
5314 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos)
5316 #define USB_COUNT6_RX_BLSIZE_Pos (15U)
5317 #define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos)
5318 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk
5320 /***************** Bit definition for USB_COUNT7_RX register ****************/
5321 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
5322 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos)
5323 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk
5325 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
5326 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos)
5327 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk
5328 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos)
5329 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos)
5330 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos)
5331 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos)
5332 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos)
5334 #define USB_COUNT7_RX_BLSIZE_Pos (15U)
5335 #define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos)
5336 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk
5338 /*----------------------------------------------------------------------------*/
5339 
5340 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
5341 #define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU
5343 #define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U
5344 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U
5345 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U
5346 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U
5347 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U
5348 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U
5350 #define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U
5352 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
5353 #define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U
5355 #define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U
5356 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U
5357 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U
5358 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U
5359 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U
5360 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U
5362 #define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U
5364 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
5365 #define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU
5367 #define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U
5368 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U
5369 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U
5370 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U
5371 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U
5372 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U
5374 #define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U
5376 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
5377 #define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U
5379 #define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U
5380 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U
5381 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U
5382 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U
5383 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U
5384 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U
5386 #define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U
5388 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
5389 #define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU
5391 #define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U
5392 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U
5393 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U
5394 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U
5395 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U
5396 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U
5398 #define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U
5400 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
5401 #define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U
5403 #define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U
5404 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U
5405 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U
5406 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U
5407 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U
5408 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U
5410 #define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U
5412 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
5413 #define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU
5415 #define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U
5416 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U
5417 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U
5418 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U
5419 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U
5420 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U
5422 #define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U
5424 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
5425 #define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U
5427 #define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U
5428 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U
5429 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U
5430 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U
5431 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U
5432 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U
5434 #define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U
5436 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
5437 #define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU
5439 #define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U
5440 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U
5441 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U
5442 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U
5443 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U
5444 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U
5446 #define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U
5448 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
5449 #define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U
5451 #define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U
5452 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U
5453 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U
5454 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U
5455 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U
5456 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U
5458 #define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U
5460 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
5461 #define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU
5463 #define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U
5464 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U
5465 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U
5466 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U
5467 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U
5468 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U
5470 #define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U
5472 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
5473 #define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U
5475 #define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U
5476 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U
5477 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U
5478 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U
5479 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U
5480 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U
5482 #define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U
5484 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
5485 #define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU
5487 #define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U
5488 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U
5489 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U
5490 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U
5491 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U
5492 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U
5494 #define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U
5496 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
5497 #define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U
5499 #define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U
5500 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U
5501 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U
5502 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U
5503 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U
5504 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U
5506 #define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U
5508 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
5509 #define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU
5511 #define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U
5512 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U
5513 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U
5514 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U
5515 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U
5516 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U
5518 #define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U
5520 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
5521 #define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U
5523 #define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U
5524 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U
5525 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U
5526 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U
5527 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U
5528 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U
5530 #define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U
5532 /******************************************************************************/
5533 /* */
5534 /* Controller Area Network */
5535 /* */
5536 /******************************************************************************/
5537 
5539 /******************* Bit definition for CAN_MCR register ********************/
5540 #define CAN_MCR_INRQ_Pos (0U)
5541 #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)
5542 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk
5543 #define CAN_MCR_SLEEP_Pos (1U)
5544 #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)
5545 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk
5546 #define CAN_MCR_TXFP_Pos (2U)
5547 #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)
5548 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk
5549 #define CAN_MCR_RFLM_Pos (3U)
5550 #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)
5551 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk
5552 #define CAN_MCR_NART_Pos (4U)
5553 #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)
5554 #define CAN_MCR_NART CAN_MCR_NART_Msk
5555 #define CAN_MCR_AWUM_Pos (5U)
5556 #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)
5557 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk
5558 #define CAN_MCR_ABOM_Pos (6U)
5559 #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)
5560 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk
5561 #define CAN_MCR_TTCM_Pos (7U)
5562 #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)
5563 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk
5564 #define CAN_MCR_RESET_Pos (15U)
5565 #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)
5566 #define CAN_MCR_RESET CAN_MCR_RESET_Msk
5567 #define CAN_MCR_DBF_Pos (16U)
5568 #define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)
5569 #define CAN_MCR_DBF CAN_MCR_DBF_Msk
5571 /******************* Bit definition for CAN_MSR register ********************/
5572 #define CAN_MSR_INAK_Pos (0U)
5573 #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)
5574 #define CAN_MSR_INAK CAN_MSR_INAK_Msk
5575 #define CAN_MSR_SLAK_Pos (1U)
5576 #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)
5577 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk
5578 #define CAN_MSR_ERRI_Pos (2U)
5579 #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)
5580 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk
5581 #define CAN_MSR_WKUI_Pos (3U)
5582 #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)
5583 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk
5584 #define CAN_MSR_SLAKI_Pos (4U)
5585 #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)
5586 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk
5587 #define CAN_MSR_TXM_Pos (8U)
5588 #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)
5589 #define CAN_MSR_TXM CAN_MSR_TXM_Msk
5590 #define CAN_MSR_RXM_Pos (9U)
5591 #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)
5592 #define CAN_MSR_RXM CAN_MSR_RXM_Msk
5593 #define CAN_MSR_SAMP_Pos (10U)
5594 #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)
5595 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk
5596 #define CAN_MSR_RX_Pos (11U)
5597 #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)
5598 #define CAN_MSR_RX CAN_MSR_RX_Msk
5600 /******************* Bit definition for CAN_TSR register ********************/
5601 #define CAN_TSR_RQCP0_Pos (0U)
5602 #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)
5603 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk
5604 #define CAN_TSR_TXOK0_Pos (1U)
5605 #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)
5606 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk
5607 #define CAN_TSR_ALST0_Pos (2U)
5608 #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)
5609 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk
5610 #define CAN_TSR_TERR0_Pos (3U)
5611 #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)
5612 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk
5613 #define CAN_TSR_ABRQ0_Pos (7U)
5614 #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)
5615 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk
5616 #define CAN_TSR_RQCP1_Pos (8U)
5617 #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)
5618 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk
5619 #define CAN_TSR_TXOK1_Pos (9U)
5620 #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)
5621 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk
5622 #define CAN_TSR_ALST1_Pos (10U)
5623 #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)
5624 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk
5625 #define CAN_TSR_TERR1_Pos (11U)
5626 #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)
5627 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk
5628 #define CAN_TSR_ABRQ1_Pos (15U)
5629 #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)
5630 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk
5631 #define CAN_TSR_RQCP2_Pos (16U)
5632 #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)
5633 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk
5634 #define CAN_TSR_TXOK2_Pos (17U)
5635 #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)
5636 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk
5637 #define CAN_TSR_ALST2_Pos (18U)
5638 #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)
5639 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk
5640 #define CAN_TSR_TERR2_Pos (19U)
5641 #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)
5642 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk
5643 #define CAN_TSR_ABRQ2_Pos (23U)
5644 #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)
5645 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk
5646 #define CAN_TSR_CODE_Pos (24U)
5647 #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)
5648 #define CAN_TSR_CODE CAN_TSR_CODE_Msk
5650 #define CAN_TSR_TME_Pos (26U)
5651 #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)
5652 #define CAN_TSR_TME CAN_TSR_TME_Msk
5653 #define CAN_TSR_TME0_Pos (26U)
5654 #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)
5655 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk
5656 #define CAN_TSR_TME1_Pos (27U)
5657 #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)
5658 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk
5659 #define CAN_TSR_TME2_Pos (28U)
5660 #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)
5661 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk
5663 #define CAN_TSR_LOW_Pos (29U)
5664 #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)
5665 #define CAN_TSR_LOW CAN_TSR_LOW_Msk
5666 #define CAN_TSR_LOW0_Pos (29U)
5667 #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)
5668 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk
5669 #define CAN_TSR_LOW1_Pos (30U)
5670 #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)
5671 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk
5672 #define CAN_TSR_LOW2_Pos (31U)
5673 #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)
5674 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk
5676 /******************* Bit definition for CAN_RF0R register *******************/
5677 #define CAN_RF0R_FMP0_Pos (0U)
5678 #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)
5679 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk
5680 #define CAN_RF0R_FULL0_Pos (3U)
5681 #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)
5682 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk
5683 #define CAN_RF0R_FOVR0_Pos (4U)
5684 #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)
5685 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk
5686 #define CAN_RF0R_RFOM0_Pos (5U)
5687 #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)
5688 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk
5690 /******************* Bit definition for CAN_RF1R register *******************/
5691 #define CAN_RF1R_FMP1_Pos (0U)
5692 #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)
5693 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk
5694 #define CAN_RF1R_FULL1_Pos (3U)
5695 #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)
5696 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk
5697 #define CAN_RF1R_FOVR1_Pos (4U)
5698 #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)
5699 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk
5700 #define CAN_RF1R_RFOM1_Pos (5U)
5701 #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)
5702 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk
5704 /******************** Bit definition for CAN_IER register *******************/
5705 #define CAN_IER_TMEIE_Pos (0U)
5706 #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)
5707 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk
5708 #define CAN_IER_FMPIE0_Pos (1U)
5709 #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)
5710 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk
5711 #define CAN_IER_FFIE0_Pos (2U)
5712 #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)
5713 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk
5714 #define CAN_IER_FOVIE0_Pos (3U)
5715 #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)
5716 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk
5717 #define CAN_IER_FMPIE1_Pos (4U)
5718 #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)
5719 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk
5720 #define CAN_IER_FFIE1_Pos (5U)
5721 #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)
5722 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk
5723 #define CAN_IER_FOVIE1_Pos (6U)
5724 #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)
5725 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk
5726 #define CAN_IER_EWGIE_Pos (8U)
5727 #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)
5728 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk
5729 #define CAN_IER_EPVIE_Pos (9U)
5730 #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)
5731 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk
5732 #define CAN_IER_BOFIE_Pos (10U)
5733 #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)
5734 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk
5735 #define CAN_IER_LECIE_Pos (11U)
5736 #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)
5737 #define CAN_IER_LECIE CAN_IER_LECIE_Msk
5738 #define CAN_IER_ERRIE_Pos (15U)
5739 #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)
5740 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk
5741 #define CAN_IER_WKUIE_Pos (16U)
5742 #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)
5743 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk
5744 #define CAN_IER_SLKIE_Pos (17U)
5745 #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)
5746 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk
5748 /******************** Bit definition for CAN_ESR register *******************/
5749 #define CAN_ESR_EWGF_Pos (0U)
5750 #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)
5751 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk
5752 #define CAN_ESR_EPVF_Pos (1U)
5753 #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)
5754 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk
5755 #define CAN_ESR_BOFF_Pos (2U)
5756 #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)
5757 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk
5759 #define CAN_ESR_LEC_Pos (4U)
5760 #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)
5761 #define CAN_ESR_LEC CAN_ESR_LEC_Msk
5762 #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)
5763 #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)
5764 #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)
5766 #define CAN_ESR_TEC_Pos (16U)
5767 #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)
5768 #define CAN_ESR_TEC CAN_ESR_TEC_Msk
5769 #define CAN_ESR_REC_Pos (24U)
5770 #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)
5771 #define CAN_ESR_REC CAN_ESR_REC_Msk
5773 /******************* Bit definition for CAN_BTR register ********************/
5774 #define CAN_BTR_BRP_Pos (0U)
5775 #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)
5776 #define CAN_BTR_BRP CAN_BTR_BRP_Msk
5777 #define CAN_BTR_TS1_Pos (16U)
5778 #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)
5779 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk
5780 #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)
5781 #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)
5782 #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)
5783 #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)
5784 #define CAN_BTR_TS2_Pos (20U)
5785 #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)
5786 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk
5787 #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)
5788 #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)
5789 #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)
5790 #define CAN_BTR_SJW_Pos (24U)
5791 #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)
5792 #define CAN_BTR_SJW CAN_BTR_SJW_Msk
5793 #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)
5794 #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)
5795 #define CAN_BTR_LBKM_Pos (30U)
5796 #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)
5797 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk
5798 #define CAN_BTR_SILM_Pos (31U)
5799 #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)
5800 #define CAN_BTR_SILM CAN_BTR_SILM_Msk
5803 /****************** Bit definition for CAN_TI0R register ********************/
5804 #define CAN_TI0R_TXRQ_Pos (0U)
5805 #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)
5806 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk
5807 #define CAN_TI0R_RTR_Pos (1U)
5808 #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)
5809 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk
5810 #define CAN_TI0R_IDE_Pos (2U)
5811 #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)
5812 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk
5813 #define CAN_TI0R_EXID_Pos (3U)
5814 #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)
5815 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk
5816 #define CAN_TI0R_STID_Pos (21U)
5817 #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)
5818 #define CAN_TI0R_STID CAN_TI0R_STID_Msk
5820 /****************** Bit definition for CAN_TDT0R register *******************/
5821 #define CAN_TDT0R_DLC_Pos (0U)
5822 #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)
5823 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk
5824 #define CAN_TDT0R_TGT_Pos (8U)
5825 #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)
5826 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk
5827 #define CAN_TDT0R_TIME_Pos (16U)
5828 #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)
5829 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk
5831 /****************** Bit definition for CAN_TDL0R register *******************/
5832 #define CAN_TDL0R_DATA0_Pos (0U)
5833 #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)
5834 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk
5835 #define CAN_TDL0R_DATA1_Pos (8U)
5836 #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)
5837 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk
5838 #define CAN_TDL0R_DATA2_Pos (16U)
5839 #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)
5840 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk
5841 #define CAN_TDL0R_DATA3_Pos (24U)
5842 #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)
5843 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk
5845 /****************** Bit definition for CAN_TDH0R register *******************/
5846 #define CAN_TDH0R_DATA4_Pos (0U)
5847 #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)
5848 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk
5849 #define CAN_TDH0R_DATA5_Pos (8U)
5850 #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)
5851 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk
5852 #define CAN_TDH0R_DATA6_Pos (16U)
5853 #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)
5854 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk
5855 #define CAN_TDH0R_DATA7_Pos (24U)
5856 #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)
5857 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk
5859 /******************* Bit definition for CAN_TI1R register *******************/
5860 #define CAN_TI1R_TXRQ_Pos (0U)
5861 #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)
5862 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk
5863 #define CAN_TI1R_RTR_Pos (1U)
5864 #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)
5865 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk
5866 #define CAN_TI1R_IDE_Pos (2U)
5867 #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)
5868 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk
5869 #define CAN_TI1R_EXID_Pos (3U)
5870 #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)
5871 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk
5872 #define CAN_TI1R_STID_Pos (21U)
5873 #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)
5874 #define CAN_TI1R_STID CAN_TI1R_STID_Msk
5876 /******************* Bit definition for CAN_TDT1R register ******************/
5877 #define CAN_TDT1R_DLC_Pos (0U)
5878 #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)
5879 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk
5880 #define CAN_TDT1R_TGT_Pos (8U)
5881 #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)
5882 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk
5883 #define CAN_TDT1R_TIME_Pos (16U)
5884 #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)
5885 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk
5887 /******************* Bit definition for CAN_TDL1R register ******************/
5888 #define CAN_TDL1R_DATA0_Pos (0U)
5889 #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)
5890 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk
5891 #define CAN_TDL1R_DATA1_Pos (8U)
5892 #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)
5893 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk
5894 #define CAN_TDL1R_DATA2_Pos (16U)
5895 #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)
5896 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk
5897 #define CAN_TDL1R_DATA3_Pos (24U)
5898 #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)
5899 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk
5901 /******************* Bit definition for CAN_TDH1R register ******************/
5902 #define CAN_TDH1R_DATA4_Pos (0U)
5903 #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)
5904 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk
5905 #define CAN_TDH1R_DATA5_Pos (8U)
5906 #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)
5907 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk
5908 #define CAN_TDH1R_DATA6_Pos (16U)
5909 #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)
5910 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk
5911 #define CAN_TDH1R_DATA7_Pos (24U)
5912 #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)
5913 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk
5915 /******************* Bit definition for CAN_TI2R register *******************/
5916 #define CAN_TI2R_TXRQ_Pos (0U)
5917 #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)
5918 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk
5919 #define CAN_TI2R_RTR_Pos (1U)
5920 #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)
5921 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk
5922 #define CAN_TI2R_IDE_Pos (2U)
5923 #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)
5924 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk
5925 #define CAN_TI2R_EXID_Pos (3U)
5926 #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)
5927 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk
5928 #define CAN_TI2R_STID_Pos (21U)
5929 #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)
5930 #define CAN_TI2R_STID CAN_TI2R_STID_Msk
5932 /******************* Bit definition for CAN_TDT2R register ******************/
5933 #define CAN_TDT2R_DLC_Pos (0U)
5934 #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)
5935 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk
5936 #define CAN_TDT2R_TGT_Pos (8U)
5937 #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)
5938 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk
5939 #define CAN_TDT2R_TIME_Pos (16U)
5940 #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)
5941 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk
5943 /******************* Bit definition for CAN_TDL2R register ******************/
5944 #define CAN_TDL2R_DATA0_Pos (0U)
5945 #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)
5946 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk
5947 #define CAN_TDL2R_DATA1_Pos (8U)
5948 #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)
5949 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk
5950 #define CAN_TDL2R_DATA2_Pos (16U)
5951 #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)
5952 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk
5953 #define CAN_TDL2R_DATA3_Pos (24U)
5954 #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)
5955 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk
5957 /******************* Bit definition for CAN_TDH2R register ******************/
5958 #define CAN_TDH2R_DATA4_Pos (0U)
5959 #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)
5960 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk
5961 #define CAN_TDH2R_DATA5_Pos (8U)
5962 #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)
5963 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk
5964 #define CAN_TDH2R_DATA6_Pos (16U)
5965 #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)
5966 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk
5967 #define CAN_TDH2R_DATA7_Pos (24U)
5968 #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)
5969 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk
5971 /******************* Bit definition for CAN_RI0R register *******************/
5972 #define CAN_RI0R_RTR_Pos (1U)
5973 #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)
5974 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk
5975 #define CAN_RI0R_IDE_Pos (2U)
5976 #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)
5977 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk
5978 #define CAN_RI0R_EXID_Pos (3U)
5979 #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)
5980 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk
5981 #define CAN_RI0R_STID_Pos (21U)
5982 #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)
5983 #define CAN_RI0R_STID CAN_RI0R_STID_Msk
5985 /******************* Bit definition for CAN_RDT0R register ******************/
5986 #define CAN_RDT0R_DLC_Pos (0U)
5987 #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)
5988 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk
5989 #define CAN_RDT0R_FMI_Pos (8U)
5990 #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)
5991 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk
5992 #define CAN_RDT0R_TIME_Pos (16U)
5993 #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)
5994 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk
5996 /******************* Bit definition for CAN_RDL0R register ******************/
5997 #define CAN_RDL0R_DATA0_Pos (0U)
5998 #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)
5999 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk
6000 #define CAN_RDL0R_DATA1_Pos (8U)
6001 #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)
6002 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk
6003 #define CAN_RDL0R_DATA2_Pos (16U)
6004 #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)
6005 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk
6006 #define CAN_RDL0R_DATA3_Pos (24U)
6007 #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)
6008 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk
6010 /******************* Bit definition for CAN_RDH0R register ******************/
6011 #define CAN_RDH0R_DATA4_Pos (0U)
6012 #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)
6013 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk
6014 #define CAN_RDH0R_DATA5_Pos (8U)
6015 #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)
6016 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk
6017 #define CAN_RDH0R_DATA6_Pos (16U)
6018 #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)
6019 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk
6020 #define CAN_RDH0R_DATA7_Pos (24U)
6021 #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)
6022 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk
6024 /******************* Bit definition for CAN_RI1R register *******************/
6025 #define CAN_RI1R_RTR_Pos (1U)
6026 #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)
6027 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk
6028 #define CAN_RI1R_IDE_Pos (2U)
6029 #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)
6030 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk
6031 #define CAN_RI1R_EXID_Pos (3U)
6032 #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)
6033 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk
6034 #define CAN_RI1R_STID_Pos (21U)
6035 #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)
6036 #define CAN_RI1R_STID CAN_RI1R_STID_Msk
6038 /******************* Bit definition for CAN_RDT1R register ******************/
6039 #define CAN_RDT1R_DLC_Pos (0U)
6040 #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)
6041 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk
6042 #define CAN_RDT1R_FMI_Pos (8U)
6043 #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)
6044 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk
6045 #define CAN_RDT1R_TIME_Pos (16U)
6046 #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)
6047 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk
6049 /******************* Bit definition for CAN_RDL1R register ******************/
6050 #define CAN_RDL1R_DATA0_Pos (0U)
6051 #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)
6052 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk
6053 #define CAN_RDL1R_DATA1_Pos (8U)
6054 #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)
6055 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk
6056 #define CAN_RDL1R_DATA2_Pos (16U)
6057 #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)
6058 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk
6059 #define CAN_RDL1R_DATA3_Pos (24U)
6060 #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)
6061 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk
6063 /******************* Bit definition for CAN_RDH1R register ******************/
6064 #define CAN_RDH1R_DATA4_Pos (0U)
6065 #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)
6066 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk
6067 #define CAN_RDH1R_DATA5_Pos (8U)
6068 #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)
6069 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk
6070 #define CAN_RDH1R_DATA6_Pos (16U)
6071 #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)
6072 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk
6073 #define CAN_RDH1R_DATA7_Pos (24U)
6074 #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)
6075 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk
6078 /******************* Bit definition for CAN_FMR register ********************/
6079 #define CAN_FMR_FINIT_Pos (0U)
6080 #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)
6081 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk
6082 #define CAN_FMR_CAN2SB_Pos (8U)
6083 #define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)
6084 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk
6086 /******************* Bit definition for CAN_FM1R register *******************/
6087 #define CAN_FM1R_FBM_Pos (0U)
6088 #define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos)
6089 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk
6090 #define CAN_FM1R_FBM0_Pos (0U)
6091 #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)
6092 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk
6093 #define CAN_FM1R_FBM1_Pos (1U)
6094 #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)
6095 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk
6096 #define CAN_FM1R_FBM2_Pos (2U)
6097 #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)
6098 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk
6099 #define CAN_FM1R_FBM3_Pos (3U)
6100 #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)
6101 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk
6102 #define CAN_FM1R_FBM4_Pos (4U)
6103 #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)
6104 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk
6105 #define CAN_FM1R_FBM5_Pos (5U)
6106 #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)
6107 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk
6108 #define CAN_FM1R_FBM6_Pos (6U)
6109 #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)
6110 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk
6111 #define CAN_FM1R_FBM7_Pos (7U)
6112 #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)
6113 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk
6114 #define CAN_FM1R_FBM8_Pos (8U)
6115 #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)
6116 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk
6117 #define CAN_FM1R_FBM9_Pos (9U)
6118 #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)
6119 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk
6120 #define CAN_FM1R_FBM10_Pos (10U)
6121 #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)
6122 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk
6123 #define CAN_FM1R_FBM11_Pos (11U)
6124 #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)
6125 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk
6126 #define CAN_FM1R_FBM12_Pos (12U)
6127 #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)
6128 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk
6129 #define CAN_FM1R_FBM13_Pos (13U)
6130 #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)
6131 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk
6133 /******************* Bit definition for CAN_FS1R register *******************/
6134 #define CAN_FS1R_FSC_Pos (0U)
6135 #define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos)
6136 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk
6137 #define CAN_FS1R_FSC0_Pos (0U)
6138 #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)
6139 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk
6140 #define CAN_FS1R_FSC1_Pos (1U)
6141 #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)
6142 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk
6143 #define CAN_FS1R_FSC2_Pos (2U)
6144 #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)
6145 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk
6146 #define CAN_FS1R_FSC3_Pos (3U)
6147 #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)
6148 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk
6149 #define CAN_FS1R_FSC4_Pos (4U)
6150 #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)
6151 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk
6152 #define CAN_FS1R_FSC5_Pos (5U)
6153 #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)
6154 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk
6155 #define CAN_FS1R_FSC6_Pos (6U)
6156 #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)
6157 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk
6158 #define CAN_FS1R_FSC7_Pos (7U)
6159 #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)
6160 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk
6161 #define CAN_FS1R_FSC8_Pos (8U)
6162 #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)
6163 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk
6164 #define CAN_FS1R_FSC9_Pos (9U)
6165 #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)
6166 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk
6167 #define CAN_FS1R_FSC10_Pos (10U)
6168 #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)
6169 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk
6170 #define CAN_FS1R_FSC11_Pos (11U)
6171 #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)
6172 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk
6173 #define CAN_FS1R_FSC12_Pos (12U)
6174 #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)
6175 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk
6176 #define CAN_FS1R_FSC13_Pos (13U)
6177 #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)
6178 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk
6180 /****************** Bit definition for CAN_FFA1R register *******************/
6181 #define CAN_FFA1R_FFA_Pos (0U)
6182 #define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos)
6183 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk
6184 #define CAN_FFA1R_FFA0_Pos (0U)
6185 #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)
6186 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk
6187 #define CAN_FFA1R_FFA1_Pos (1U)
6188 #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)
6189 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk
6190 #define CAN_FFA1R_FFA2_Pos (2U)
6191 #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)
6192 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk
6193 #define CAN_FFA1R_FFA3_Pos (3U)
6194 #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)
6195 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk
6196 #define CAN_FFA1R_FFA4_Pos (4U)
6197 #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)
6198 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk
6199 #define CAN_FFA1R_FFA5_Pos (5U)
6200 #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)
6201 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk
6202 #define CAN_FFA1R_FFA6_Pos (6U)
6203 #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)
6204 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk
6205 #define CAN_FFA1R_FFA7_Pos (7U)
6206 #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)
6207 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk
6208 #define CAN_FFA1R_FFA8_Pos (8U)
6209 #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)
6210 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk
6211 #define CAN_FFA1R_FFA9_Pos (9U)
6212 #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)
6213 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk
6214 #define CAN_FFA1R_FFA10_Pos (10U)
6215 #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)
6216 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk
6217 #define CAN_FFA1R_FFA11_Pos (11U)
6218 #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)
6219 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk
6220 #define CAN_FFA1R_FFA12_Pos (12U)
6221 #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)
6222 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk
6223 #define CAN_FFA1R_FFA13_Pos (13U)
6224 #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)
6225 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk
6227 /******************* Bit definition for CAN_FA1R register *******************/
6228 #define CAN_FA1R_FACT_Pos (0U)
6229 #define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos)
6230 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk
6231 #define CAN_FA1R_FACT0_Pos (0U)
6232 #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)
6233 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk
6234 #define CAN_FA1R_FACT1_Pos (1U)
6235 #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)
6236 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk
6237 #define CAN_FA1R_FACT2_Pos (2U)
6238 #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)
6239 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk
6240 #define CAN_FA1R_FACT3_Pos (3U)
6241 #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)
6242 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk
6243 #define CAN_FA1R_FACT4_Pos (4U)
6244 #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)
6245 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk
6246 #define CAN_FA1R_FACT5_Pos (5U)
6247 #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)
6248 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk
6249 #define CAN_FA1R_FACT6_Pos (6U)
6250 #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)
6251 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk
6252 #define CAN_FA1R_FACT7_Pos (7U)
6253 #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)
6254 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk
6255 #define CAN_FA1R_FACT8_Pos (8U)
6256 #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)
6257 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk
6258 #define CAN_FA1R_FACT9_Pos (9U)
6259 #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)
6260 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk
6261 #define CAN_FA1R_FACT10_Pos (10U)
6262 #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)
6263 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk
6264 #define CAN_FA1R_FACT11_Pos (11U)
6265 #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)
6266 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk
6267 #define CAN_FA1R_FACT12_Pos (12U)
6268 #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)
6269 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk
6270 #define CAN_FA1R_FACT13_Pos (13U)
6271 #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)
6272 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk
6274 /******************* Bit definition for CAN_F0R1 register *******************/
6275 #define CAN_F0R1_FB0_Pos (0U)
6276 #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)
6277 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk
6278 #define CAN_F0R1_FB1_Pos (1U)
6279 #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)
6280 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk
6281 #define CAN_F0R1_FB2_Pos (2U)
6282 #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)
6283 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk
6284 #define CAN_F0R1_FB3_Pos (3U)
6285 #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)
6286 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk
6287 #define CAN_F0R1_FB4_Pos (4U)
6288 #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)
6289 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk
6290 #define CAN_F0R1_FB5_Pos (5U)
6291 #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)
6292 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk
6293 #define CAN_F0R1_FB6_Pos (6U)
6294 #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)
6295 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk
6296 #define CAN_F0R1_FB7_Pos (7U)
6297 #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)
6298 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk
6299 #define CAN_F0R1_FB8_Pos (8U)
6300 #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)
6301 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk
6302 #define CAN_F0R1_FB9_Pos (9U)
6303 #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)
6304 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk
6305 #define CAN_F0R1_FB10_Pos (10U)
6306 #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)
6307 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk
6308 #define CAN_F0R1_FB11_Pos (11U)
6309 #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)
6310 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk
6311 #define CAN_F0R1_FB12_Pos (12U)
6312 #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)
6313 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk
6314 #define CAN_F0R1_FB13_Pos (13U)
6315 #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)
6316 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk
6317 #define CAN_F0R1_FB14_Pos (14U)
6318 #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)
6319 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk
6320 #define CAN_F0R1_FB15_Pos (15U)
6321 #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)
6322 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk
6323 #define CAN_F0R1_FB16_Pos (16U)
6324 #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)
6325 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk
6326 #define CAN_F0R1_FB17_Pos (17U)
6327 #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)
6328 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk
6329 #define CAN_F0R1_FB18_Pos (18U)
6330 #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)
6331 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk
6332 #define CAN_F0R1_FB19_Pos (19U)
6333 #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)
6334 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk
6335 #define CAN_F0R1_FB20_Pos (20U)
6336 #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)
6337 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk
6338 #define CAN_F0R1_FB21_Pos (21U)
6339 #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)
6340 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk
6341 #define CAN_F0R1_FB22_Pos (22U)
6342 #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)
6343 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk
6344 #define CAN_F0R1_FB23_Pos (23U)
6345 #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)
6346 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk
6347 #define CAN_F0R1_FB24_Pos (24U)
6348 #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)
6349 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk
6350 #define CAN_F0R1_FB25_Pos (25U)
6351 #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)
6352 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk
6353 #define CAN_F0R1_FB26_Pos (26U)
6354 #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)
6355 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk
6356 #define CAN_F0R1_FB27_Pos (27U)
6357 #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)
6358 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk
6359 #define CAN_F0R1_FB28_Pos (28U)
6360 #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)
6361 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk
6362 #define CAN_F0R1_FB29_Pos (29U)
6363 #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)
6364 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk
6365 #define CAN_F0R1_FB30_Pos (30U)
6366 #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)
6367 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk
6368 #define CAN_F0R1_FB31_Pos (31U)
6369 #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)
6370 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk
6372 /******************* Bit definition for CAN_F1R1 register *******************/
6373 #define CAN_F1R1_FB0_Pos (0U)
6374 #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)
6375 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk
6376 #define CAN_F1R1_FB1_Pos (1U)
6377 #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)
6378 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk
6379 #define CAN_F1R1_FB2_Pos (2U)
6380 #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)
6381 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk
6382 #define CAN_F1R1_FB3_Pos (3U)
6383 #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)
6384 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk
6385 #define CAN_F1R1_FB4_Pos (4U)
6386 #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)
6387 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk
6388 #define CAN_F1R1_FB5_Pos (5U)
6389 #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)
6390 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk
6391 #define CAN_F1R1_FB6_Pos (6U)
6392 #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)
6393 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk
6394 #define CAN_F1R1_FB7_Pos (7U)
6395 #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)
6396 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk
6397 #define CAN_F1R1_FB8_Pos (8U)
6398 #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)
6399 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk
6400 #define CAN_F1R1_FB9_Pos (9U)
6401 #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)
6402 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk
6403 #define CAN_F1R1_FB10_Pos (10U)
6404 #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)
6405 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk
6406 #define CAN_F1R1_FB11_Pos (11U)
6407 #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)
6408 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk
6409 #define CAN_F1R1_FB12_Pos (12U)
6410 #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)
6411 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk
6412 #define CAN_F1R1_FB13_Pos (13U)
6413 #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)
6414 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk
6415 #define CAN_F1R1_FB14_Pos (14U)
6416 #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)
6417 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk
6418 #define CAN_F1R1_FB15_Pos (15U)
6419 #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)
6420 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk
6421 #define CAN_F1R1_FB16_Pos (16U)
6422 #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)
6423 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk
6424 #define CAN_F1R1_FB17_Pos (17U)
6425 #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)
6426 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk
6427 #define CAN_F1R1_FB18_Pos (18U)
6428 #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)
6429 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk
6430 #define CAN_F1R1_FB19_Pos (19U)
6431 #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)
6432 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk
6433 #define CAN_F1R1_FB20_Pos (20U)
6434 #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)
6435 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk
6436 #define CAN_F1R1_FB21_Pos (21U)
6437 #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)
6438 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk
6439 #define CAN_F1R1_FB22_Pos (22U)
6440 #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)
6441 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk
6442 #define CAN_F1R1_FB23_Pos (23U)
6443 #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)
6444 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk
6445 #define CAN_F1R1_FB24_Pos (24U)
6446 #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)
6447 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk
6448 #define CAN_F1R1_FB25_Pos (25U)
6449 #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)
6450 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk
6451 #define CAN_F1R1_FB26_Pos (26U)
6452 #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)
6453 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk
6454 #define CAN_F1R1_FB27_Pos (27U)
6455 #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)
6456 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk
6457 #define CAN_F1R1_FB28_Pos (28U)
6458 #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)
6459 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk
6460 #define CAN_F1R1_FB29_Pos (29U)
6461 #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)
6462 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk
6463 #define CAN_F1R1_FB30_Pos (30U)
6464 #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)
6465 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk
6466 #define CAN_F1R1_FB31_Pos (31U)
6467 #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)
6468 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk
6470 /******************* Bit definition for CAN_F2R1 register *******************/
6471 #define CAN_F2R1_FB0_Pos (0U)
6472 #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)
6473 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk
6474 #define CAN_F2R1_FB1_Pos (1U)
6475 #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)
6476 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk
6477 #define CAN_F2R1_FB2_Pos (2U)
6478 #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)
6479 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk
6480 #define CAN_F2R1_FB3_Pos (3U)
6481 #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)
6482 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk
6483 #define CAN_F2R1_FB4_Pos (4U)
6484 #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)
6485 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk
6486 #define CAN_F2R1_FB5_Pos (5U)
6487 #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)
6488 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk
6489 #define CAN_F2R1_FB6_Pos (6U)
6490 #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)
6491 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk
6492 #define CAN_F2R1_FB7_Pos (7U)
6493 #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)
6494 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk
6495 #define CAN_F2R1_FB8_Pos (8U)
6496 #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)
6497 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk
6498 #define CAN_F2R1_FB9_Pos (9U)
6499 #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)
6500 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk
6501 #define CAN_F2R1_FB10_Pos (10U)
6502 #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)
6503 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk
6504 #define CAN_F2R1_FB11_Pos (11U)
6505 #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)
6506 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk
6507 #define CAN_F2R1_FB12_Pos (12U)
6508 #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)
6509 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk
6510 #define CAN_F2R1_FB13_Pos (13U)
6511 #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)
6512 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk
6513 #define CAN_F2R1_FB14_Pos (14U)
6514 #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)
6515 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk
6516 #define CAN_F2R1_FB15_Pos (15U)
6517 #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)
6518 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk
6519 #define CAN_F2R1_FB16_Pos (16U)
6520 #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)
6521 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk
6522 #define CAN_F2R1_FB17_Pos (17U)
6523 #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)
6524 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk
6525 #define CAN_F2R1_FB18_Pos (18U)
6526 #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)
6527 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk
6528 #define CAN_F2R1_FB19_Pos (19U)
6529 #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)
6530 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk
6531 #define CAN_F2R1_FB20_Pos (20U)
6532 #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)
6533 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk
6534 #define CAN_F2R1_FB21_Pos (21U)
6535 #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)
6536 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk
6537 #define CAN_F2R1_FB22_Pos (22U)
6538 #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)
6539 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk
6540 #define CAN_F2R1_FB23_Pos (23U)
6541 #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)
6542 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk
6543 #define CAN_F2R1_FB24_Pos (24U)
6544 #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)
6545 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk
6546 #define CAN_F2R1_FB25_Pos (25U)
6547 #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)
6548 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk
6549 #define CAN_F2R1_FB26_Pos (26U)
6550 #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)
6551 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk
6552 #define CAN_F2R1_FB27_Pos (27U)
6553 #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)
6554 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk
6555 #define CAN_F2R1_FB28_Pos (28U)
6556 #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)
6557 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk
6558 #define CAN_F2R1_FB29_Pos (29U)
6559 #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)
6560 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk
6561 #define CAN_F2R1_FB30_Pos (30U)
6562 #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)
6563 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk
6564 #define CAN_F2R1_FB31_Pos (31U)
6565 #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)
6566 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk
6568 /******************* Bit definition for CAN_F3R1 register *******************/
6569 #define CAN_F3R1_FB0_Pos (0U)
6570 #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)
6571 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk
6572 #define CAN_F3R1_FB1_Pos (1U)
6573 #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)
6574 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk
6575 #define CAN_F3R1_FB2_Pos (2U)
6576 #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)
6577 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk
6578 #define CAN_F3R1_FB3_Pos (3U)
6579 #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)
6580 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk
6581 #define CAN_F3R1_FB4_Pos (4U)
6582 #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)
6583 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk
6584 #define CAN_F3R1_FB5_Pos (5U)
6585 #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)
6586 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk
6587 #define CAN_F3R1_FB6_Pos (6U)
6588 #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)
6589 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk
6590 #define CAN_F3R1_FB7_Pos (7U)
6591 #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)
6592 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk
6593 #define CAN_F3R1_FB8_Pos (8U)
6594 #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)
6595 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk
6596 #define CAN_F3R1_FB9_Pos (9U)
6597 #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)
6598 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk
6599 #define CAN_F3R1_FB10_Pos (10U)
6600 #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)
6601 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk
6602 #define CAN_F3R1_FB11_Pos (11U)
6603 #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)
6604 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk
6605 #define CAN_F3R1_FB12_Pos (12U)
6606 #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)
6607 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk
6608 #define CAN_F3R1_FB13_Pos (13U)
6609 #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)
6610 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk
6611 #define CAN_F3R1_FB14_Pos (14U)
6612 #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)
6613 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk
6614 #define CAN_F3R1_FB15_Pos (15U)
6615 #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)
6616 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk
6617 #define CAN_F3R1_FB16_Pos (16U)
6618 #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)
6619 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk
6620 #define CAN_F3R1_FB17_Pos (17U)
6621 #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)
6622 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk
6623 #define CAN_F3R1_FB18_Pos (18U)
6624 #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)
6625 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk
6626 #define CAN_F3R1_FB19_Pos (19U)
6627 #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)
6628 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk
6629 #define CAN_F3R1_FB20_Pos (20U)
6630 #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)
6631 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk
6632 #define CAN_F3R1_FB21_Pos (21U)
6633 #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)
6634 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk
6635 #define CAN_F3R1_FB22_Pos (22U)
6636 #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)
6637 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk
6638 #define CAN_F3R1_FB23_Pos (23U)
6639 #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)
6640 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk
6641 #define CAN_F3R1_FB24_Pos (24U)
6642 #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)
6643 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk
6644 #define CAN_F3R1_FB25_Pos (25U)
6645 #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)
6646 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk
6647 #define CAN_F3R1_FB26_Pos (26U)
6648 #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)
6649 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk
6650 #define CAN_F3R1_FB27_Pos (27U)
6651 #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)
6652 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk
6653 #define CAN_F3R1_FB28_Pos (28U)
6654 #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)
6655 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk
6656 #define CAN_F3R1_FB29_Pos (29U)
6657 #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)
6658 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk
6659 #define CAN_F3R1_FB30_Pos (30U)
6660 #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)
6661 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk
6662 #define CAN_F3R1_FB31_Pos (31U)
6663 #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)
6664 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk
6666 /******************* Bit definition for CAN_F4R1 register *******************/
6667 #define CAN_F4R1_FB0_Pos (0U)
6668 #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)
6669 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk
6670 #define CAN_F4R1_FB1_Pos (1U)
6671 #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)
6672 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk
6673 #define CAN_F4R1_FB2_Pos (2U)
6674 #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)
6675 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk
6676 #define CAN_F4R1_FB3_Pos (3U)
6677 #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)
6678 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk
6679 #define CAN_F4R1_FB4_Pos (4U)
6680 #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)
6681 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk
6682 #define CAN_F4R1_FB5_Pos (5U)
6683 #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)
6684 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk
6685 #define CAN_F4R1_FB6_Pos (6U)
6686 #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)
6687 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk
6688 #define CAN_F4R1_FB7_Pos (7U)
6689 #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)
6690 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk
6691 #define CAN_F4R1_FB8_Pos (8U)
6692 #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)
6693 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk
6694 #define CAN_F4R1_FB9_Pos (9U)
6695 #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)
6696 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk
6697 #define CAN_F4R1_FB10_Pos (10U)
6698 #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)
6699 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk
6700 #define CAN_F4R1_FB11_Pos (11U)
6701 #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)
6702 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk
6703 #define CAN_F4R1_FB12_Pos (12U)
6704 #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)
6705 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk
6706 #define CAN_F4R1_FB13_Pos (13U)
6707 #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)
6708 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk
6709 #define CAN_F4R1_FB14_Pos (14U)
6710 #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)
6711 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk
6712 #define CAN_F4R1_FB15_Pos (15U)
6713 #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)
6714 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk
6715 #define CAN_F4R1_FB16_Pos (16U)
6716 #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)
6717 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk
6718 #define CAN_F4R1_FB17_Pos (17U)
6719 #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)
6720 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk
6721 #define CAN_F4R1_FB18_Pos (18U)
6722 #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)
6723 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk
6724 #define CAN_F4R1_FB19_Pos (19U)
6725 #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)
6726 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk
6727 #define CAN_F4R1_FB20_Pos (20U)
6728 #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)
6729 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk
6730 #define CAN_F4R1_FB21_Pos (21U)
6731 #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)
6732 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk
6733 #define CAN_F4R1_FB22_Pos (22U)
6734 #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)
6735 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk
6736 #define CAN_F4R1_FB23_Pos (23U)
6737 #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)
6738 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk
6739 #define CAN_F4R1_FB24_Pos (24U)
6740 #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)
6741 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk
6742 #define CAN_F4R1_FB25_Pos (25U)
6743 #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)
6744 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk
6745 #define CAN_F4R1_FB26_Pos (26U)
6746 #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)
6747 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk
6748 #define CAN_F4R1_FB27_Pos (27U)
6749 #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)
6750 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk
6751 #define CAN_F4R1_FB28_Pos (28U)
6752 #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)
6753 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk
6754 #define CAN_F4R1_FB29_Pos (29U)
6755 #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)
6756 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk
6757 #define CAN_F4R1_FB30_Pos (30U)
6758 #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)
6759 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk
6760 #define CAN_F4R1_FB31_Pos (31U)
6761 #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)
6762 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk
6764 /******************* Bit definition for CAN_F5R1 register *******************/
6765 #define CAN_F5R1_FB0_Pos (0U)
6766 #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)
6767 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk
6768 #define CAN_F5R1_FB1_Pos (1U)
6769 #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)
6770 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk
6771 #define CAN_F5R1_FB2_Pos (2U)
6772 #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)
6773 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk
6774 #define CAN_F5R1_FB3_Pos (3U)
6775 #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)
6776 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk
6777 #define CAN_F5R1_FB4_Pos (4U)
6778 #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)
6779 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk
6780 #define CAN_F5R1_FB5_Pos (5U)
6781 #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)
6782 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk
6783 #define CAN_F5R1_FB6_Pos (6U)
6784 #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)
6785 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk
6786 #define CAN_F5R1_FB7_Pos (7U)
6787 #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)
6788 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk
6789 #define CAN_F5R1_FB8_Pos (8U)
6790 #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)
6791 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk
6792 #define CAN_F5R1_FB9_Pos (9U)
6793 #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)
6794 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk
6795 #define CAN_F5R1_FB10_Pos (10U)
6796 #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)
6797 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk
6798 #define CAN_F5R1_FB11_Pos (11U)
6799 #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)
6800 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk
6801 #define CAN_F5R1_FB12_Pos (12U)
6802 #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)
6803 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk
6804 #define CAN_F5R1_FB13_Pos (13U)
6805 #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)
6806 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk
6807 #define CAN_F5R1_FB14_Pos (14U)
6808 #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)
6809 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk
6810 #define CAN_F5R1_FB15_Pos (15U)
6811 #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)
6812 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk
6813 #define CAN_F5R1_FB16_Pos (16U)
6814 #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)
6815 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk
6816 #define CAN_F5R1_FB17_Pos (17U)
6817 #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)
6818 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk
6819 #define CAN_F5R1_FB18_Pos (18U)
6820 #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)
6821 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk
6822 #define CAN_F5R1_FB19_Pos (19U)
6823 #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)
6824 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk
6825 #define CAN_F5R1_FB20_Pos (20U)
6826 #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)
6827 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk
6828 #define CAN_F5R1_FB21_Pos (21U)
6829 #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)
6830 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk
6831 #define CAN_F5R1_FB22_Pos (22U)
6832 #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)
6833 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk
6834 #define CAN_F5R1_FB23_Pos (23U)
6835 #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)
6836 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk
6837 #define CAN_F5R1_FB24_Pos (24U)
6838 #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)
6839 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk
6840 #define CAN_F5R1_FB25_Pos (25U)
6841 #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)
6842 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk
6843 #define CAN_F5R1_FB26_Pos (26U)
6844 #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)
6845 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk
6846 #define CAN_F5R1_FB27_Pos (27U)
6847 #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)
6848 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk
6849 #define CAN_F5R1_FB28_Pos (28U)
6850 #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)
6851 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk
6852 #define CAN_F5R1_FB29_Pos (29U)
6853 #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)
6854 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk
6855 #define CAN_F5R1_FB30_Pos (30U)
6856 #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)
6857 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk
6858 #define CAN_F5R1_FB31_Pos (31U)
6859 #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)
6860 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk
6862 /******************* Bit definition for CAN_F6R1 register *******************/
6863 #define CAN_F6R1_FB0_Pos (0U)
6864 #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)
6865 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk
6866 #define CAN_F6R1_FB1_Pos (1U)
6867 #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)
6868 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk
6869 #define CAN_F6R1_FB2_Pos (2U)
6870 #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)
6871 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk
6872 #define CAN_F6R1_FB3_Pos (3U)
6873 #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)
6874 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk
6875 #define CAN_F6R1_FB4_Pos (4U)
6876 #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)
6877 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk
6878 #define CAN_F6R1_FB5_Pos (5U)
6879 #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)
6880 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk
6881 #define CAN_F6R1_FB6_Pos (6U)
6882 #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)
6883 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk
6884 #define CAN_F6R1_FB7_Pos (7U)
6885 #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)
6886 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk
6887 #define CAN_F6R1_FB8_Pos (8U)
6888 #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)
6889 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk
6890 #define CAN_F6R1_FB9_Pos (9U)
6891 #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)
6892 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk
6893 #define CAN_F6R1_FB10_Pos (10U)
6894 #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)
6895 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk
6896 #define CAN_F6R1_FB11_Pos (11U)
6897 #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)
6898 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk
6899 #define CAN_F6R1_FB12_Pos (12U)
6900 #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)
6901 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk
6902 #define CAN_F6R1_FB13_Pos (13U)
6903 #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)
6904 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk
6905 #define CAN_F6R1_FB14_Pos (14U)
6906 #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)
6907 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk
6908 #define CAN_F6R1_FB15_Pos (15U)
6909 #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)
6910 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk
6911 #define CAN_F6R1_FB16_Pos (16U)
6912 #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)
6913 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk
6914 #define CAN_F6R1_FB17_Pos (17U)
6915 #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)
6916 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk
6917 #define CAN_F6R1_FB18_Pos (18U)
6918 #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)
6919 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk
6920 #define CAN_F6R1_FB19_Pos (19U)
6921 #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)
6922 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk
6923 #define CAN_F6R1_FB20_Pos (20U)
6924 #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)
6925 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk
6926 #define CAN_F6R1_FB21_Pos (21U)
6927 #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)
6928 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk
6929 #define CAN_F6R1_FB22_Pos (22U)
6930 #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)
6931 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk
6932 #define CAN_F6R1_FB23_Pos (23U)
6933 #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)
6934 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk
6935 #define CAN_F6R1_FB24_Pos (24U)
6936 #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)
6937 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk
6938 #define CAN_F6R1_FB25_Pos (25U)
6939 #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)
6940 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk
6941 #define CAN_F6R1_FB26_Pos (26U)
6942 #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)
6943 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk
6944 #define CAN_F6R1_FB27_Pos (27U)
6945 #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)
6946 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk
6947 #define CAN_F6R1_FB28_Pos (28U)
6948 #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)
6949 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk
6950 #define CAN_F6R1_FB29_Pos (29U)
6951 #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)
6952 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk
6953 #define CAN_F6R1_FB30_Pos (30U)
6954 #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)
6955 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk
6956 #define CAN_F6R1_FB31_Pos (31U)
6957 #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)
6958 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk
6960 /******************* Bit definition for CAN_F7R1 register *******************/
6961 #define CAN_F7R1_FB0_Pos (0U)
6962 #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)
6963 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk
6964 #define CAN_F7R1_FB1_Pos (1U)
6965 #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)
6966 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk
6967 #define CAN_F7R1_FB2_Pos (2U)
6968 #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)
6969 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk
6970 #define CAN_F7R1_FB3_Pos (3U)
6971 #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)
6972 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk
6973 #define CAN_F7R1_FB4_Pos (4U)
6974 #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)
6975 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk
6976 #define CAN_F7R1_FB5_Pos (5U)
6977 #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)
6978 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk
6979 #define CAN_F7R1_FB6_Pos (6U)
6980 #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)
6981 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk
6982 #define CAN_F7R1_FB7_Pos (7U)
6983 #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)
6984 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk
6985 #define CAN_F7R1_FB8_Pos (8U)
6986 #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)
6987 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk
6988 #define CAN_F7R1_FB9_Pos (9U)
6989 #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)
6990 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk
6991 #define CAN_F7R1_FB10_Pos (10U)
6992 #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)
6993 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk
6994 #define CAN_F7R1_FB11_Pos (11U)
6995 #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)
6996 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk
6997 #define CAN_F7R1_FB12_Pos (12U)
6998 #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)
6999 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk
7000 #define CAN_F7R1_FB13_Pos (13U)
7001 #define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)
7002 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk
7003 #define CAN_F7R1_FB14_Pos (14U)
7004 #define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)
7005 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk
7006 #define CAN_F7R1_FB15_Pos (15U)
7007 #define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)
7008 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk
7009 #define CAN_F7R1_FB16_Pos (16U)
7010 #define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)
7011 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk
7012 #define CAN_F7R1_FB17_Pos (17U)
7013 #define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)
7014 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk
7015 #define CAN_F7R1_FB18_Pos (18U)
7016 #define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)
7017 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk
7018 #define CAN_F7R1_FB19_Pos (19U)
7019 #define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)
7020 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk
7021 #define CAN_F7R1_FB20_Pos (20U)
7022 #define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)
7023 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk
7024 #define CAN_F7R1_FB21_Pos (21U)
7025 #define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)
7026 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk
7027 #define CAN_F7R1_FB22_Pos (22U)
7028 #define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)
7029 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk
7030 #define CAN_F7R1_FB23_Pos (23U)
7031 #define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)
7032 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk
7033 #define CAN_F7R1_FB24_Pos (24U)
7034 #define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)
7035 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk
7036 #define CAN_F7R1_FB25_Pos (25U)
7037 #define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)
7038 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk
7039 #define CAN_F7R1_FB26_Pos (26U)
7040 #define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)
7041 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk
7042 #define CAN_F7R1_FB27_Pos (27U)
7043 #define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)
7044 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk
7045 #define CAN_F7R1_FB28_Pos (28U)
7046 #define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)
7047 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk
7048 #define CAN_F7R1_FB29_Pos (29U)
7049 #define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)
7050 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk
7051 #define CAN_F7R1_FB30_Pos (30U)
7052 #define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)
7053 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk
7054 #define CAN_F7R1_FB31_Pos (31U)
7055 #define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)
7056 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk
7058 /******************* Bit definition for CAN_F8R1 register *******************/
7059 #define CAN_F8R1_FB0_Pos (0U)
7060 #define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)
7061 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk
7062 #define CAN_F8R1_FB1_Pos (1U)
7063 #define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)
7064 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk
7065 #define CAN_F8R1_FB2_Pos (2U)
7066 #define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)
7067 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk
7068 #define CAN_F8R1_FB3_Pos (3U)
7069 #define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)
7070 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk
7071 #define CAN_F8R1_FB4_Pos (4U)
7072 #define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)
7073 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk
7074 #define CAN_F8R1_FB5_Pos (5U)
7075 #define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)
7076 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk
7077 #define CAN_F8R1_FB6_Pos (6U)
7078 #define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)
7079 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk
7080 #define CAN_F8R1_FB7_Pos (7U)
7081 #define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)
7082 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk
7083 #define CAN_F8R1_FB8_Pos (8U)
7084 #define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)
7085 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk
7086 #define CAN_F8R1_FB9_Pos (9U)
7087 #define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)
7088 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk
7089 #define CAN_F8R1_FB10_Pos (10U)
7090 #define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)
7091 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk
7092 #define CAN_F8R1_FB11_Pos (11U)
7093 #define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)
7094 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk
7095 #define CAN_F8R1_FB12_Pos (12U)
7096 #define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)
7097 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk
7098 #define CAN_F8R1_FB13_Pos (13U)
7099 #define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)
7100 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk
7101 #define CAN_F8R1_FB14_Pos (14U)
7102 #define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)
7103 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk
7104 #define CAN_F8R1_FB15_Pos (15U)
7105 #define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)
7106 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk
7107 #define CAN_F8R1_FB16_Pos (16U)
7108 #define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)
7109 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk
7110 #define CAN_F8R1_FB17_Pos (17U)
7111 #define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)
7112 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk
7113 #define CAN_F8R1_FB18_Pos (18U)
7114 #define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)
7115 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk
7116 #define CAN_F8R1_FB19_Pos (19U)
7117 #define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)
7118 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk
7119 #define CAN_F8R1_FB20_Pos (20U)
7120 #define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)
7121 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk
7122 #define CAN_F8R1_FB21_Pos (21U)
7123 #define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)
7124 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk
7125 #define CAN_F8R1_FB22_Pos (22U)
7126 #define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)
7127 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk
7128 #define CAN_F8R1_FB23_Pos (23U)
7129 #define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)
7130 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk
7131 #define CAN_F8R1_FB24_Pos (24U)
7132 #define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)
7133 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk
7134 #define CAN_F8R1_FB25_Pos (25U)
7135 #define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)
7136 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk
7137 #define CAN_F8R1_FB26_Pos (26U)
7138 #define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)
7139 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk
7140 #define CAN_F8R1_FB27_Pos (27U)
7141 #define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)
7142 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk
7143 #define CAN_F8R1_FB28_Pos (28U)
7144 #define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)
7145 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk
7146 #define CAN_F8R1_FB29_Pos (29U)
7147 #define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)
7148 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk
7149 #define CAN_F8R1_FB30_Pos (30U)
7150 #define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)
7151 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk
7152 #define CAN_F8R1_FB31_Pos (31U)
7153 #define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)
7154 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk
7156 /******************* Bit definition for CAN_F9R1 register *******************/
7157 #define CAN_F9R1_FB0_Pos (0U)
7158 #define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)
7159 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk
7160 #define CAN_F9R1_FB1_Pos (1U)
7161 #define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)
7162 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk
7163 #define CAN_F9R1_FB2_Pos (2U)
7164 #define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)
7165 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk
7166 #define CAN_F9R1_FB3_Pos (3U)
7167 #define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)
7168 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk
7169 #define CAN_F9R1_FB4_Pos (4U)
7170 #define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)
7171 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk
7172 #define CAN_F9R1_FB5_Pos (5U)
7173 #define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)
7174 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk
7175 #define CAN_F9R1_FB6_Pos (6U)
7176 #define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)
7177 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk
7178 #define CAN_F9R1_FB7_Pos (7U)
7179 #define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)
7180 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk
7181 #define CAN_F9R1_FB8_Pos (8U)
7182 #define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)
7183 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk
7184 #define CAN_F9R1_FB9_Pos (9U)
7185 #define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)
7186 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk
7187 #define CAN_F9R1_FB10_Pos (10U)
7188 #define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)
7189 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk
7190 #define CAN_F9R1_FB11_Pos (11U)
7191 #define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)
7192 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk
7193 #define CAN_F9R1_FB12_Pos (12U)
7194 #define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)
7195 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk
7196 #define CAN_F9R1_FB13_Pos (13U)
7197 #define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)
7198 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk
7199 #define CAN_F9R1_FB14_Pos (14U)
7200 #define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)
7201 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk
7202 #define CAN_F9R1_FB15_Pos (15U)
7203 #define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)
7204 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk
7205 #define CAN_F9R1_FB16_Pos (16U)
7206 #define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)
7207 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk
7208 #define CAN_F9R1_FB17_Pos (17U)
7209 #define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)
7210 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk
7211 #define CAN_F9R1_FB18_Pos (18U)
7212 #define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)
7213 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk
7214 #define CAN_F9R1_FB19_Pos (19U)
7215 #define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)
7216 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk
7217 #define CAN_F9R1_FB20_Pos (20U)
7218 #define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)
7219 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk
7220 #define CAN_F9R1_FB21_Pos (21U)
7221 #define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)
7222 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk
7223 #define CAN_F9R1_FB22_Pos (22U)
7224 #define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)
7225 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk
7226 #define CAN_F9R1_FB23_Pos (23U)
7227 #define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)
7228 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk
7229 #define CAN_F9R1_FB24_Pos (24U)
7230 #define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)
7231 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk
7232 #define CAN_F9R1_FB25_Pos (25U)
7233 #define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)
7234 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk
7235 #define CAN_F9R1_FB26_Pos (26U)
7236 #define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)
7237 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk
7238 #define CAN_F9R1_FB27_Pos (27U)
7239 #define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)
7240 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk
7241 #define CAN_F9R1_FB28_Pos (28U)
7242 #define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)
7243 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk
7244 #define CAN_F9R1_FB29_Pos (29U)
7245 #define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)
7246 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk
7247 #define CAN_F9R1_FB30_Pos (30U)
7248 #define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)
7249 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk
7250 #define CAN_F9R1_FB31_Pos (31U)
7251 #define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)
7252 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk
7254 /******************* Bit definition for CAN_F10R1 register ******************/
7255 #define CAN_F10R1_FB0_Pos (0U)
7256 #define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)
7257 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk
7258 #define CAN_F10R1_FB1_Pos (1U)
7259 #define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)
7260 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk
7261 #define CAN_F10R1_FB2_Pos (2U)
7262 #define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)
7263 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk
7264 #define CAN_F10R1_FB3_Pos (3U)
7265 #define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)
7266 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk
7267 #define CAN_F10R1_FB4_Pos (4U)
7268 #define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)
7269 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk
7270 #define CAN_F10R1_FB5_Pos (5U)
7271 #define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)
7272 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk
7273 #define CAN_F10R1_FB6_Pos (6U)
7274 #define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)
7275 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk
7276 #define CAN_F10R1_FB7_Pos (7U)
7277 #define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)
7278 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk
7279 #define CAN_F10R1_FB8_Pos (8U)
7280 #define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)
7281 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk
7282 #define CAN_F10R1_FB9_Pos (9U)
7283 #define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)
7284 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk
7285 #define CAN_F10R1_FB10_Pos (10U)
7286 #define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)
7287 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk
7288 #define CAN_F10R1_FB11_Pos (11U)
7289 #define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)
7290 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk
7291 #define CAN_F10R1_FB12_Pos (12U)
7292 #define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)
7293 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk
7294 #define CAN_F10R1_FB13_Pos (13U)
7295 #define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)
7296 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk
7297 #define CAN_F10R1_FB14_Pos (14U)
7298 #define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)
7299 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk
7300 #define CAN_F10R1_FB15_Pos (15U)
7301 #define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)
7302 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk
7303 #define CAN_F10R1_FB16_Pos (16U)
7304 #define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)
7305 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk
7306 #define CAN_F10R1_FB17_Pos (17U)
7307 #define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)
7308 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk
7309 #define CAN_F10R1_FB18_Pos (18U)
7310 #define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)
7311 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk
7312 #define CAN_F10R1_FB19_Pos (19U)
7313 #define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)
7314 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk
7315 #define CAN_F10R1_FB20_Pos (20U)
7316 #define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)
7317 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk
7318 #define CAN_F10R1_FB21_Pos (21U)
7319 #define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)
7320 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk
7321 #define CAN_F10R1_FB22_Pos (22U)
7322 #define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)
7323 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk
7324 #define CAN_F10R1_FB23_Pos (23U)
7325 #define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)
7326 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk
7327 #define CAN_F10R1_FB24_Pos (24U)
7328 #define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)
7329 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk
7330 #define CAN_F10R1_FB25_Pos (25U)
7331 #define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)
7332 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk
7333 #define CAN_F10R1_FB26_Pos (26U)
7334 #define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)
7335 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk
7336 #define CAN_F10R1_FB27_Pos (27U)
7337 #define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)
7338 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk
7339 #define CAN_F10R1_FB28_Pos (28U)
7340 #define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)
7341 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk
7342 #define CAN_F10R1_FB29_Pos (29U)
7343 #define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)
7344 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk
7345 #define CAN_F10R1_FB30_Pos (30U)
7346 #define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)
7347 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk
7348 #define CAN_F10R1_FB31_Pos (31U)
7349 #define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)
7350 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk
7352 /******************* Bit definition for CAN_F11R1 register ******************/
7353 #define CAN_F11R1_FB0_Pos (0U)
7354 #define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)
7355 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk
7356 #define CAN_F11R1_FB1_Pos (1U)
7357 #define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)
7358 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk
7359 #define CAN_F11R1_FB2_Pos (2U)
7360 #define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)
7361 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk
7362 #define CAN_F11R1_FB3_Pos (3U)
7363 #define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)
7364 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk
7365 #define CAN_F11R1_FB4_Pos (4U)
7366 #define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)
7367 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk
7368 #define CAN_F11R1_FB5_Pos (5U)
7369 #define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)
7370 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk
7371 #define CAN_F11R1_FB6_Pos (6U)
7372 #define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)
7373 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk
7374 #define CAN_F11R1_FB7_Pos (7U)
7375 #define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)
7376 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk
7377 #define CAN_F11R1_FB8_Pos (8U)
7378 #define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)
7379 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk
7380 #define CAN_F11R1_FB9_Pos (9U)
7381 #define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)
7382 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk
7383 #define CAN_F11R1_FB10_Pos (10U)
7384 #define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)
7385 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk
7386 #define CAN_F11R1_FB11_Pos (11U)
7387 #define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)
7388 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk
7389 #define CAN_F11R1_FB12_Pos (12U)
7390 #define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)
7391 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk
7392 #define CAN_F11R1_FB13_Pos (13U)
7393 #define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)
7394 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk
7395 #define CAN_F11R1_FB14_Pos (14U)
7396 #define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)
7397 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk
7398 #define CAN_F11R1_FB15_Pos (15U)
7399 #define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)
7400 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk
7401 #define CAN_F11R1_FB16_Pos (16U)
7402 #define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)
7403 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk
7404 #define CAN_F11R1_FB17_Pos (17U)
7405 #define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)
7406 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk
7407 #define CAN_F11R1_FB18_Pos (18U)
7408 #define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)
7409 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk
7410 #define CAN_F11R1_FB19_Pos (19U)
7411 #define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)
7412 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk
7413 #define CAN_F11R1_FB20_Pos (20U)
7414 #define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)
7415 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk
7416 #define CAN_F11R1_FB21_Pos (21U)
7417 #define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)
7418 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk
7419 #define CAN_F11R1_FB22_Pos (22U)
7420 #define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)
7421 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk
7422 #define CAN_F11R1_FB23_Pos (23U)
7423 #define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)
7424 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk
7425 #define CAN_F11R1_FB24_Pos (24U)
7426 #define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)
7427 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk
7428 #define CAN_F11R1_FB25_Pos (25U)
7429 #define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)
7430 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk
7431 #define CAN_F11R1_FB26_Pos (26U)
7432 #define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)
7433 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk
7434 #define CAN_F11R1_FB27_Pos (27U)
7435 #define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)
7436 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk
7437 #define CAN_F11R1_FB28_Pos (28U)
7438 #define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)
7439 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk
7440 #define CAN_F11R1_FB29_Pos (29U)
7441 #define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)
7442 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk
7443 #define CAN_F11R1_FB30_Pos (30U)
7444 #define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)
7445 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk
7446 #define CAN_F11R1_FB31_Pos (31U)
7447 #define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)
7448 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk
7450 /******************* Bit definition for CAN_F12R1 register ******************/
7451 #define CAN_F12R1_FB0_Pos (0U)
7452 #define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)
7453 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk
7454 #define CAN_F12R1_FB1_Pos (1U)
7455 #define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)
7456 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk
7457 #define CAN_F12R1_FB2_Pos (2U)
7458 #define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)
7459 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk
7460 #define CAN_F12R1_FB3_Pos (3U)
7461 #define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)
7462 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk
7463 #define CAN_F12R1_FB4_Pos (4U)
7464 #define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)
7465 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk
7466 #define CAN_F12R1_FB5_Pos (5U)
7467 #define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)
7468 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk
7469 #define CAN_F12R1_FB6_Pos (6U)
7470 #define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)
7471 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk
7472 #define CAN_F12R1_FB7_Pos (7U)
7473 #define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)
7474 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk
7475 #define CAN_F12R1_FB8_Pos (8U)
7476 #define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)
7477 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk
7478 #define CAN_F12R1_FB9_Pos (9U)
7479 #define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)
7480 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk
7481 #define CAN_F12R1_FB10_Pos (10U)
7482 #define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)
7483 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk
7484 #define CAN_F12R1_FB11_Pos (11U)
7485 #define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)
7486 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk
7487 #define CAN_F12R1_FB12_Pos (12U)
7488 #define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)
7489 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk
7490 #define CAN_F12R1_FB13_Pos (13U)
7491 #define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)
7492 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk
7493 #define CAN_F12R1_FB14_Pos (14U)
7494 #define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)
7495 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk
7496 #define CAN_F12R1_FB15_Pos (15U)
7497 #define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)
7498 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk
7499 #define CAN_F12R1_FB16_Pos (16U)
7500 #define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)
7501 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk
7502 #define CAN_F12R1_FB17_Pos (17U)
7503 #define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)
7504 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk
7505 #define CAN_F12R1_FB18_Pos (18U)
7506 #define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)
7507 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk
7508 #define CAN_F12R1_FB19_Pos (19U)
7509 #define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)
7510 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk
7511 #define CAN_F12R1_FB20_Pos (20U)
7512 #define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)
7513 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk
7514 #define CAN_F12R1_FB21_Pos (21U)
7515 #define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)
7516 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk
7517 #define CAN_F12R1_FB22_Pos (22U)
7518 #define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)
7519 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk
7520 #define CAN_F12R1_FB23_Pos (23U)
7521 #define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)
7522 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk
7523 #define CAN_F12R1_FB24_Pos (24U)
7524 #define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)
7525 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk
7526 #define CAN_F12R1_FB25_Pos (25U)
7527 #define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)
7528 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk
7529 #define CAN_F12R1_FB26_Pos (26U)
7530 #define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)
7531 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk
7532 #define CAN_F12R1_FB27_Pos (27U)
7533 #define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)
7534 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk
7535 #define CAN_F12R1_FB28_Pos (28U)
7536 #define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)
7537 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk
7538 #define CAN_F12R1_FB29_Pos (29U)
7539 #define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)
7540 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk
7541 #define CAN_F12R1_FB30_Pos (30U)
7542 #define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)
7543 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk
7544 #define CAN_F12R1_FB31_Pos (31U)
7545 #define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)
7546 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk
7548 /******************* Bit definition for CAN_F13R1 register ******************/
7549 #define CAN_F13R1_FB0_Pos (0U)
7550 #define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)
7551 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk
7552 #define CAN_F13R1_FB1_Pos (1U)
7553 #define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)
7554 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk
7555 #define CAN_F13R1_FB2_Pos (2U)
7556 #define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)
7557 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk
7558 #define CAN_F13R1_FB3_Pos (3U)
7559 #define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)
7560 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk
7561 #define CAN_F13R1_FB4_Pos (4U)
7562 #define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)
7563 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk
7564 #define CAN_F13R1_FB5_Pos (5U)
7565 #define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)
7566 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk
7567 #define CAN_F13R1_FB6_Pos (6U)
7568 #define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)
7569 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk
7570 #define CAN_F13R1_FB7_Pos (7U)
7571 #define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)
7572 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk
7573 #define CAN_F13R1_FB8_Pos (8U)
7574 #define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)
7575 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk
7576 #define CAN_F13R1_FB9_Pos (9U)
7577 #define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)
7578 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk
7579 #define CAN_F13R1_FB10_Pos (10U)
7580 #define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)
7581 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk
7582 #define CAN_F13R1_FB11_Pos (11U)
7583 #define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)
7584 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk
7585 #define CAN_F13R1_FB12_Pos (12U)
7586 #define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)
7587 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk
7588 #define CAN_F13R1_FB13_Pos (13U)
7589 #define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)
7590 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk
7591 #define CAN_F13R1_FB14_Pos (14U)
7592 #define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)
7593 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk
7594 #define CAN_F13R1_FB15_Pos (15U)
7595 #define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)
7596 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk
7597 #define CAN_F13R1_FB16_Pos (16U)
7598 #define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)
7599 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk
7600 #define CAN_F13R1_FB17_Pos (17U)
7601 #define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)
7602 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk
7603 #define CAN_F13R1_FB18_Pos (18U)
7604 #define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)
7605 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk
7606 #define CAN_F13R1_FB19_Pos (19U)
7607 #define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)
7608 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk
7609 #define CAN_F13R1_FB20_Pos (20U)
7610 #define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)
7611 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk
7612 #define CAN_F13R1_FB21_Pos (21U)
7613 #define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)
7614 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk
7615 #define CAN_F13R1_FB22_Pos (22U)
7616 #define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)
7617 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk
7618 #define CAN_F13R1_FB23_Pos (23U)
7619 #define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)
7620 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk
7621 #define CAN_F13R1_FB24_Pos (24U)
7622 #define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)
7623 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk
7624 #define CAN_F13R1_FB25_Pos (25U)
7625 #define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)
7626 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk
7627 #define CAN_F13R1_FB26_Pos (26U)
7628 #define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)
7629 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk
7630 #define CAN_F13R1_FB27_Pos (27U)
7631 #define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)
7632 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk
7633 #define CAN_F13R1_FB28_Pos (28U)
7634 #define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)
7635 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk
7636 #define CAN_F13R1_FB29_Pos (29U)
7637 #define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)
7638 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk
7639 #define CAN_F13R1_FB30_Pos (30U)
7640 #define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)
7641 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk
7642 #define CAN_F13R1_FB31_Pos (31U)
7643 #define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)
7644 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk
7646 /******************* Bit definition for CAN_F0R2 register *******************/
7647 #define CAN_F0R2_FB0_Pos (0U)
7648 #define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)
7649 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk
7650 #define CAN_F0R2_FB1_Pos (1U)
7651 #define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)
7652 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk
7653 #define CAN_F0R2_FB2_Pos (2U)
7654 #define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)
7655 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk
7656 #define CAN_F0R2_FB3_Pos (3U)
7657 #define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)
7658 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk
7659 #define CAN_F0R2_FB4_Pos (4U)
7660 #define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)
7661 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk
7662 #define CAN_F0R2_FB5_Pos (5U)
7663 #define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)
7664 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk
7665 #define CAN_F0R2_FB6_Pos (6U)
7666 #define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)
7667 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk
7668 #define CAN_F0R2_FB7_Pos (7U)
7669 #define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)
7670 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk
7671 #define CAN_F0R2_FB8_Pos (8U)
7672 #define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)
7673 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk
7674 #define CAN_F0R2_FB9_Pos (9U)
7675 #define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)
7676 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk
7677 #define CAN_F0R2_FB10_Pos (10U)
7678 #define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)
7679 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk
7680 #define CAN_F0R2_FB11_Pos (11U)
7681 #define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)
7682 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk
7683 #define CAN_F0R2_FB12_Pos (12U)
7684 #define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)
7685 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk
7686 #define CAN_F0R2_FB13_Pos (13U)
7687 #define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)
7688 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk
7689 #define CAN_F0R2_FB14_Pos (14U)
7690 #define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)
7691 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk
7692 #define CAN_F0R2_FB15_Pos (15U)
7693 #define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)
7694 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk
7695 #define CAN_F0R2_FB16_Pos (16U)
7696 #define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)
7697 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk
7698 #define CAN_F0R2_FB17_Pos (17U)
7699 #define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)
7700 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk
7701 #define CAN_F0R2_FB18_Pos (18U)
7702 #define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)
7703 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk
7704 #define CAN_F0R2_FB19_Pos (19U)
7705 #define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)
7706 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk
7707 #define CAN_F0R2_FB20_Pos (20U)
7708 #define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)
7709 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk
7710 #define CAN_F0R2_FB21_Pos (21U)
7711 #define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)
7712 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk
7713 #define CAN_F0R2_FB22_Pos (22U)
7714 #define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)
7715 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk
7716 #define CAN_F0R2_FB23_Pos (23U)
7717 #define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)
7718 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk
7719 #define CAN_F0R2_FB24_Pos (24U)
7720 #define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)
7721 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk
7722 #define CAN_F0R2_FB25_Pos (25U)
7723 #define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)
7724 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk
7725 #define CAN_F0R2_FB26_Pos (26U)
7726 #define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)
7727 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk
7728 #define CAN_F0R2_FB27_Pos (27U)
7729 #define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)
7730 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk
7731 #define CAN_F0R2_FB28_Pos (28U)
7732 #define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)
7733 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk
7734 #define CAN_F0R2_FB29_Pos (29U)
7735 #define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)
7736 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk
7737 #define CAN_F0R2_FB30_Pos (30U)
7738 #define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)
7739 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk
7740 #define CAN_F0R2_FB31_Pos (31U)
7741 #define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)
7742 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk
7744 /******************* Bit definition for CAN_F1R2 register *******************/
7745 #define CAN_F1R2_FB0_Pos (0U)
7746 #define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)
7747 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk
7748 #define CAN_F1R2_FB1_Pos (1U)
7749 #define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)
7750 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk
7751 #define CAN_F1R2_FB2_Pos (2U)
7752 #define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)
7753 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk
7754 #define CAN_F1R2_FB3_Pos (3U)
7755 #define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)
7756 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk
7757 #define CAN_F1R2_FB4_Pos (4U)
7758 #define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)
7759 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk
7760 #define CAN_F1R2_FB5_Pos (5U)
7761 #define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)
7762 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk
7763 #define CAN_F1R2_FB6_Pos (6U)
7764 #define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)
7765 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk
7766 #define CAN_F1R2_FB7_Pos (7U)
7767 #define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)
7768 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk
7769 #define CAN_F1R2_FB8_Pos (8U)
7770 #define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)
7771 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk
7772 #define CAN_F1R2_FB9_Pos (9U)
7773 #define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)
7774 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk
7775 #define CAN_F1R2_FB10_Pos (10U)
7776 #define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)
7777 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk
7778 #define CAN_F1R2_FB11_Pos (11U)
7779 #define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)
7780 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk
7781 #define CAN_F1R2_FB12_Pos (12U)
7782 #define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)
7783 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk
7784 #define CAN_F1R2_FB13_Pos (13U)
7785 #define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)
7786 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk
7787 #define CAN_F1R2_FB14_Pos (14U)
7788 #define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)
7789 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk
7790 #define CAN_F1R2_FB15_Pos (15U)
7791 #define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)
7792 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk
7793 #define CAN_F1R2_FB16_Pos (16U)
7794 #define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)
7795 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk
7796 #define CAN_F1R2_FB17_Pos (17U)
7797 #define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)
7798 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk
7799 #define CAN_F1R2_FB18_Pos (18U)
7800 #define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)
7801 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk
7802 #define CAN_F1R2_FB19_Pos (19U)
7803 #define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)
7804 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk
7805 #define CAN_F1R2_FB20_Pos (20U)
7806 #define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)
7807 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk
7808 #define CAN_F1R2_FB21_Pos (21U)
7809 #define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)
7810 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk
7811 #define CAN_F1R2_FB22_Pos (22U)
7812 #define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)
7813 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk
7814 #define CAN_F1R2_FB23_Pos (23U)
7815 #define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)
7816 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk
7817 #define CAN_F1R2_FB24_Pos (24U)
7818 #define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)
7819 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk
7820 #define CAN_F1R2_FB25_Pos (25U)
7821 #define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)
7822 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk
7823 #define CAN_F1R2_FB26_Pos (26U)
7824 #define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)
7825 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk
7826 #define CAN_F1R2_FB27_Pos (27U)
7827 #define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)
7828 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk
7829 #define CAN_F1R2_FB28_Pos (28U)
7830 #define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)
7831 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk
7832 #define CAN_F1R2_FB29_Pos (29U)
7833 #define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)
7834 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk
7835 #define CAN_F1R2_FB30_Pos (30U)
7836 #define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)
7837 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk
7838 #define CAN_F1R2_FB31_Pos (31U)
7839 #define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)
7840 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk
7842 /******************* Bit definition for CAN_F2R2 register *******************/
7843 #define CAN_F2R2_FB0_Pos (0U)
7844 #define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)
7845 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk
7846 #define CAN_F2R2_FB1_Pos (1U)
7847 #define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)
7848 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk
7849 #define CAN_F2R2_FB2_Pos (2U)
7850 #define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)
7851 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk
7852 #define CAN_F2R2_FB3_Pos (3U)
7853 #define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)
7854 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk
7855 #define CAN_F2R2_FB4_Pos (4U)
7856 #define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)
7857 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk
7858 #define CAN_F2R2_FB5_Pos (5U)
7859 #define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)
7860 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk
7861 #define CAN_F2R2_FB6_Pos (6U)
7862 #define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)
7863 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk
7864 #define CAN_F2R2_FB7_Pos (7U)
7865 #define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)
7866 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk
7867 #define CAN_F2R2_FB8_Pos (8U)
7868 #define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)
7869 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk
7870 #define CAN_F2R2_FB9_Pos (9U)
7871 #define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)
7872 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk
7873 #define CAN_F2R2_FB10_Pos (10U)
7874 #define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)
7875 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk
7876 #define CAN_F2R2_FB11_Pos (11U)
7877 #define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)
7878 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk
7879 #define CAN_F2R2_FB12_Pos (12U)
7880 #define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)
7881 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk
7882 #define CAN_F2R2_FB13_Pos (13U)
7883 #define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)
7884 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk
7885 #define CAN_F2R2_FB14_Pos (14U)
7886 #define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)
7887 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk
7888 #define CAN_F2R2_FB15_Pos (15U)
7889 #define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)
7890 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk
7891 #define CAN_F2R2_FB16_Pos (16U)
7892 #define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)
7893 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk
7894 #define CAN_F2R2_FB17_Pos (17U)
7895 #define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)
7896 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk
7897 #define CAN_F2R2_FB18_Pos (18U)
7898 #define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)
7899 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk
7900 #define CAN_F2R2_FB19_Pos (19U)
7901 #define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)
7902 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk
7903 #define CAN_F2R2_FB20_Pos (20U)
7904 #define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)
7905 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk
7906 #define CAN_F2R2_FB21_Pos (21U)
7907 #define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)
7908 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk
7909 #define CAN_F2R2_FB22_Pos (22U)
7910 #define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)
7911 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk
7912 #define CAN_F2R2_FB23_Pos (23U)
7913 #define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)
7914 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk
7915 #define CAN_F2R2_FB24_Pos (24U)
7916 #define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)
7917 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk
7918 #define CAN_F2R2_FB25_Pos (25U)
7919 #define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)
7920 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk
7921 #define CAN_F2R2_FB26_Pos (26U)
7922 #define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)
7923 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk
7924 #define CAN_F2R2_FB27_Pos (27U)
7925 #define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)
7926 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk
7927 #define CAN_F2R2_FB28_Pos (28U)
7928 #define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)
7929 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk
7930 #define CAN_F2R2_FB29_Pos (29U)
7931 #define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)
7932 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk
7933 #define CAN_F2R2_FB30_Pos (30U)
7934 #define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)
7935 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk
7936 #define CAN_F2R2_FB31_Pos (31U)
7937 #define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)
7938 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk
7940 /******************* Bit definition for CAN_F3R2 register *******************/
7941 #define CAN_F3R2_FB0_Pos (0U)
7942 #define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)
7943 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk
7944 #define CAN_F3R2_FB1_Pos (1U)
7945 #define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)
7946 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk
7947 #define CAN_F3R2_FB2_Pos (2U)
7948 #define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)
7949 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk
7950 #define CAN_F3R2_FB3_Pos (3U)
7951 #define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)
7952 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk
7953 #define CAN_F3R2_FB4_Pos (4U)
7954 #define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)
7955 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk
7956 #define CAN_F3R2_FB5_Pos (5U)
7957 #define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)
7958 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk
7959 #define CAN_F3R2_FB6_Pos (6U)
7960 #define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)
7961 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk
7962 #define CAN_F3R2_FB7_Pos (7U)
7963 #define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)
7964 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk
7965 #define CAN_F3R2_FB8_Pos (8U)
7966 #define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)
7967 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk
7968 #define CAN_F3R2_FB9_Pos (9U)
7969 #define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)
7970 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk
7971 #define CAN_F3R2_FB10_Pos (10U)
7972 #define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)
7973 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk
7974 #define CAN_F3R2_FB11_Pos (11U)
7975 #define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)
7976 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk
7977 #define CAN_F3R2_FB12_Pos (12U)
7978 #define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)
7979 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk
7980 #define CAN_F3R2_FB13_Pos (13U)
7981 #define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)
7982 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk
7983 #define CAN_F3R2_FB14_Pos (14U)
7984 #define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)
7985 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk
7986 #define CAN_F3R2_FB15_Pos (15U)
7987 #define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)
7988 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk
7989 #define CAN_F3R2_FB16_Pos (16U)
7990 #define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)
7991 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk
7992 #define CAN_F3R2_FB17_Pos (17U)
7993 #define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)
7994 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk
7995 #define CAN_F3R2_FB18_Pos (18U)
7996 #define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)
7997 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk
7998 #define CAN_F3R2_FB19_Pos (19U)
7999 #define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)
8000 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk
8001 #define CAN_F3R2_FB20_Pos (20U)
8002 #define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)
8003 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk
8004 #define CAN_F3R2_FB21_Pos (21U)
8005 #define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)
8006 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk
8007 #define CAN_F3R2_FB22_Pos (22U)
8008 #define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)
8009 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk
8010 #define CAN_F3R2_FB23_Pos (23U)
8011 #define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)
8012 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk
8013 #define CAN_F3R2_FB24_Pos (24U)
8014 #define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)
8015 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk
8016 #define CAN_F3R2_FB25_Pos (25U)
8017 #define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)
8018 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk
8019 #define CAN_F3R2_FB26_Pos (26U)
8020 #define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)
8021 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk
8022 #define CAN_F3R2_FB27_Pos (27U)
8023 #define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)
8024 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk
8025 #define CAN_F3R2_FB28_Pos (28U)
8026 #define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)
8027 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk
8028 #define CAN_F3R2_FB29_Pos (29U)
8029 #define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)
8030 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk
8031 #define CAN_F3R2_FB30_Pos (30U)
8032 #define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)
8033 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk
8034 #define CAN_F3R2_FB31_Pos (31U)
8035 #define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)
8036 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk
8038 /******************* Bit definition for CAN_F4R2 register *******************/
8039 #define CAN_F4R2_FB0_Pos (0U)
8040 #define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)
8041 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk
8042 #define CAN_F4R2_FB1_Pos (1U)
8043 #define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)
8044 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk
8045 #define CAN_F4R2_FB2_Pos (2U)
8046 #define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)
8047 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk
8048 #define CAN_F4R2_FB3_Pos (3U)
8049 #define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)
8050 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk
8051 #define CAN_F4R2_FB4_Pos (4U)
8052 #define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)
8053 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk
8054 #define CAN_F4R2_FB5_Pos (5U)
8055 #define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)
8056 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk
8057 #define CAN_F4R2_FB6_Pos (6U)
8058 #define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)
8059 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk
8060 #define CAN_F4R2_FB7_Pos (7U)
8061 #define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)
8062 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk
8063 #define CAN_F4R2_FB8_Pos (8U)
8064 #define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)
8065 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk
8066 #define CAN_F4R2_FB9_Pos (9U)
8067 #define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)
8068 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk
8069 #define CAN_F4R2_FB10_Pos (10U)
8070 #define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)
8071 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk
8072 #define CAN_F4R2_FB11_Pos (11U)
8073 #define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)
8074 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk
8075 #define CAN_F4R2_FB12_Pos (12U)
8076 #define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)
8077 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk
8078 #define CAN_F4R2_FB13_Pos (13U)
8079 #define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)
8080 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk
8081 #define CAN_F4R2_FB14_Pos (14U)
8082 #define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)
8083 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk
8084 #define CAN_F4R2_FB15_Pos (15U)
8085 #define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)
8086 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk
8087 #define CAN_F4R2_FB16_Pos (16U)
8088 #define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)
8089 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk
8090 #define CAN_F4R2_FB17_Pos (17U)
8091 #define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)
8092 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk
8093 #define CAN_F4R2_FB18_Pos (18U)
8094 #define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)
8095 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk
8096 #define CAN_F4R2_FB19_Pos (19U)
8097 #define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)
8098 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk
8099 #define CAN_F4R2_FB20_Pos (20U)
8100 #define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)
8101 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk
8102 #define CAN_F4R2_FB21_Pos (21U)
8103 #define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)
8104 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk
8105 #define CAN_F4R2_FB22_Pos (22U)
8106 #define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)
8107 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk
8108 #define CAN_F4R2_FB23_Pos (23U)
8109 #define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)
8110 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk
8111 #define CAN_F4R2_FB24_Pos (24U)
8112 #define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)
8113 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk
8114 #define CAN_F4R2_FB25_Pos (25U)
8115 #define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)
8116 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk
8117 #define CAN_F4R2_FB26_Pos (26U)
8118 #define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)
8119 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk
8120 #define CAN_F4R2_FB27_Pos (27U)
8121 #define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)
8122 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk
8123 #define CAN_F4R2_FB28_Pos (28U)
8124 #define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)
8125 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk
8126 #define CAN_F4R2_FB29_Pos (29U)
8127 #define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)
8128 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk
8129 #define CAN_F4R2_FB30_Pos (30U)
8130 #define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)
8131 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk
8132 #define CAN_F4R2_FB31_Pos (31U)
8133 #define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)
8134 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk
8136 /******************* Bit definition for CAN_F5R2 register *******************/
8137 #define CAN_F5R2_FB0_Pos (0U)
8138 #define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)
8139 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk
8140 #define CAN_F5R2_FB1_Pos (1U)
8141 #define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)
8142 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk
8143 #define CAN_F5R2_FB2_Pos (2U)
8144 #define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)
8145 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk
8146 #define CAN_F5R2_FB3_Pos (3U)
8147 #define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)
8148 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk
8149 #define CAN_F5R2_FB4_Pos (4U)
8150 #define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)
8151 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk
8152 #define CAN_F5R2_FB5_Pos (5U)
8153 #define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)
8154 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk
8155 #define CAN_F5R2_FB6_Pos (6U)
8156 #define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)
8157 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk
8158 #define CAN_F5R2_FB7_Pos (7U)
8159 #define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)
8160 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk
8161 #define CAN_F5R2_FB8_Pos (8U)
8162 #define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)
8163 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk
8164 #define CAN_F5R2_FB9_Pos (9U)
8165 #define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)
8166 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk
8167 #define CAN_F5R2_FB10_Pos (10U)
8168 #define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)
8169 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk
8170 #define CAN_F5R2_FB11_Pos (11U)
8171 #define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)
8172 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk
8173 #define CAN_F5R2_FB12_Pos (12U)
8174 #define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)
8175 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk
8176 #define CAN_F5R2_FB13_Pos (13U)
8177 #define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)
8178 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk
8179 #define CAN_F5R2_FB14_Pos (14U)
8180 #define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)
8181 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk
8182 #define CAN_F5R2_FB15_Pos (15U)
8183 #define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)
8184 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk
8185 #define CAN_F5R2_FB16_Pos (16U)
8186 #define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)
8187 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk
8188 #define CAN_F5R2_FB17_Pos (17U)
8189 #define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)
8190 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk
8191 #define CAN_F5R2_FB18_Pos (18U)
8192 #define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)
8193 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk
8194 #define CAN_F5R2_FB19_Pos (19U)
8195 #define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)
8196 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk
8197 #define CAN_F5R2_FB20_Pos (20U)
8198 #define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)
8199 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk
8200 #define CAN_F5R2_FB21_Pos (21U)
8201 #define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)
8202 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk
8203 #define CAN_F5R2_FB22_Pos (22U)
8204 #define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)
8205 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk
8206 #define CAN_F5R2_FB23_Pos (23U)
8207 #define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)
8208 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk
8209 #define CAN_F5R2_FB24_Pos (24U)
8210 #define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)
8211 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk
8212 #define CAN_F5R2_FB25_Pos (25U)
8213 #define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)
8214 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk
8215 #define CAN_F5R2_FB26_Pos (26U)
8216 #define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)
8217 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk
8218 #define CAN_F5R2_FB27_Pos (27U)
8219 #define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)
8220 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk
8221 #define CAN_F5R2_FB28_Pos (28U)
8222 #define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)
8223 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk
8224 #define CAN_F5R2_FB29_Pos (29U)
8225 #define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)
8226 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk
8227 #define CAN_F5R2_FB30_Pos (30U)
8228 #define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)
8229 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk
8230 #define CAN_F5R2_FB31_Pos (31U)
8231 #define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)
8232 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk
8234 /******************* Bit definition for CAN_F6R2 register *******************/
8235 #define CAN_F6R2_FB0_Pos (0U)
8236 #define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)
8237 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk
8238 #define CAN_F6R2_FB1_Pos (1U)
8239 #define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)
8240 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk
8241 #define CAN_F6R2_FB2_Pos (2U)
8242 #define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)
8243 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk
8244 #define CAN_F6R2_FB3_Pos (3U)
8245 #define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)
8246 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk
8247 #define CAN_F6R2_FB4_Pos (4U)
8248 #define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)
8249 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk
8250 #define CAN_F6R2_FB5_Pos (5U)
8251 #define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)
8252 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk
8253 #define CAN_F6R2_FB6_Pos (6U)
8254 #define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)
8255 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk
8256 #define CAN_F6R2_FB7_Pos (7U)
8257 #define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)
8258 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk
8259 #define CAN_F6R2_FB8_Pos (8U)
8260 #define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)
8261 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk
8262 #define CAN_F6R2_FB9_Pos (9U)
8263 #define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)
8264 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk
8265 #define CAN_F6R2_FB10_Pos (10U)
8266 #define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)
8267 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk
8268 #define CAN_F6R2_FB11_Pos (11U)
8269 #define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)
8270 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk
8271 #define CAN_F6R2_FB12_Pos (12U)
8272 #define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)
8273 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk
8274 #define CAN_F6R2_FB13_Pos (13U)
8275 #define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)
8276 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk
8277 #define CAN_F6R2_FB14_Pos (14U)
8278 #define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)
8279 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk
8280 #define CAN_F6R2_FB15_Pos (15U)
8281 #define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)
8282 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk
8283 #define CAN_F6R2_FB16_Pos (16U)
8284 #define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)
8285 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk
8286 #define CAN_F6R2_FB17_Pos (17U)
8287 #define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)
8288 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk
8289 #define CAN_F6R2_FB18_Pos (18U)
8290 #define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)
8291 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk
8292 #define CAN_F6R2_FB19_Pos (19U)
8293 #define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)
8294 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk
8295 #define CAN_F6R2_FB20_Pos (20U)
8296 #define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)
8297 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk
8298 #define CAN_F6R2_FB21_Pos (21U)
8299 #define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)
8300 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk
8301 #define CAN_F6R2_FB22_Pos (22U)
8302 #define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)
8303 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk
8304 #define CAN_F6R2_FB23_Pos (23U)
8305 #define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)
8306 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk
8307 #define CAN_F6R2_FB24_Pos (24U)
8308 #define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)
8309 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk
8310 #define CAN_F6R2_FB25_Pos (25U)
8311 #define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)
8312 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk
8313 #define CAN_F6R2_FB26_Pos (26U)
8314 #define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)
8315 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk
8316 #define CAN_F6R2_FB27_Pos (27U)
8317 #define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)
8318 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk
8319 #define CAN_F6R2_FB28_Pos (28U)
8320 #define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)
8321 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk
8322 #define CAN_F6R2_FB29_Pos (29U)
8323 #define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)
8324 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk
8325 #define CAN_F6R2_FB30_Pos (30U)
8326 #define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)
8327 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk
8328 #define CAN_F6R2_FB31_Pos (31U)
8329 #define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)
8330 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk
8332 /******************* Bit definition for CAN_F7R2 register *******************/
8333 #define CAN_F7R2_FB0_Pos (0U)
8334 #define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)
8335 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk
8336 #define CAN_F7R2_FB1_Pos (1U)
8337 #define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)
8338 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk
8339 #define CAN_F7R2_FB2_Pos (2U)
8340 #define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)
8341 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk
8342 #define CAN_F7R2_FB3_Pos (3U)
8343 #define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)
8344 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk
8345 #define CAN_F7R2_FB4_Pos (4U)
8346 #define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)
8347 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk
8348 #define CAN_F7R2_FB5_Pos (5U)
8349 #define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)
8350 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk
8351 #define CAN_F7R2_FB6_Pos (6U)
8352 #define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)
8353 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk
8354 #define CAN_F7R2_FB7_Pos (7U)
8355 #define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)
8356 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk
8357 #define CAN_F7R2_FB8_Pos (8U)
8358 #define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)
8359 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk
8360 #define CAN_F7R2_FB9_Pos (9U)
8361 #define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)
8362 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk
8363 #define CAN_F7R2_FB10_Pos (10U)
8364 #define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)
8365 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk
8366 #define CAN_F7R2_FB11_Pos (11U)
8367 #define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)
8368 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk
8369 #define CAN_F7R2_FB12_Pos (12U)
8370 #define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)
8371 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk
8372 #define CAN_F7R2_FB13_Pos (13U)
8373 #define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)
8374 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk
8375 #define CAN_F7R2_FB14_Pos (14U)
8376 #define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)
8377 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk
8378 #define CAN_F7R2_FB15_Pos (15U)
8379 #define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)
8380 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk
8381 #define CAN_F7R2_FB16_Pos (16U)
8382 #define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)
8383 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk
8384 #define CAN_F7R2_FB17_Pos (17U)
8385 #define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)
8386 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk
8387 #define CAN_F7R2_FB18_Pos (18U)
8388 #define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)
8389 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk
8390 #define CAN_F7R2_FB19_Pos (19U)
8391 #define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)
8392 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk
8393 #define CAN_F7R2_FB20_Pos (20U)
8394 #define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)
8395 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk
8396 #define CAN_F7R2_FB21_Pos (21U)
8397 #define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)
8398 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk
8399 #define CAN_F7R2_FB22_Pos (22U)
8400 #define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)
8401 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk
8402 #define CAN_F7R2_FB23_Pos (23U)
8403 #define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)
8404 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk
8405 #define CAN_F7R2_FB24_Pos (24U)
8406 #define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)
8407 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk
8408 #define CAN_F7R2_FB25_Pos (25U)
8409 #define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)
8410 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk
8411 #define CAN_F7R2_FB26_Pos (26U)
8412 #define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)
8413 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk
8414 #define CAN_F7R2_FB27_Pos (27U)
8415 #define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)
8416 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk
8417 #define CAN_F7R2_FB28_Pos (28U)
8418 #define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)
8419 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk
8420 #define CAN_F7R2_FB29_Pos (29U)
8421 #define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)
8422 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk
8423 #define CAN_F7R2_FB30_Pos (30U)
8424 #define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)
8425 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk
8426 #define CAN_F7R2_FB31_Pos (31U)
8427 #define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)
8428 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk
8430 /******************* Bit definition for CAN_F8R2 register *******************/
8431 #define CAN_F8R2_FB0_Pos (0U)
8432 #define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)
8433 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk
8434 #define CAN_F8R2_FB1_Pos (1U)
8435 #define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)
8436 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk
8437 #define CAN_F8R2_FB2_Pos (2U)
8438 #define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)
8439 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk
8440 #define CAN_F8R2_FB3_Pos (3U)
8441 #define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)
8442 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk
8443 #define CAN_F8R2_FB4_Pos (4U)
8444 #define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)
8445 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk
8446 #define CAN_F8R2_FB5_Pos (5U)
8447 #define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)
8448 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk
8449 #define CAN_F8R2_FB6_Pos (6U)
8450 #define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)
8451 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk
8452 #define CAN_F8R2_FB7_Pos (7U)
8453 #define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)
8454 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk
8455 #define CAN_F8R2_FB8_Pos (8U)
8456 #define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)
8457 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk
8458 #define CAN_F8R2_FB9_Pos (9U)
8459 #define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)
8460 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk
8461 #define CAN_F8R2_FB10_Pos (10U)
8462 #define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)
8463 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk
8464 #define CAN_F8R2_FB11_Pos (11U)
8465 #define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)
8466 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk
8467 #define CAN_F8R2_FB12_Pos (12U)
8468 #define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)
8469 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk
8470 #define CAN_F8R2_FB13_Pos (13U)
8471 #define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)
8472 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk
8473 #define CAN_F8R2_FB14_Pos (14U)
8474 #define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)
8475 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk
8476 #define CAN_F8R2_FB15_Pos (15U)
8477 #define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)
8478 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk
8479 #define CAN_F8R2_FB16_Pos (16U)
8480 #define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)
8481 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk
8482 #define CAN_F8R2_FB17_Pos (17U)
8483 #define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)
8484 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk
8485 #define CAN_F8R2_FB18_Pos (18U)
8486 #define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)
8487 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk
8488 #define CAN_F8R2_FB19_Pos (19U)
8489 #define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)
8490 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk
8491 #define CAN_F8R2_FB20_Pos (20U)
8492 #define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)
8493 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk
8494 #define CAN_F8R2_FB21_Pos (21U)
8495 #define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)
8496 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk
8497 #define CAN_F8R2_FB22_Pos (22U)
8498 #define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)
8499 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk
8500 #define CAN_F8R2_FB23_Pos (23U)
8501 #define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)
8502 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk
8503 #define CAN_F8R2_FB24_Pos (24U)
8504 #define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)
8505 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk
8506 #define CAN_F8R2_FB25_Pos (25U)
8507 #define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)
8508 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk
8509 #define CAN_F8R2_FB26_Pos (26U)
8510 #define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)
8511 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk
8512 #define CAN_F8R2_FB27_Pos (27U)
8513 #define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)
8514 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk
8515 #define CAN_F8R2_FB28_Pos (28U)
8516 #define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)
8517 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk
8518 #define CAN_F8R2_FB29_Pos (29U)
8519 #define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)
8520 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk
8521 #define CAN_F8R2_FB30_Pos (30U)
8522 #define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)
8523 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk
8524 #define CAN_F8R2_FB31_Pos (31U)
8525 #define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)
8526 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk
8528 /******************* Bit definition for CAN_F9R2 register *******************/
8529 #define CAN_F9R2_FB0_Pos (0U)
8530 #define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)
8531 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk
8532 #define CAN_F9R2_FB1_Pos (1U)
8533 #define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)
8534 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk
8535 #define CAN_F9R2_FB2_Pos (2U)
8536 #define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)
8537 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk
8538 #define CAN_F9R2_FB3_Pos (3U)
8539 #define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)
8540 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk
8541 #define CAN_F9R2_FB4_Pos (4U)
8542 #define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)
8543 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk
8544 #define CAN_F9R2_FB5_Pos (5U)
8545 #define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)
8546 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk
8547 #define CAN_F9R2_FB6_Pos (6U)
8548 #define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)
8549 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk
8550 #define CAN_F9R2_FB7_Pos (7U)
8551 #define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)
8552 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk
8553 #define CAN_F9R2_FB8_Pos (8U)
8554 #define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)
8555 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk
8556 #define CAN_F9R2_FB9_Pos (9U)
8557 #define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)
8558 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk
8559 #define CAN_F9R2_FB10_Pos (10U)
8560 #define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)
8561 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk
8562 #define CAN_F9R2_FB11_Pos (11U)
8563 #define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)
8564 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk
8565 #define CAN_F9R2_FB12_Pos (12U)
8566 #define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)
8567 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk
8568 #define CAN_F9R2_FB13_Pos (13U)
8569 #define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)
8570 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk
8571 #define CAN_F9R2_FB14_Pos (14U)
8572 #define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)
8573 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk
8574 #define CAN_F9R2_FB15_Pos (15U)
8575 #define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)
8576 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk
8577 #define CAN_F9R2_FB16_Pos (16U)
8578 #define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)
8579 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk
8580 #define CAN_F9R2_FB17_Pos (17U)
8581 #define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)
8582 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk
8583 #define CAN_F9R2_FB18_Pos (18U)
8584 #define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)
8585 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk
8586 #define CAN_F9R2_FB19_Pos (19U)
8587 #define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)
8588 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk
8589 #define CAN_F9R2_FB20_Pos (20U)
8590 #define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)
8591 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk
8592 #define CAN_F9R2_FB21_Pos (21U)
8593 #define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)
8594 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk
8595 #define CAN_F9R2_FB22_Pos (22U)
8596 #define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)
8597 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk
8598 #define CAN_F9R2_FB23_Pos (23U)
8599 #define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)
8600 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk
8601 #define CAN_F9R2_FB24_Pos (24U)
8602 #define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)
8603 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk
8604 #define CAN_F9R2_FB25_Pos (25U)
8605 #define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)
8606 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk
8607 #define CAN_F9R2_FB26_Pos (26U)
8608 #define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)
8609 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk
8610 #define CAN_F9R2_FB27_Pos (27U)
8611 #define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)
8612 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk
8613 #define CAN_F9R2_FB28_Pos (28U)
8614 #define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)
8615 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk
8616 #define CAN_F9R2_FB29_Pos (29U)
8617 #define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)
8618 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk
8619 #define CAN_F9R2_FB30_Pos (30U)
8620 #define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)
8621 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk
8622 #define CAN_F9R2_FB31_Pos (31U)
8623 #define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)
8624 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk
8626 /******************* Bit definition for CAN_F10R2 register ******************/
8627 #define CAN_F10R2_FB0_Pos (0U)
8628 #define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)
8629 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk
8630 #define CAN_F10R2_FB1_Pos (1U)
8631 #define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)
8632 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk
8633 #define CAN_F10R2_FB2_Pos (2U)
8634 #define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)
8635 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk
8636 #define CAN_F10R2_FB3_Pos (3U)
8637 #define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)
8638 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk
8639 #define CAN_F10R2_FB4_Pos (4U)
8640 #define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)
8641 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk
8642 #define CAN_F10R2_FB5_Pos (5U)
8643 #define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)
8644 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk
8645 #define CAN_F10R2_FB6_Pos (6U)
8646 #define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)
8647 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk
8648 #define CAN_F10R2_FB7_Pos (7U)
8649 #define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)
8650 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk
8651 #define CAN_F10R2_FB8_Pos (8U)
8652 #define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)
8653 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk
8654 #define CAN_F10R2_FB9_Pos (9U)
8655 #define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)
8656 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk
8657 #define CAN_F10R2_FB10_Pos (10U)
8658 #define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)
8659 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk
8660 #define CAN_F10R2_FB11_Pos (11U)
8661 #define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)
8662 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk
8663 #define CAN_F10R2_FB12_Pos (12U)
8664 #define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)
8665 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk
8666 #define CAN_F10R2_FB13_Pos (13U)
8667 #define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)
8668 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk
8669 #define CAN_F10R2_FB14_Pos (14U)
8670 #define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)
8671 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk
8672 #define CAN_F10R2_FB15_Pos (15U)
8673 #define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)
8674 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk
8675 #define CAN_F10R2_FB16_Pos (16U)
8676 #define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)
8677 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk
8678 #define CAN_F10R2_FB17_Pos (17U)
8679 #define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)
8680 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk
8681 #define CAN_F10R2_FB18_Pos (18U)
8682 #define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)
8683 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk
8684 #define CAN_F10R2_FB19_Pos (19U)
8685 #define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)
8686 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk
8687 #define CAN_F10R2_FB20_Pos (20U)
8688 #define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)
8689 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk
8690 #define CAN_F10R2_FB21_Pos (21U)
8691 #define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)
8692 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk
8693 #define CAN_F10R2_FB22_Pos (22U)
8694 #define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)
8695 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk
8696 #define CAN_F10R2_FB23_Pos (23U)
8697 #define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)
8698 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk
8699 #define CAN_F10R2_FB24_Pos (24U)
8700 #define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)
8701 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk
8702 #define CAN_F10R2_FB25_Pos (25U)
8703 #define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)
8704 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk
8705 #define CAN_F10R2_FB26_Pos (26U)
8706 #define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)
8707 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk
8708 #define CAN_F10R2_FB27_Pos (27U)
8709 #define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)
8710 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk
8711 #define CAN_F10R2_FB28_Pos (28U)
8712 #define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)
8713 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk
8714 #define CAN_F10R2_FB29_Pos (29U)
8715 #define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)
8716 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk
8717 #define CAN_F10R2_FB30_Pos (30U)
8718 #define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)
8719 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk
8720 #define CAN_F10R2_FB31_Pos (31U)
8721 #define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)
8722 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk
8724 /******************* Bit definition for CAN_F11R2 register ******************/
8725 #define CAN_F11R2_FB0_Pos (0U)
8726 #define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)
8727 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk
8728 #define CAN_F11R2_FB1_Pos (1U)
8729 #define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)
8730 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk
8731 #define CAN_F11R2_FB2_Pos (2U)
8732 #define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)
8733 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk
8734 #define CAN_F11R2_FB3_Pos (3U)
8735 #define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)
8736 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk
8737 #define CAN_F11R2_FB4_Pos (4U)
8738 #define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)
8739 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk
8740 #define CAN_F11R2_FB5_Pos (5U)
8741 #define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)
8742 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk
8743 #define CAN_F11R2_FB6_Pos (6U)
8744 #define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)
8745 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk
8746 #define CAN_F11R2_FB7_Pos (7U)
8747 #define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)
8748 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk
8749 #define CAN_F11R2_FB8_Pos (8U)
8750 #define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)
8751 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk
8752 #define CAN_F11R2_FB9_Pos (9U)
8753 #define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)
8754 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk
8755 #define CAN_F11R2_FB10_Pos (10U)
8756 #define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)
8757 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk
8758 #define CAN_F11R2_FB11_Pos (11U)
8759 #define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)
8760 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk
8761 #define CAN_F11R2_FB12_Pos (12U)
8762 #define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)
8763 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk
8764 #define CAN_F11R2_FB13_Pos (13U)
8765 #define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)
8766 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk
8767 #define CAN_F11R2_FB14_Pos (14U)
8768 #define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)
8769 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk
8770 #define CAN_F11R2_FB15_Pos (15U)
8771 #define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)
8772 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk
8773 #define CAN_F11R2_FB16_Pos (16U)
8774 #define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)
8775 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk
8776 #define CAN_F11R2_FB17_Pos (17U)
8777 #define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)
8778 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk
8779 #define CAN_F11R2_FB18_Pos (18U)
8780 #define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)
8781 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk
8782 #define CAN_F11R2_FB19_Pos (19U)
8783 #define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)
8784 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk
8785 #define CAN_F11R2_FB20_Pos (20U)
8786 #define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)
8787 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk
8788 #define CAN_F11R2_FB21_Pos (21U)
8789 #define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)
8790 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk
8791 #define CAN_F11R2_FB22_Pos (22U)
8792 #define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)
8793 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk
8794 #define CAN_F11R2_FB23_Pos (23U)
8795 #define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)
8796 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk
8797 #define CAN_F11R2_FB24_Pos (24U)
8798 #define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)
8799 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk
8800 #define CAN_F11R2_FB25_Pos (25U)
8801 #define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)
8802 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk
8803 #define CAN_F11R2_FB26_Pos (26U)
8804 #define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)
8805 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk
8806 #define CAN_F11R2_FB27_Pos (27U)
8807 #define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)
8808 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk
8809 #define CAN_F11R2_FB28_Pos (28U)
8810 #define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)
8811 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk
8812 #define CAN_F11R2_FB29_Pos (29U)
8813 #define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)
8814 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk
8815 #define CAN_F11R2_FB30_Pos (30U)
8816 #define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)
8817 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk
8818 #define CAN_F11R2_FB31_Pos (31U)
8819 #define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)
8820 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk
8822 /******************* Bit definition for CAN_F12R2 register ******************/
8823 #define CAN_F12R2_FB0_Pos (0U)
8824 #define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)
8825 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk
8826 #define CAN_F12R2_FB1_Pos (1U)
8827 #define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)
8828 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk
8829 #define CAN_F12R2_FB2_Pos (2U)
8830 #define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)
8831 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk
8832 #define CAN_F12R2_FB3_Pos (3U)
8833 #define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)
8834 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk
8835 #define CAN_F12R2_FB4_Pos (4U)
8836 #define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)
8837 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk
8838 #define CAN_F12R2_FB5_Pos (5U)
8839 #define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)
8840 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk
8841 #define CAN_F12R2_FB6_Pos (6U)
8842 #define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)
8843 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk
8844 #define CAN_F12R2_FB7_Pos (7U)
8845 #define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)
8846 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk
8847 #define CAN_F12R2_FB8_Pos (8U)
8848 #define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)
8849 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk
8850 #define CAN_F12R2_FB9_Pos (9U)
8851 #define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)
8852 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk
8853 #define CAN_F12R2_FB10_Pos (10U)
8854 #define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)
8855 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk
8856 #define CAN_F12R2_FB11_Pos (11U)
8857 #define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)
8858 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk
8859 #define CAN_F12R2_FB12_Pos (12U)
8860 #define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)
8861 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk
8862 #define CAN_F12R2_FB13_Pos (13U)
8863 #define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)
8864 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk
8865 #define CAN_F12R2_FB14_Pos (14U)
8866 #define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)
8867 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk
8868 #define CAN_F12R2_FB15_Pos (15U)
8869 #define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)
8870 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk
8871 #define CAN_F12R2_FB16_Pos (16U)
8872 #define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)
8873 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk
8874 #define CAN_F12R2_FB17_Pos (17U)
8875 #define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)
8876 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk
8877 #define CAN_F12R2_FB18_Pos (18U)
8878 #define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)
8879 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk
8880 #define CAN_F12R2_FB19_Pos (19U)
8881 #define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)
8882 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk
8883 #define CAN_F12R2_FB20_Pos (20U)
8884 #define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)
8885 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk
8886 #define CAN_F12R2_FB21_Pos (21U)
8887 #define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)
8888 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk
8889 #define CAN_F12R2_FB22_Pos (22U)
8890 #define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)
8891 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk
8892 #define CAN_F12R2_FB23_Pos (23U)
8893 #define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)
8894 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk
8895 #define CAN_F12R2_FB24_Pos (24U)
8896 #define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)
8897 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk
8898 #define CAN_F12R2_FB25_Pos (25U)
8899 #define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)
8900 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk
8901 #define CAN_F12R2_FB26_Pos (26U)
8902 #define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)
8903 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk
8904 #define CAN_F12R2_FB27_Pos (27U)
8905 #define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)
8906 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk
8907 #define CAN_F12R2_FB28_Pos (28U)
8908 #define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)
8909 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk
8910 #define CAN_F12R2_FB29_Pos (29U)
8911 #define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)
8912 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk
8913 #define CAN_F12R2_FB30_Pos (30U)
8914 #define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)
8915 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk
8916 #define CAN_F12R2_FB31_Pos (31U)
8917 #define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)
8918 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk
8920 /******************* Bit definition for CAN_F13R2 register ******************/
8921 #define CAN_F13R2_FB0_Pos (0U)
8922 #define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)
8923 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk
8924 #define CAN_F13R2_FB1_Pos (1U)
8925 #define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)
8926 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk
8927 #define CAN_F13R2_FB2_Pos (2U)
8928 #define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)
8929 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk
8930 #define CAN_F13R2_FB3_Pos (3U)
8931 #define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)
8932 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk
8933 #define CAN_F13R2_FB4_Pos (4U)
8934 #define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)
8935 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk
8936 #define CAN_F13R2_FB5_Pos (5U)
8937 #define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)
8938 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk
8939 #define CAN_F13R2_FB6_Pos (6U)
8940 #define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)
8941 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk
8942 #define CAN_F13R2_FB7_Pos (7U)
8943 #define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)
8944 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk
8945 #define CAN_F13R2_FB8_Pos (8U)
8946 #define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)
8947 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk
8948 #define CAN_F13R2_FB9_Pos (9U)
8949 #define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)
8950 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk
8951 #define CAN_F13R2_FB10_Pos (10U)
8952 #define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)
8953 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk
8954 #define CAN_F13R2_FB11_Pos (11U)
8955 #define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)
8956 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk
8957 #define CAN_F13R2_FB12_Pos (12U)
8958 #define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)
8959 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk
8960 #define CAN_F13R2_FB13_Pos (13U)
8961 #define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)
8962 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk
8963 #define CAN_F13R2_FB14_Pos (14U)
8964 #define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)
8965 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk
8966 #define CAN_F13R2_FB15_Pos (15U)
8967 #define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)
8968 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk
8969 #define CAN_F13R2_FB16_Pos (16U)
8970 #define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)
8971 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk
8972 #define CAN_F13R2_FB17_Pos (17U)
8973 #define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)
8974 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk
8975 #define CAN_F13R2_FB18_Pos (18U)
8976 #define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)
8977 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk
8978 #define CAN_F13R2_FB19_Pos (19U)
8979 #define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)
8980 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk
8981 #define CAN_F13R2_FB20_Pos (20U)
8982 #define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)
8983 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk
8984 #define CAN_F13R2_FB21_Pos (21U)
8985 #define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)
8986 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk
8987 #define CAN_F13R2_FB22_Pos (22U)
8988 #define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)
8989 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk
8990 #define CAN_F13R2_FB23_Pos (23U)
8991 #define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)
8992 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk
8993 #define CAN_F13R2_FB24_Pos (24U)
8994 #define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)
8995 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk
8996 #define CAN_F13R2_FB25_Pos (25U)
8997 #define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)
8998 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk
8999 #define CAN_F13R2_FB26_Pos (26U)
9000 #define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)
9001 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk
9002 #define CAN_F13R2_FB27_Pos (27U)
9003 #define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)
9004 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk
9005 #define CAN_F13R2_FB28_Pos (28U)
9006 #define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)
9007 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk
9008 #define CAN_F13R2_FB29_Pos (29U)
9009 #define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)
9010 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk
9011 #define CAN_F13R2_FB30_Pos (30U)
9012 #define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)
9013 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk
9014 #define CAN_F13R2_FB31_Pos (31U)
9015 #define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)
9016 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk
9018 /******************************************************************************/
9019 /* */
9020 /* Serial Peripheral Interface */
9021 /* */
9022 /******************************************************************************/
9023 
9024 /******************* Bit definition for SPI_CR1 register ********************/
9025 #define SPI_CR1_CPHA_Pos (0U)
9026 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)
9027 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk
9028 #define SPI_CR1_CPOL_Pos (1U)
9029 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)
9030 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk
9031 #define SPI_CR1_MSTR_Pos (2U)
9032 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)
9033 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk
9035 #define SPI_CR1_BR_Pos (3U)
9036 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)
9037 #define SPI_CR1_BR SPI_CR1_BR_Msk
9038 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)
9039 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)
9040 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)
9042 #define SPI_CR1_SPE_Pos (6U)
9043 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
9044 #define SPI_CR1_SPE SPI_CR1_SPE_Msk
9045 #define SPI_CR1_LSBFIRST_Pos (7U)
9046 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)
9047 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk
9048 #define SPI_CR1_SSI_Pos (8U)
9049 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
9050 #define SPI_CR1_SSI SPI_CR1_SSI_Msk
9051 #define SPI_CR1_SSM_Pos (9U)
9052 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)
9053 #define SPI_CR1_SSM SPI_CR1_SSM_Msk
9054 #define SPI_CR1_RXONLY_Pos (10U)
9055 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)
9056 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk
9057 #define SPI_CR1_DFF_Pos (11U)
9058 #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)
9059 #define SPI_CR1_DFF SPI_CR1_DFF_Msk
9060 #define SPI_CR1_CRCNEXT_Pos (12U)
9061 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)
9062 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk
9063 #define SPI_CR1_CRCEN_Pos (13U)
9064 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)
9065 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk
9066 #define SPI_CR1_BIDIOE_Pos (14U)
9067 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)
9068 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk
9069 #define SPI_CR1_BIDIMODE_Pos (15U)
9070 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)
9071 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk
9073 /******************* Bit definition for SPI_CR2 register ********************/
9074 #define SPI_CR2_RXDMAEN_Pos (0U)
9075 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)
9076 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk
9077 #define SPI_CR2_TXDMAEN_Pos (1U)
9078 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)
9079 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk
9080 #define SPI_CR2_SSOE_Pos (2U)
9081 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)
9082 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk
9083 #define SPI_CR2_ERRIE_Pos (5U)
9084 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)
9085 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk
9086 #define SPI_CR2_RXNEIE_Pos (6U)
9087 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)
9088 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk
9089 #define SPI_CR2_TXEIE_Pos (7U)
9090 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)
9091 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk
9093 /******************** Bit definition for SPI_SR register ********************/
9094 #define SPI_SR_RXNE_Pos (0U)
9095 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)
9096 #define SPI_SR_RXNE SPI_SR_RXNE_Msk
9097 #define SPI_SR_TXE_Pos (1U)
9098 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)
9099 #define SPI_SR_TXE SPI_SR_TXE_Msk
9100 #define SPI_SR_CHSIDE_Pos (2U)
9101 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)
9102 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk
9103 #define SPI_SR_UDR_Pos (3U)
9104 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
9105 #define SPI_SR_UDR SPI_SR_UDR_Msk
9106 #define SPI_SR_CRCERR_Pos (4U)
9107 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)
9108 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk
9109 #define SPI_SR_MODF_Pos (5U)
9110 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
9111 #define SPI_SR_MODF SPI_SR_MODF_Msk
9112 #define SPI_SR_OVR_Pos (6U)
9113 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
9114 #define SPI_SR_OVR SPI_SR_OVR_Msk
9115 #define SPI_SR_BSY_Pos (7U)
9116 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)
9117 #define SPI_SR_BSY SPI_SR_BSY_Msk
9119 /******************** Bit definition for SPI_DR register ********************/
9120 #define SPI_DR_DR_Pos (0U)
9121 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)
9122 #define SPI_DR_DR SPI_DR_DR_Msk
9124 /******************* Bit definition for SPI_CRCPR register ******************/
9125 #define SPI_CRCPR_CRCPOLY_Pos (0U)
9126 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)
9127 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk
9129 /****************** Bit definition for SPI_RXCRCR register ******************/
9130 #define SPI_RXCRCR_RXCRC_Pos (0U)
9131 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)
9132 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk
9134 /****************** Bit definition for SPI_TXCRCR register ******************/
9135 #define SPI_TXCRCR_TXCRC_Pos (0U)
9136 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)
9137 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk
9139 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
9140 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
9141 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
9143 /******************************************************************************/
9144 /* */
9145 /* Inter-integrated Circuit Interface */
9146 /* */
9147 /******************************************************************************/
9148 
9149 /******************* Bit definition for I2C_CR1 register ********************/
9150 #define I2C_CR1_PE_Pos (0U)
9151 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
9152 #define I2C_CR1_PE I2C_CR1_PE_Msk
9153 #define I2C_CR1_SMBUS_Pos (1U)
9154 #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)
9155 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk
9156 #define I2C_CR1_SMBTYPE_Pos (3U)
9157 #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)
9158 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk
9159 #define I2C_CR1_ENARP_Pos (4U)
9160 #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)
9161 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk
9162 #define I2C_CR1_ENPEC_Pos (5U)
9163 #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)
9164 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk
9165 #define I2C_CR1_ENGC_Pos (6U)
9166 #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)
9167 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk
9168 #define I2C_CR1_NOSTRETCH_Pos (7U)
9169 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
9170 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
9171 #define I2C_CR1_START_Pos (8U)
9172 #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)
9173 #define I2C_CR1_START I2C_CR1_START_Msk
9174 #define I2C_CR1_STOP_Pos (9U)
9175 #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)
9176 #define I2C_CR1_STOP I2C_CR1_STOP_Msk
9177 #define I2C_CR1_ACK_Pos (10U)
9178 #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)
9179 #define I2C_CR1_ACK I2C_CR1_ACK_Msk
9180 #define I2C_CR1_POS_Pos (11U)
9181 #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)
9182 #define I2C_CR1_POS I2C_CR1_POS_Msk
9183 #define I2C_CR1_PEC_Pos (12U)
9184 #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)
9185 #define I2C_CR1_PEC I2C_CR1_PEC_Msk
9186 #define I2C_CR1_ALERT_Pos (13U)
9187 #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)
9188 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk
9189 #define I2C_CR1_SWRST_Pos (15U)
9190 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)
9191 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk
9193 /******************* Bit definition for I2C_CR2 register ********************/
9194 #define I2C_CR2_FREQ_Pos (0U)
9195 #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)
9196 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk
9197 #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)
9198 #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)
9199 #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)
9200 #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)
9201 #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)
9202 #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)
9204 #define I2C_CR2_ITERREN_Pos (8U)
9205 #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)
9206 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk
9207 #define I2C_CR2_ITEVTEN_Pos (9U)
9208 #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)
9209 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk
9210 #define I2C_CR2_ITBUFEN_Pos (10U)
9211 #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)
9212 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk
9213 #define I2C_CR2_DMAEN_Pos (11U)
9214 #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)
9215 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk
9216 #define I2C_CR2_LAST_Pos (12U)
9217 #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)
9218 #define I2C_CR2_LAST I2C_CR2_LAST_Msk
9220 /******************* Bit definition for I2C_OAR1 register *******************/
9221 #define I2C_OAR1_ADD1_7 0x000000FEU
9222 #define I2C_OAR1_ADD8_9 0x00000300U
9224 #define I2C_OAR1_ADD0_Pos (0U)
9225 #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)
9226 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk
9227 #define I2C_OAR1_ADD1_Pos (1U)
9228 #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)
9229 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk
9230 #define I2C_OAR1_ADD2_Pos (2U)
9231 #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)
9232 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk
9233 #define I2C_OAR1_ADD3_Pos (3U)
9234 #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)
9235 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk
9236 #define I2C_OAR1_ADD4_Pos (4U)
9237 #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)
9238 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk
9239 #define I2C_OAR1_ADD5_Pos (5U)
9240 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)
9241 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk
9242 #define I2C_OAR1_ADD6_Pos (6U)
9243 #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)
9244 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk
9245 #define I2C_OAR1_ADD7_Pos (7U)
9246 #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)
9247 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk
9248 #define I2C_OAR1_ADD8_Pos (8U)
9249 #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)
9250 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk
9251 #define I2C_OAR1_ADD9_Pos (9U)
9252 #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)
9253 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk
9255 #define I2C_OAR1_ADDMODE_Pos (15U)
9256 #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)
9257 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk
9259 /******************* Bit definition for I2C_OAR2 register *******************/
9260 #define I2C_OAR2_ENDUAL_Pos (0U)
9261 #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)
9262 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk
9263 #define I2C_OAR2_ADD2_Pos (1U)
9264 #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)
9265 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk
9267 /******************** Bit definition for I2C_DR register ********************/
9268 #define I2C_DR_DR_Pos (0U)
9269 #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)
9270 #define I2C_DR_DR I2C_DR_DR_Msk
9272 /******************* Bit definition for I2C_SR1 register ********************/
9273 #define I2C_SR1_SB_Pos (0U)
9274 #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)
9275 #define I2C_SR1_SB I2C_SR1_SB_Msk
9276 #define I2C_SR1_ADDR_Pos (1U)
9277 #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)
9278 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk
9279 #define I2C_SR1_BTF_Pos (2U)
9280 #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)
9281 #define I2C_SR1_BTF I2C_SR1_BTF_Msk
9282 #define I2C_SR1_ADD10_Pos (3U)
9283 #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)
9284 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk
9285 #define I2C_SR1_STOPF_Pos (4U)
9286 #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)
9287 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk
9288 #define I2C_SR1_RXNE_Pos (6U)
9289 #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)
9290 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk
9291 #define I2C_SR1_TXE_Pos (7U)
9292 #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)
9293 #define I2C_SR1_TXE I2C_SR1_TXE_Msk
9294 #define I2C_SR1_BERR_Pos (8U)
9295 #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)
9296 #define I2C_SR1_BERR I2C_SR1_BERR_Msk
9297 #define I2C_SR1_ARLO_Pos (9U)
9298 #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)
9299 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk
9300 #define I2C_SR1_AF_Pos (10U)
9301 #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)
9302 #define I2C_SR1_AF I2C_SR1_AF_Msk
9303 #define I2C_SR1_OVR_Pos (11U)
9304 #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)
9305 #define I2C_SR1_OVR I2C_SR1_OVR_Msk
9306 #define I2C_SR1_PECERR_Pos (12U)
9307 #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)
9308 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk
9309 #define I2C_SR1_TIMEOUT_Pos (14U)
9310 #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)
9311 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk
9312 #define I2C_SR1_SMBALERT_Pos (15U)
9313 #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)
9314 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk
9316 /******************* Bit definition for I2C_SR2 register ********************/
9317 #define I2C_SR2_MSL_Pos (0U)
9318 #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)
9319 #define I2C_SR2_MSL I2C_SR2_MSL_Msk
9320 #define I2C_SR2_BUSY_Pos (1U)
9321 #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)
9322 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk
9323 #define I2C_SR2_TRA_Pos (2U)
9324 #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)
9325 #define I2C_SR2_TRA I2C_SR2_TRA_Msk
9326 #define I2C_SR2_GENCALL_Pos (4U)
9327 #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)
9328 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk
9329 #define I2C_SR2_SMBDEFAULT_Pos (5U)
9330 #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)
9331 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk
9332 #define I2C_SR2_SMBHOST_Pos (6U)
9333 #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)
9334 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk
9335 #define I2C_SR2_DUALF_Pos (7U)
9336 #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)
9337 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk
9338 #define I2C_SR2_PEC_Pos (8U)
9339 #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)
9340 #define I2C_SR2_PEC I2C_SR2_PEC_Msk
9342 /******************* Bit definition for I2C_CCR register ********************/
9343 #define I2C_CCR_CCR_Pos (0U)
9344 #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)
9345 #define I2C_CCR_CCR I2C_CCR_CCR_Msk
9346 #define I2C_CCR_DUTY_Pos (14U)
9347 #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)
9348 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk
9349 #define I2C_CCR_FS_Pos (15U)
9350 #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)
9351 #define I2C_CCR_FS I2C_CCR_FS_Msk
9353 /****************** Bit definition for I2C_TRISE register *******************/
9354 #define I2C_TRISE_TRISE_Pos (0U)
9355 #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)
9356 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk
9358 /******************************************************************************/
9359 /* */
9360 /* Universal Synchronous Asynchronous Receiver Transmitter */
9361 /* */
9362 /******************************************************************************/
9363 
9364 /******************* Bit definition for USART_SR register *******************/
9365 #define USART_SR_PE_Pos (0U)
9366 #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)
9367 #define USART_SR_PE USART_SR_PE_Msk
9368 #define USART_SR_FE_Pos (1U)
9369 #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)
9370 #define USART_SR_FE USART_SR_FE_Msk
9371 #define USART_SR_NE_Pos (2U)
9372 #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)
9373 #define USART_SR_NE USART_SR_NE_Msk
9374 #define USART_SR_ORE_Pos (3U)
9375 #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)
9376 #define USART_SR_ORE USART_SR_ORE_Msk
9377 #define USART_SR_IDLE_Pos (4U)
9378 #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)
9379 #define USART_SR_IDLE USART_SR_IDLE_Msk
9380 #define USART_SR_RXNE_Pos (5U)
9381 #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)
9382 #define USART_SR_RXNE USART_SR_RXNE_Msk
9383 #define USART_SR_TC_Pos (6U)
9384 #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)
9385 #define USART_SR_TC USART_SR_TC_Msk
9386 #define USART_SR_TXE_Pos (7U)
9387 #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)
9388 #define USART_SR_TXE USART_SR_TXE_Msk
9389 #define USART_SR_LBD_Pos (8U)
9390 #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)
9391 #define USART_SR_LBD USART_SR_LBD_Msk
9392 #define USART_SR_CTS_Pos (9U)
9393 #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)
9394 #define USART_SR_CTS USART_SR_CTS_Msk
9396 /******************* Bit definition for USART_DR register *******************/
9397 #define USART_DR_DR_Pos (0U)
9398 #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)
9399 #define USART_DR_DR USART_DR_DR_Msk
9401 /****************** Bit definition for USART_BRR register *******************/
9402 #define USART_BRR_DIV_Fraction_Pos (0U)
9403 #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)
9404 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk
9405 #define USART_BRR_DIV_Mantissa_Pos (4U)
9406 #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)
9407 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk
9409 /****************** Bit definition for USART_CR1 register *******************/
9410 #define USART_CR1_SBK_Pos (0U)
9411 #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)
9412 #define USART_CR1_SBK USART_CR1_SBK_Msk
9413 #define USART_CR1_RWU_Pos (1U)
9414 #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)
9415 #define USART_CR1_RWU USART_CR1_RWU_Msk
9416 #define USART_CR1_RE_Pos (2U)
9417 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
9418 #define USART_CR1_RE USART_CR1_RE_Msk
9419 #define USART_CR1_TE_Pos (3U)
9420 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
9421 #define USART_CR1_TE USART_CR1_TE_Msk
9422 #define USART_CR1_IDLEIE_Pos (4U)
9423 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
9424 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
9425 #define USART_CR1_RXNEIE_Pos (5U)
9426 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)
9427 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk
9428 #define USART_CR1_TCIE_Pos (6U)
9429 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
9430 #define USART_CR1_TCIE USART_CR1_TCIE_Msk
9431 #define USART_CR1_TXEIE_Pos (7U)
9432 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)
9433 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk
9434 #define USART_CR1_PEIE_Pos (8U)
9435 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
9436 #define USART_CR1_PEIE USART_CR1_PEIE_Msk
9437 #define USART_CR1_PS_Pos (9U)
9438 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
9439 #define USART_CR1_PS USART_CR1_PS_Msk
9440 #define USART_CR1_PCE_Pos (10U)
9441 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
9442 #define USART_CR1_PCE USART_CR1_PCE_Msk
9443 #define USART_CR1_WAKE_Pos (11U)
9444 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
9445 #define USART_CR1_WAKE USART_CR1_WAKE_Msk
9446 #define USART_CR1_M_Pos (12U)
9447 #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)
9448 #define USART_CR1_M USART_CR1_M_Msk
9449 #define USART_CR1_UE_Pos (13U)
9450 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
9451 #define USART_CR1_UE USART_CR1_UE_Msk
9453 /****************** Bit definition for USART_CR2 register *******************/
9454 #define USART_CR2_ADD_Pos (0U)
9455 #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)
9456 #define USART_CR2_ADD USART_CR2_ADD_Msk
9457 #define USART_CR2_LBDL_Pos (5U)
9458 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
9459 #define USART_CR2_LBDL USART_CR2_LBDL_Msk
9460 #define USART_CR2_LBDIE_Pos (6U)
9461 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
9462 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
9463 #define USART_CR2_LBCL_Pos (8U)
9464 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
9465 #define USART_CR2_LBCL USART_CR2_LBCL_Msk
9466 #define USART_CR2_CPHA_Pos (9U)
9467 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
9468 #define USART_CR2_CPHA USART_CR2_CPHA_Msk
9469 #define USART_CR2_CPOL_Pos (10U)
9470 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
9471 #define USART_CR2_CPOL USART_CR2_CPOL_Msk
9472 #define USART_CR2_CLKEN_Pos (11U)
9473 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
9474 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
9476 #define USART_CR2_STOP_Pos (12U)
9477 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
9478 #define USART_CR2_STOP USART_CR2_STOP_Msk
9479 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
9480 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
9482 #define USART_CR2_LINEN_Pos (14U)
9483 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
9484 #define USART_CR2_LINEN USART_CR2_LINEN_Msk
9486 /****************** Bit definition for USART_CR3 register *******************/
9487 #define USART_CR3_EIE_Pos (0U)
9488 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
9489 #define USART_CR3_EIE USART_CR3_EIE_Msk
9490 #define USART_CR3_IREN_Pos (1U)
9491 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
9492 #define USART_CR3_IREN USART_CR3_IREN_Msk
9493 #define USART_CR3_IRLP_Pos (2U)
9494 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
9495 #define USART_CR3_IRLP USART_CR3_IRLP_Msk
9496 #define USART_CR3_HDSEL_Pos (3U)
9497 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
9498 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
9499 #define USART_CR3_NACK_Pos (4U)
9500 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
9501 #define USART_CR3_NACK USART_CR3_NACK_Msk
9502 #define USART_CR3_SCEN_Pos (5U)
9503 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
9504 #define USART_CR3_SCEN USART_CR3_SCEN_Msk
9505 #define USART_CR3_DMAR_Pos (6U)
9506 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
9507 #define USART_CR3_DMAR USART_CR3_DMAR_Msk
9508 #define USART_CR3_DMAT_Pos (7U)
9509 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
9510 #define USART_CR3_DMAT USART_CR3_DMAT_Msk
9511 #define USART_CR3_RTSE_Pos (8U)
9512 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
9513 #define USART_CR3_RTSE USART_CR3_RTSE_Msk
9514 #define USART_CR3_CTSE_Pos (9U)
9515 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
9516 #define USART_CR3_CTSE USART_CR3_CTSE_Msk
9517 #define USART_CR3_CTSIE_Pos (10U)
9518 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
9519 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
9521 /****************** Bit definition for USART_GTPR register ******************/
9522 #define USART_GTPR_PSC_Pos (0U)
9523 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
9524 #define USART_GTPR_PSC USART_GTPR_PSC_Msk
9525 #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)
9526 #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)
9527 #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)
9528 #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)
9529 #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)
9530 #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)
9531 #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)
9532 #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)
9534 #define USART_GTPR_GT_Pos (8U)
9535 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
9536 #define USART_GTPR_GT USART_GTPR_GT_Msk
9538 /******************************************************************************/
9539 /* */
9540 /* Debug MCU */
9541 /* */
9542 /******************************************************************************/
9543 
9544 /**************** Bit definition for DBGMCU_IDCODE register *****************/
9545 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
9546 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
9547 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
9549 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
9550 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
9551 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
9552 #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos)
9553 #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos)
9554 #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos)
9555 #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos)
9556 #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos)
9557 #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos)
9558 #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos)
9559 #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos)
9560 #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos)
9561 #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos)
9562 #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos)
9563 #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos)
9564 #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos)
9565 #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos)
9566 #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos)
9567 #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos)
9569 /****************** Bit definition for DBGMCU_CR register *******************/
9570 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
9571 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)
9572 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk
9573 #define DBGMCU_CR_DBG_STOP_Pos (1U)
9574 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)
9575 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk
9576 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
9577 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)
9578 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk
9579 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
9580 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)
9581 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk
9583 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
9584 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)
9585 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk
9586 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)
9587 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)
9589 #define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
9590 #define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos)
9591 #define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk
9592 #define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
9593 #define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos)
9594 #define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk
9595 #define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
9596 #define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM1_STOP_Pos)
9597 #define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk
9598 #define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
9599 #define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos)
9600 #define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk
9601 #define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
9602 #define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos)
9603 #define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk
9604 #define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
9605 #define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_CAN1_STOP_Pos)
9606 #define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk
9607 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
9608 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos)
9609 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk
9611 /******************************************************************************/
9612 /* */
9613 /* FLASH and Option Bytes Registers */
9614 /* */
9615 /******************************************************************************/
9616 /******************* Bit definition for FLASH_ACR register ******************/
9617 #define FLASH_ACR_LATENCY_Pos (0U)
9618 #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)
9619 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
9620 #define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos)
9621 #define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos)
9622 #define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos)
9624 #define FLASH_ACR_HLFCYA_Pos (3U)
9625 #define FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos)
9626 #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk
9627 #define FLASH_ACR_PRFTBE_Pos (4U)
9628 #define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos)
9629 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk
9630 #define FLASH_ACR_PRFTBS_Pos (5U)
9631 #define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos)
9632 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk
9634 /****************** Bit definition for FLASH_KEYR register ******************/
9635 #define FLASH_KEYR_FKEYR_Pos (0U)
9636 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos)
9637 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk
9639 #define RDP_KEY_Pos (0U)
9640 #define RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos)
9641 #define RDP_KEY RDP_KEY_Msk
9642 #define FLASH_KEY1_Pos (0U)
9643 #define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos)
9644 #define FLASH_KEY1 FLASH_KEY1_Msk
9645 #define FLASH_KEY2_Pos (0U)
9646 #define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos)
9647 #define FLASH_KEY2 FLASH_KEY2_Msk
9649 /***************** Bit definition for FLASH_OPTKEYR register ****************/
9650 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
9651 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos)
9652 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk
9654 #define FLASH_OPTKEY1 FLASH_KEY1
9655 #define FLASH_OPTKEY2 FLASH_KEY2
9657 /****************** Bit definition for FLASH_SR register ********************/
9658 #define FLASH_SR_BSY_Pos (0U)
9659 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
9660 #define FLASH_SR_BSY FLASH_SR_BSY_Msk
9661 #define FLASH_SR_PGERR_Pos (2U)
9662 #define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos)
9663 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk
9664 #define FLASH_SR_WRPRTERR_Pos (4U)
9665 #define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos)
9666 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk
9667 #define FLASH_SR_EOP_Pos (5U)
9668 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
9669 #define FLASH_SR_EOP FLASH_SR_EOP_Msk
9671 /******************* Bit definition for FLASH_CR register *******************/
9672 #define FLASH_CR_PG_Pos (0U)
9673 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
9674 #define FLASH_CR_PG FLASH_CR_PG_Msk
9675 #define FLASH_CR_PER_Pos (1U)
9676 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)
9677 #define FLASH_CR_PER FLASH_CR_PER_Msk
9678 #define FLASH_CR_MER_Pos (2U)
9679 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)
9680 #define FLASH_CR_MER FLASH_CR_MER_Msk
9681 #define FLASH_CR_OPTPG_Pos (4U)
9682 #define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos)
9683 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk
9684 #define FLASH_CR_OPTER_Pos (5U)
9685 #define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos)
9686 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk
9687 #define FLASH_CR_STRT_Pos (6U)
9688 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)
9689 #define FLASH_CR_STRT FLASH_CR_STRT_Msk
9690 #define FLASH_CR_LOCK_Pos (7U)
9691 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
9692 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
9693 #define FLASH_CR_OPTWRE_Pos (9U)
9694 #define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos)
9695 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk
9696 #define FLASH_CR_ERRIE_Pos (10U)
9697 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)
9698 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
9699 #define FLASH_CR_EOPIE_Pos (12U)
9700 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
9701 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
9703 /******************* Bit definition for FLASH_AR register *******************/
9704 #define FLASH_AR_FAR_Pos (0U)
9705 #define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos)
9706 #define FLASH_AR_FAR FLASH_AR_FAR_Msk
9708 /****************** Bit definition for FLASH_OBR register *******************/
9709 #define FLASH_OBR_OPTERR_Pos (0U)
9710 #define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos)
9711 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk
9712 #define FLASH_OBR_RDPRT_Pos (1U)
9713 #define FLASH_OBR_RDPRT_Msk (0x1UL << FLASH_OBR_RDPRT_Pos)
9714 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk
9716 #define FLASH_OBR_IWDG_SW_Pos (2U)
9717 #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos)
9718 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk
9719 #define FLASH_OBR_nRST_STOP_Pos (3U)
9720 #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos)
9721 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk
9722 #define FLASH_OBR_nRST_STDBY_Pos (4U)
9723 #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos)
9724 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk
9725 #define FLASH_OBR_USER_Pos (2U)
9726 #define FLASH_OBR_USER_Msk (0x7UL << FLASH_OBR_USER_Pos)
9727 #define FLASH_OBR_USER FLASH_OBR_USER_Msk
9728 #define FLASH_OBR_DATA0_Pos (10U)
9729 #define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos)
9730 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk
9731 #define FLASH_OBR_DATA1_Pos (18U)
9732 #define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos)
9733 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk
9735 /****************** Bit definition for FLASH_WRPR register ******************/
9736 #define FLASH_WRPR_WRP_Pos (0U)
9737 #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos)
9738 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk
9740 /*----------------------------------------------------------------------------*/
9741 
9742 /****************** Bit definition for FLASH_RDP register *******************/
9743 #define FLASH_RDP_RDP_Pos (0U)
9744 #define FLASH_RDP_RDP_Msk (0xFFUL << FLASH_RDP_RDP_Pos)
9745 #define FLASH_RDP_RDP FLASH_RDP_RDP_Msk
9746 #define FLASH_RDP_nRDP_Pos (8U)
9747 #define FLASH_RDP_nRDP_Msk (0xFFUL << FLASH_RDP_nRDP_Pos)
9748 #define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk
9750 /****************** Bit definition for FLASH_USER register ******************/
9751 #define FLASH_USER_USER_Pos (16U)
9752 #define FLASH_USER_USER_Msk (0xFFUL << FLASH_USER_USER_Pos)
9753 #define FLASH_USER_USER FLASH_USER_USER_Msk
9754 #define FLASH_USER_nUSER_Pos (24U)
9755 #define FLASH_USER_nUSER_Msk (0xFFUL << FLASH_USER_nUSER_Pos)
9756 #define FLASH_USER_nUSER FLASH_USER_nUSER_Msk
9758 /****************** Bit definition for FLASH_Data0 register *****************/
9759 #define FLASH_DATA0_DATA0_Pos (0U)
9760 #define FLASH_DATA0_DATA0_Msk (0xFFUL << FLASH_DATA0_DATA0_Pos)
9761 #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk
9762 #define FLASH_DATA0_nDATA0_Pos (8U)
9763 #define FLASH_DATA0_nDATA0_Msk (0xFFUL << FLASH_DATA0_nDATA0_Pos)
9764 #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk
9766 /****************** Bit definition for FLASH_Data1 register *****************/
9767 #define FLASH_DATA1_DATA1_Pos (16U)
9768 #define FLASH_DATA1_DATA1_Msk (0xFFUL << FLASH_DATA1_DATA1_Pos)
9769 #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk
9770 #define FLASH_DATA1_nDATA1_Pos (24U)
9771 #define FLASH_DATA1_nDATA1_Msk (0xFFUL << FLASH_DATA1_nDATA1_Pos)
9772 #define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk
9774 /****************** Bit definition for FLASH_WRP0 register ******************/
9775 #define FLASH_WRP0_WRP0_Pos (0U)
9776 #define FLASH_WRP0_WRP0_Msk (0xFFUL << FLASH_WRP0_WRP0_Pos)
9777 #define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk
9778 #define FLASH_WRP0_nWRP0_Pos (8U)
9779 #define FLASH_WRP0_nWRP0_Msk (0xFFUL << FLASH_WRP0_nWRP0_Pos)
9780 #define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk
9796 /****************************** ADC Instances *********************************/
9797 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
9798  ((INSTANCE) == ADC2))
9799 
9800 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
9801 
9802 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
9803 
9804 #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
9805 
9806 /****************************** CAN Instances *********************************/
9807 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
9808 
9809 /****************************** CRC Instances *********************************/
9810 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
9811 
9812 /****************************** DAC Instances *********************************/
9813 
9814 /****************************** DMA Instances *********************************/
9815 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
9816  ((INSTANCE) == DMA1_Channel2) || \
9817  ((INSTANCE) == DMA1_Channel3) || \
9818  ((INSTANCE) == DMA1_Channel4) || \
9819  ((INSTANCE) == DMA1_Channel5) || \
9820  ((INSTANCE) == DMA1_Channel6) || \
9821  ((INSTANCE) == DMA1_Channel7))
9822 
9823 /******************************* GPIO Instances *******************************/
9824 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
9825  ((INSTANCE) == GPIOB) || \
9826  ((INSTANCE) == GPIOC) || \
9827  ((INSTANCE) == GPIOD))
9828 
9829 /**************************** GPIO Alternate Function Instances ***************/
9830 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
9831 
9832 /**************************** GPIO Lock Instances *****************************/
9833 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
9834 
9835 /******************************** I2C Instances *******************************/
9836 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
9837 
9838 /******************************* SMBUS Instances ******************************/
9839 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
9840 
9841 /****************************** IWDG Instances ********************************/
9842 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
9843 
9844 /******************************** SPI Instances *******************************/
9845 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
9846 
9847 /****************************** START TIM Instances ***************************/
9848 /****************************** TIM Instances *********************************/
9849 #define IS_TIM_INSTANCE(INSTANCE)\
9850  (((INSTANCE) == TIM1) || \
9851  ((INSTANCE) == TIM2) || \
9852  ((INSTANCE) == TIM3))
9853 
9854 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
9855 
9856 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
9857  (((INSTANCE) == TIM1) || \
9858  ((INSTANCE) == TIM2) || \
9859  ((INSTANCE) == TIM3))
9860 
9861 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
9862  (((INSTANCE) == TIM1) || \
9863  ((INSTANCE) == TIM2) || \
9864  ((INSTANCE) == TIM3))
9865 
9866 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
9867  (((INSTANCE) == TIM1) || \
9868  ((INSTANCE) == TIM2) || \
9869  ((INSTANCE) == TIM3))
9870 
9871 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
9872  (((INSTANCE) == TIM1) || \
9873  ((INSTANCE) == TIM2) || \
9874  ((INSTANCE) == TIM3))
9875 
9876 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
9877  (((INSTANCE) == TIM1) || \
9878  ((INSTANCE) == TIM2) || \
9879  ((INSTANCE) == TIM3))
9880 
9881 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
9882  (((INSTANCE) == TIM1) || \
9883  ((INSTANCE) == TIM2) || \
9884  ((INSTANCE) == TIM3))
9885 
9886 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
9887  (((INSTANCE) == TIM1) || \
9888  ((INSTANCE) == TIM2) || \
9889  ((INSTANCE) == TIM3))
9890 
9891 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
9892  (((INSTANCE) == TIM1) || \
9893  ((INSTANCE) == TIM2) || \
9894  ((INSTANCE) == TIM3))
9895 
9896 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
9897  (((INSTANCE) == TIM1) || \
9898  ((INSTANCE) == TIM2) || \
9899  ((INSTANCE) == TIM3))
9900 
9901 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
9902  (((INSTANCE) == TIM1) || \
9903  ((INSTANCE) == TIM2) || \
9904  ((INSTANCE) == TIM3))
9905 
9906 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
9907  (((INSTANCE) == TIM1) || \
9908  ((INSTANCE) == TIM2) || \
9909  ((INSTANCE) == TIM3))
9910 
9911 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
9912  (((INSTANCE) == TIM1) || \
9913  ((INSTANCE) == TIM2) || \
9914  ((INSTANCE) == TIM3))
9915 
9916 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
9917  (((INSTANCE) == TIM1) || \
9918  ((INSTANCE) == TIM2) || \
9919  ((INSTANCE) == TIM3))
9920 
9921 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
9922  (((INSTANCE) == TIM1) || \
9923  ((INSTANCE) == TIM2) || \
9924  ((INSTANCE) == TIM3))
9925 
9926 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
9927  ((INSTANCE) == TIM1)
9928 
9929 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
9930  ((((INSTANCE) == TIM1) && \
9931  (((CHANNEL) == TIM_CHANNEL_1) || \
9932  ((CHANNEL) == TIM_CHANNEL_2) || \
9933  ((CHANNEL) == TIM_CHANNEL_3) || \
9934  ((CHANNEL) == TIM_CHANNEL_4))) \
9935  || \
9936  (((INSTANCE) == TIM2) && \
9937  (((CHANNEL) == TIM_CHANNEL_1) || \
9938  ((CHANNEL) == TIM_CHANNEL_2) || \
9939  ((CHANNEL) == TIM_CHANNEL_3) || \
9940  ((CHANNEL) == TIM_CHANNEL_4))) \
9941  || \
9942  (((INSTANCE) == TIM3) && \
9943  (((CHANNEL) == TIM_CHANNEL_1) || \
9944  ((CHANNEL) == TIM_CHANNEL_2) || \
9945  ((CHANNEL) == TIM_CHANNEL_3) || \
9946  ((CHANNEL) == TIM_CHANNEL_4))))
9947 
9948 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
9949  (((INSTANCE) == TIM1) && \
9950  (((CHANNEL) == TIM_CHANNEL_1) || \
9951  ((CHANNEL) == TIM_CHANNEL_2) || \
9952  ((CHANNEL) == TIM_CHANNEL_3)))
9953 
9954 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
9955  (((INSTANCE) == TIM1) || \
9956  ((INSTANCE) == TIM2) || \
9957  ((INSTANCE) == TIM3))
9958 
9959 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
9960  ((INSTANCE) == TIM1)
9961 
9962 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
9963  (((INSTANCE) == TIM1) || \
9964  ((INSTANCE) == TIM2) || \
9965  ((INSTANCE) == TIM3))
9966 
9967 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
9968  (((INSTANCE) == TIM1) || \
9969  ((INSTANCE) == TIM2) || \
9970  ((INSTANCE) == TIM3))
9971 
9972 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
9973  (((INSTANCE) == TIM1) || \
9974  ((INSTANCE) == TIM2) || \
9975  ((INSTANCE) == TIM3))
9976 
9977 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
9978  ((INSTANCE) == TIM1)
9979 
9980 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9981  ((INSTANCE) == TIM2) || \
9982  ((INSTANCE) == TIM3))
9983 
9984 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
9985  ((INSTANCE) == TIM2) || \
9986  ((INSTANCE) == TIM3))
9987 
9988 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
9989 
9990 /****************************** END TIM Instances *****************************/
9991 
9992 
9993 /******************** USART Instances : Synchronous mode **********************/
9994 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9995  ((INSTANCE) == USART2))
9996 
9997 /******************** UART Instances : Asynchronous mode **********************/
9998 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9999  ((INSTANCE) == USART2) )
10000 
10001 /******************** UART Instances : Half-Duplex mode **********************/
10002 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10003  ((INSTANCE) == USART2) )
10004 
10005 /******************** UART Instances : LIN mode **********************/
10006 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10007  ((INSTANCE) == USART2) )
10008 
10009 /****************** UART Instances : Hardware Flow control ********************/
10010 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10011  ((INSTANCE) == USART2) )
10012 
10013 /********************* UART Instances : Smard card mode ***********************/
10014 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10015  ((INSTANCE) == USART2) )
10016 
10017 /*********************** UART Instances : IRDA mode ***************************/
10018 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10019  ((INSTANCE) == USART2) )
10020 
10021 /***************** UART Instances : Multi-Processor mode **********************/
10022 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10023  ((INSTANCE) == USART2) )
10024 
10025 /***************** UART Instances : DMA mode available **********************/
10026 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10027  ((INSTANCE) == USART2))
10028 
10029 /****************************** RTC Instances *********************************/
10030 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
10031 
10032 /**************************** WWDG Instances *****************************/
10033 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
10034 
10035 /****************************** USB Instances ********************************/
10036 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
10037 
10038 
10039 
10040 #define RCC_HSE_MIN 4000000U
10041 #define RCC_HSE_MAX 16000000U
10042 
10043 #define RCC_MAX_FREQUENCY 72000000U
10044 
10048 /******************************************************************************/
10049 /* For a painless codes migration between the STM32F1xx device product */
10050 /* lines, the aliases defined below are put in place to overcome the */
10051 /* differences in the interrupt handlers and IRQn definitions. */
10052 /* No need to update developed interrupt code when moving across */
10053 /* product lines within the same STM32F1 Family */
10054 /******************************************************************************/
10055 
10056 /* Aliases for __IRQn */
10057 #define ADC1_IRQn ADC1_2_IRQn
10058 #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
10059 #define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
10060 #define TIM9_IRQn TIM1_BRK_IRQn
10061 #define TIM11_IRQn TIM1_TRG_COM_IRQn
10062 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
10063 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
10064 #define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
10065 #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
10066 #define TIM10_IRQn TIM1_UP_IRQn
10067 #define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
10068 #define CEC_IRQn USBWakeUp_IRQn
10069 #define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
10070 #define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
10071 #define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
10072 #define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
10073 
10074 
10075 /* Aliases for __IRQHandler */
10076 #define ADC1_IRQHandler ADC1_2_IRQHandler
10077 #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
10078 #define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
10079 #define TIM9_IRQHandler TIM1_BRK_IRQHandler
10080 #define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
10081 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
10082 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
10083 #define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
10084 #define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
10085 #define TIM10_IRQHandler TIM1_UP_IRQHandler
10086 #define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
10087 #define CEC_IRQHandler USBWakeUp_IRQHandler
10088 #define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
10089 #define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
10090 #define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
10091 #define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
10092 
10093 
10103 #ifdef __cplusplus
10104  }
10105 #endif /* __cplusplus */
10106 
10107 #endif /* __STM32F103x6_H */
10108 
10109 
10110 
10111  /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
HardFault_IRQn
Definition: stm32f103x6.h:73
USB_TypeDef::CNTR
__IO uint16_t CNTR
Definition: stm32f103x6.h:535
DMA1_Channel2_IRQn
Definition: stm32f103x6.h:95
USB_TypeDef::EP0R
__IO uint16_t EP0R
Definition: stm32f103x6.h:519
PVD_IRQn
Definition: stm32f103x6.h:84
CRC_TypeDef
CRC calculation unit.
Definition: stm32f103x6.h:262
USB_TypeDef::EP2R
__IO uint16_t EP2R
Definition: stm32f103x6.h:523
TIM_TypeDef::SR
__IO uint32_t SR
Definition: stm32f103x6.h:478
TIM1_UP_IRQn
Definition: stm32f103x6.h:108
TIM_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f103x6.h:474
USB_TypeDef::RESERVED2
__IO uint16_t RESERVED2
Definition: stm32f103x6.h:524
USB_TypeDef::EP1R
__IO uint16_t EP1R
Definition: stm32f103x6.h:521
DMA1_Channel6_IRQn
Definition: stm32f103x6.h:99
DMA1_Channel1_IRQn
Definition: stm32f103x6.h:94
DebugMonitor_IRQn
Definition: stm32f103x6.h:78
BKP_TypeDef
Backup Registers.
Definition: stm32f103x6.h:176
TIM_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f103x6.h:475
USB_TypeDef::FNR
__IO uint16_t FNR
Definition: stm32f103x6.h:539
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f103x6.h:502
PendSV_IRQn
Definition: stm32f103x6.h:79
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32f103x6.h:139
USB_TypeDef::EP3R
__IO uint16_t EP3R
Definition: stm32f103x6.h:525
USART_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f103x6.h:508
USART_TypeDef::CR3
__IO uint32_t CR3
Definition: stm32f103x6.h:509
FLASH_TypeDef
FLASH Registers.
Definition: stm32f103x6.h:320
USB_TypeDef::RESERVED6
__IO uint16_t RESERVED6
Definition: stm32f103x6.h:532
I2C1_EV_IRQn
Definition: stm32f103x6.h:113
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f103x6.h:210
FLASH_IRQn
Definition: stm32f103x6.h:87
USB_TypeDef::EP5R
__IO uint16_t EP5R
Definition: stm32f103x6.h:529
AFIO_TypeDef
Alternate Function I/O.
Definition: stm32f103x6.h:368
CRC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f103x6.h:264
USB_TypeDef
Universal Serial Bus Full Speed Device.
Definition: stm32f103x6.h:517
USB_LP_CAN1_RX0_IRQn
Definition: stm32f103x6.h:103
RTC_TypeDef
Real-Time Clock.
Definition: stm32f103x6.h:439
USB_TypeDef::EP6R
__IO uint16_t EP6R
Definition: stm32f103x6.h:531
USB_TypeDef::RESERVED5
__IO uint16_t RESERVED5
Definition: stm32f103x6.h:530
DMA1_Channel7_IRQn
Definition: stm32f103x6.h:100
WWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f103x6.h:556
SysTick_IRQn
Definition: stm32f103x6.h:80
USB_TypeDef::RESERVED3
__IO uint16_t RESERVED3
Definition: stm32f103x6.h:526
TIM1_BRK_IRQn
Definition: stm32f103x6.h:107
TIM_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32f103x6.h:492
USB_TypeDef::RESERVEDC
__IO uint16_t RESERVEDC
Definition: stm32f103x6.h:544
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f103x6.h:457
EXTI15_10_IRQn
Definition: stm32f103x6.h:118
USB_TypeDef::RESERVEDB
__IO uint16_t RESERVEDB
Definition: stm32f103x6.h:542
EXTI2_IRQn
Definition: stm32f103x6.h:91
USB_TypeDef::RESERVED4
__IO uint16_t RESERVED4
Definition: stm32f103x6.h:528
CAN1_SCE_IRQn
Definition: stm32f103x6.h:105
WWDG_IRQn
Definition: stm32f103x6.h:83
UsageFault_IRQn
Definition: stm32f103x6.h:76
core_cm3.h
CMSIS Cortex-M3 Core Peripheral Access Layer Header File.
TIM_TypeDef::DMAR
__IO uint32_t DMAR
Definition: stm32f103x6.h:493
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f103x6.h:306
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f103x6.h:276
IWDG_TypeDef::KR
__IO uint32_t KR
Definition: stm32f103x6.h:399
IWDG_TypeDef::PR
__IO uint32_t PR
Definition: stm32f103x6.h:400
USART_TypeDef::GTPR
__IO uint32_t GTPR
Definition: stm32f103x6.h:510
CRC_TypeDef::IDR
__IO uint8_t IDR
Definition: stm32f103x6.h:265
USB_TypeDef::BTABLE
__IO uint16_t BTABLE
Definition: stm32f103x6.h:543
TIM1_CC_IRQn
Definition: stm32f103x6.h:110
TIM_TypeDef::CCR3
__IO uint32_t CCR3
Definition: stm32f103x6.h:489
USB_TypeDef::EP4R
__IO uint16_t EP4R
Definition: stm32f103x6.h:527
USART_TypeDef::SR
__IO uint32_t SR
Definition: stm32f103x6.h:504
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f103x6.h:353
TIM_TypeDef::PSC
__IO uint32_t PSC
Definition: stm32f103x6.h:484
USB_TypeDef::RESERVED9
__IO uint16_t RESERVED9
Definition: stm32f103x6.h:538
TIM_TypeDef::RCR
__IO uint32_t RCR
Definition: stm32f103x6.h:486
TIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32f103x6.h:483
CRC_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f103x6.h:267
USB_TypeDef::RESERVED1
__IO uint16_t RESERVED1
Definition: stm32f103x6.h:522
MemoryManagement_IRQn
Definition: stm32f103x6.h:74
__IO
#define __IO
Definition: core_armv8mbl.h:196
WWDG_TypeDef::CFR
__IO uint32_t CFR
Definition: stm32f103x6.h:555
ADC_Common_TypeDef::SR
__IO uint32_t SR
Definition: stm32f103x6.h:165
RCC_IRQn
Definition: stm32f103x6.h:88
USART_TypeDef::DR
__IO uint32_t DR
Definition: stm32f103x6.h:505
DMA1_Channel3_IRQn
Definition: stm32f103x6.h:96
DMA1_Channel5_IRQn
Definition: stm32f103x6.h:98
TIM_TypeDef::EGR
__IO uint32_t EGR
Definition: stm32f103x6.h:479
TIM_TypeDef::CCMR2
__IO uint32_t CCMR2
Definition: stm32f103x6.h:481
ADC_Common_TypeDef
Definition: stm32f103x6.h:163
USB_TypeDef::RESERVED0
__IO uint16_t RESERVED0
Definition: stm32f103x6.h:520
ADC_Common_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f103x6.h:166
SPI1_IRQn
Definition: stm32f103x6.h:115
CRC_TypeDef::RESERVED0
uint8_t RESERVED0
Definition: stm32f103x6.h:266
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f103x6.h:397
TIM_TypeDef::OR
__IO uint32_t OR
Definition: stm32f103x6.h:494
TIM_TypeDef::CCER
__IO uint32_t CCER
Definition: stm32f103x6.h:482
IWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f103x6.h:402
IRQn_Type
IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f103x6.h:69
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f103x6.h:552
TIM_TypeDef::CCMR1
__IO uint32_t CCMR1
Definition: stm32f103x6.h:480
USB_TypeDef::EP7R
__IO uint16_t EP7R
Definition: stm32f103x6.h:533
USB_TypeDef::ISTR
__IO uint16_t ISTR
Definition: stm32f103x6.h:537
EXTI0_IRQn
Definition: stm32f103x6.h:89
USART_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f103x6.h:507
I2C1_ER_IRQn
Definition: stm32f103x6.h:114
USBWakeUp_IRQn
Definition: stm32f103x6.h:120
TIM_TypeDef
TIM Timers.
Definition: stm32f103x6.h:472
EXTI9_5_IRQn
Definition: stm32f103x6.h:106
BusFault_IRQn
Definition: stm32f103x6.h:75
RTC_Alarm_IRQn
Definition: stm32f103x6.h:119
USART2_IRQn
Definition: stm32f103x6.h:117
DMA_TypeDef
Definition: stm32f103x6.h:294
TIM_TypeDef::DIER
__IO uint32_t DIER
Definition: stm32f103x6.h:477
TAMPER_IRQn
Definition: stm32f103x6.h:85
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f103x6.h:222
PWR_TypeDef
Power Control.
Definition: stm32f103x6.h:409
USB_HP_CAN1_TX_IRQn
Definition: stm32f103x6.h:102
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f103x6.h:419
DMA_Channel_TypeDef
DMA Controller.
Definition: stm32f103x6.h:286
TIM_TypeDef::CCR2
__IO uint32_t CCR2
Definition: stm32f103x6.h:488
EXTI1_IRQn
Definition: stm32f103x6.h:90
USART_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32f103x6.h:506
USB_TypeDef::RESERVED8
__IO uint16_t RESERVED8
Definition: stm32f103x6.h:536
CAN_TypeDef
Controller Area Network.
Definition: stm32f103x6.h:232
ADC1_2_IRQn
Definition: stm32f103x6.h:101
TIM3_IRQn
Definition: stm32f103x6.h:112
IWDG_TypeDef::RLR
__IO uint32_t RLR
Definition: stm32f103x6.h:401
TIM_TypeDef::CCR4
__IO uint32_t CCR4
Definition: stm32f103x6.h:490
EXTI3_IRQn
Definition: stm32f103x6.h:92
TIM_TypeDef::SMCR
__IO uint32_t SMCR
Definition: stm32f103x6.h:476
I2C_TypeDef
Inter Integrated Circuit Interface.
Definition: stm32f103x6.h:380
DMA1_Channel4_IRQn
Definition: stm32f103x6.h:97
EXTI4_IRQn
Definition: stm32f103x6.h:93
RTC_IRQn
Definition: stm32f103x6.h:86
TIM1_TRG_COM_IRQn
Definition: stm32f103x6.h:109
WWDG_TypeDef::CR
__IO uint32_t CR
Definition: stm32f103x6.h:554
NonMaskableInt_IRQn
Definition: stm32f103x6.h:72
CRC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f103x6.h:268
CAN1_RX1_IRQn
Definition: stm32f103x6.h:104
TIM_TypeDef::BDTR
__IO uint32_t BDTR
Definition: stm32f103x6.h:491
USB_TypeDef::DADDR
__IO uint16_t DADDR
Definition: stm32f103x6.h:541
ADC_Common_TypeDef::DR
__IO uint32_t DR
Definition: stm32f103x6.h:169
USB_TypeDef::RESERVEDA
__IO uint16_t RESERVEDA
Definition: stm32f103x6.h:540
TIM_TypeDef::CCR1
__IO uint32_t CCR1
Definition: stm32f103x6.h:487
USART1_IRQn
Definition: stm32f103x6.h:116
OB_TypeDef
Option Bytes Registers.
Definition: stm32f103x6.h:337
TIM2_IRQn
Definition: stm32f103x6.h:111
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f103x6.h:198
TIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32f103x6.h:485
SVCall_IRQn
Definition: stm32f103x6.h:77
ADC_Common_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f103x6.h:167
Generated by   doxygen 1.8.13