mastering_embedded_systems_diploma
stm32f1xx_hal_tim.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32F1xx_HAL_TIM_H
22 #define STM32F1xx_HAL_TIM_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f1xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
47 typedef struct
48 {
49  uint32_t Prescaler;
52  uint32_t CounterMode;
55  uint32_t Period;
59  uint32_t ClockDivision;
62  uint32_t RepetitionCounter;
73  uint32_t AutoReloadPreload;
75 } TIM_Base_InitTypeDef;
76 
80 typedef struct
81 {
82  uint32_t OCMode;
85  uint32_t Pulse;
88  uint32_t OCPolarity;
91  uint32_t OCNPolarity;
95  uint32_t OCFastMode;
100  uint32_t OCIdleState;
104  uint32_t OCNIdleState;
107 } TIM_OC_InitTypeDef;
108 
112 typedef struct
113 {
114  uint32_t OCMode;
117  uint32_t Pulse;
120  uint32_t OCPolarity;
123  uint32_t OCNPolarity;
127  uint32_t OCIdleState;
131  uint32_t OCNIdleState;
135  uint32_t ICPolarity;
138  uint32_t ICSelection;
141  uint32_t ICFilter;
143 } TIM_OnePulse_InitTypeDef;
144 
148 typedef struct
149 {
150  uint32_t ICPolarity;
153  uint32_t ICSelection;
156  uint32_t ICPrescaler;
159  uint32_t ICFilter;
161 } TIM_IC_InitTypeDef;
162 
166 typedef struct
167 {
168  uint32_t EncoderMode;
171  uint32_t IC1Polarity;
174  uint32_t IC1Selection;
177  uint32_t IC1Prescaler;
180  uint32_t IC1Filter;
183  uint32_t IC2Polarity;
186  uint32_t IC2Selection;
189  uint32_t IC2Prescaler;
192  uint32_t IC2Filter;
194 } TIM_Encoder_InitTypeDef;
195 
199 typedef struct
200 {
201  uint32_t ClockSource;
203  uint32_t ClockPolarity;
205  uint32_t ClockPrescaler;
207  uint32_t ClockFilter;
209 } TIM_ClockConfigTypeDef;
210 
214 typedef struct
215 {
216  uint32_t ClearInputState;
218  uint32_t ClearInputSource;
220  uint32_t ClearInputPolarity;
222  uint32_t ClearInputPrescaler;
225  uint32_t ClearInputFilter;
227 } TIM_ClearInputConfigTypeDef;
228 
232 typedef struct
233 {
234  uint32_t MasterOutputTrigger;
236  uint32_t MasterSlaveMode;
243 } TIM_MasterConfigTypeDef;
244 
248 typedef struct
249 {
250  uint32_t SlaveMode;
252  uint32_t InputTrigger;
254  uint32_t TriggerPolarity;
256  uint32_t TriggerPrescaler;
258  uint32_t TriggerFilter;
261 } TIM_SlaveConfigTypeDef;
262 
268 typedef struct
269 {
270  uint32_t OffStateRunMode;
272  uint32_t OffStateIDLEMode;
274  uint32_t LockLevel;
276  uint32_t DeadTime;
278  uint32_t BreakState;
280  uint32_t BreakPolarity;
282  uint32_t BreakFilter;
284  uint32_t AutomaticOutput;
286 } TIM_BreakDeadTimeConfigTypeDef;
287 
291 typedef enum
292 {
293  HAL_TIM_STATE_RESET = 0x00U,
294  HAL_TIM_STATE_READY = 0x01U,
295  HAL_TIM_STATE_BUSY = 0x02U,
296  HAL_TIM_STATE_TIMEOUT = 0x03U,
297  HAL_TIM_STATE_ERROR = 0x04U
298 } HAL_TIM_StateTypeDef;
299 
303 typedef enum
304 {
305  HAL_TIM_CHANNEL_STATE_RESET = 0x00U,
306  HAL_TIM_CHANNEL_STATE_READY = 0x01U,
307  HAL_TIM_CHANNEL_STATE_BUSY = 0x02U,
308 } HAL_TIM_ChannelStateTypeDef;
309 
313 typedef enum
314 {
315  HAL_DMA_BURST_STATE_RESET = 0x00U,
316  HAL_DMA_BURST_STATE_READY = 0x01U,
317  HAL_DMA_BURST_STATE_BUSY = 0x02U,
318 } HAL_TIM_DMABurstStateTypeDef;
319 
323 typedef enum
324 {
325  HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
326  HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
327  HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
328  HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
329  HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
330 } HAL_TIM_ActiveChannel;
331 
335 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
336 typedef struct __TIM_HandleTypeDef
337 #else
338 typedef struct
339 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
340 {
341  TIM_TypeDef *Instance;
342  TIM_Base_InitTypeDef Init;
343  HAL_TIM_ActiveChannel Channel;
344  DMA_HandleTypeDef *hdma[7];
346  HAL_LockTypeDef Lock;
347  __IO HAL_TIM_StateTypeDef State;
348  __IO HAL_TIM_ChannelStateTypeDef ChannelState[4];
349  __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4];
350  __IO HAL_TIM_DMABurstStateTypeDef DMABurstState;
352 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
353  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
354  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
355  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
356  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
357  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
358  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
359  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
360  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
361  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
362  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
363  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
364  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
365  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
366  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
367  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);
368  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
369  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);
370  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
371  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);
372  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
373  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);
374  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);
375  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
376  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);
377  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);
378  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
379  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);
380 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
381 } TIM_HandleTypeDef;
382 
383 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
384 
387 typedef enum
388 {
389  HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U
390  , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U
391  , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U
392  , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U
393  , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U
394  , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U
395  , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U
396  , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U
397  , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U
398  , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U
399  , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU
400  , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU
401  , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU
402  , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU
403  , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU
404  , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU
405  , HAL_TIM_TRIGGER_CB_ID = 0x10U
406  , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U
408  , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U
409  , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U
410  , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U
411  , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U
412  , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U
413  , HAL_TIM_ERROR_CB_ID = 0x17U
414  , HAL_TIM_COMMUTATION_CB_ID = 0x18U
415  , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U
416  , HAL_TIM_BREAK_CB_ID = 0x1AU
417 } HAL_TIM_CallbackIDTypeDef;
418 
422 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);
424 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
425 
429 /* End of exported types -----------------------------------------------------*/
430 
431 /* Exported constants --------------------------------------------------------*/
439 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
440 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
448 #define TIM_DMABASE_CR1 0x00000000U
449 #define TIM_DMABASE_CR2 0x00000001U
450 #define TIM_DMABASE_SMCR 0x00000002U
451 #define TIM_DMABASE_DIER 0x00000003U
452 #define TIM_DMABASE_SR 0x00000004U
453 #define TIM_DMABASE_EGR 0x00000005U
454 #define TIM_DMABASE_CCMR1 0x00000006U
455 #define TIM_DMABASE_CCMR2 0x00000007U
456 #define TIM_DMABASE_CCER 0x00000008U
457 #define TIM_DMABASE_CNT 0x00000009U
458 #define TIM_DMABASE_PSC 0x0000000AU
459 #define TIM_DMABASE_ARR 0x0000000BU
460 #define TIM_DMABASE_RCR 0x0000000CU
461 #define TIM_DMABASE_CCR1 0x0000000DU
462 #define TIM_DMABASE_CCR2 0x0000000EU
463 #define TIM_DMABASE_CCR3 0x0000000FU
464 #define TIM_DMABASE_CCR4 0x00000010U
465 #define TIM_DMABASE_BDTR 0x00000011U
466 #define TIM_DMABASE_DCR 0x00000012U
467 #define TIM_DMABASE_DMAR 0x00000013U
468 
475 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
476 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
477 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
478 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
479 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
480 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
481 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
482 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
490 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
491 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P
492 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
500 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP
501 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U
509 #define TIM_ETRPRESCALER_DIV1 0x00000000U
510 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0
511 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1
512 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS
520 #define TIM_COUNTERMODE_UP 0x00000000U
521 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
522 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
523 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
524 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
532 #define TIM_CLOCKDIVISION_DIV1 0x00000000U
533 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
534 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
542 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U
543 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E
551 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U
552 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE
561 #define TIM_OCFAST_DISABLE 0x00000000U
562 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE
570 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U
571 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE
579 #define TIM_OCPOLARITY_HIGH 0x00000000U
580 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P
588 #define TIM_OCNPOLARITY_HIGH 0x00000000U
589 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP
597 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1
598 #define TIM_OCIDLESTATE_RESET 0x00000000U
606 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N
607 #define TIM_OCNIDLESTATE_RESET 0x00000000U
615 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
616 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
617 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
625 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
626 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
634 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0
635 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1
636 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S
644 #define TIM_ICPSC_DIV1 0x00000000U
645 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0
646 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1
647 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC
655 #define TIM_OPMODE_SINGLE TIM_CR1_OPM
656 #define TIM_OPMODE_REPETITIVE 0x00000000U
664 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0
665 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1
666 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
674 #define TIM_IT_UPDATE TIM_DIER_UIE
675 #define TIM_IT_CC1 TIM_DIER_CC1IE
676 #define TIM_IT_CC2 TIM_DIER_CC2IE
677 #define TIM_IT_CC3 TIM_DIER_CC3IE
678 #define TIM_IT_CC4 TIM_DIER_CC4IE
679 #define TIM_IT_COM TIM_DIER_COMIE
680 #define TIM_IT_TRIGGER TIM_DIER_TIE
681 #define TIM_IT_BREAK TIM_DIER_BIE
689 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS
690 #define TIM_COMMUTATION_SOFTWARE 0x00000000U
698 #define TIM_DMA_UPDATE TIM_DIER_UDE
699 #define TIM_DMA_CC1 TIM_DIER_CC1DE
700 #define TIM_DMA_CC2 TIM_DIER_CC2DE
701 #define TIM_DMA_CC3 TIM_DIER_CC3DE
702 #define TIM_DMA_CC4 TIM_DIER_CC4DE
703 #define TIM_DMA_COM TIM_DIER_COMDE
704 #define TIM_DMA_TRIGGER TIM_DIER_TDE
712 #define TIM_FLAG_UPDATE TIM_SR_UIF
713 #define TIM_FLAG_CC1 TIM_SR_CC1IF
714 #define TIM_FLAG_CC2 TIM_SR_CC2IF
715 #define TIM_FLAG_CC3 TIM_SR_CC3IF
716 #define TIM_FLAG_CC4 TIM_SR_CC4IF
717 #define TIM_FLAG_COM TIM_SR_COMIF
718 #define TIM_FLAG_TRIGGER TIM_SR_TIF
719 #define TIM_FLAG_BREAK TIM_SR_BIF
720 #define TIM_FLAG_CC1OF TIM_SR_CC1OF
721 #define TIM_FLAG_CC2OF TIM_SR_CC2OF
722 #define TIM_FLAG_CC3OF TIM_SR_CC3OF
723 #define TIM_FLAG_CC4OF TIM_SR_CC4OF
731 #define TIM_CHANNEL_1 0x00000000U
732 #define TIM_CHANNEL_2 0x00000004U
733 #define TIM_CHANNEL_3 0x00000008U
734 #define TIM_CHANNEL_4 0x0000000CU
735 #define TIM_CHANNEL_ALL 0x0000003CU
743 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1
744 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0
745 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0
746 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1
747 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2
748 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3
749 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED
750 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1
751 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2
752 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF
760 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
761 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
762 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
763 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
764 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
772 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
773 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
774 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
775 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
783 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
784 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
792 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
793 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
794 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
795 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
803 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR
804 #define TIM_OSSR_DISABLE 0x00000000U
812 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI
813 #define TIM_OSSI_DISABLE 0x00000000U
820 #define TIM_LOCKLEVEL_OFF 0x00000000U
821 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
822 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
823 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
831 #define TIM_BREAK_ENABLE TIM_BDTR_BKE
832 #define TIM_BREAK_DISABLE 0x00000000U
840 #define TIM_BREAKPOLARITY_LOW 0x00000000U
841 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP
849 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
850 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
858 #define TIM_TRGO_RESET 0x00000000U
859 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0
860 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1
861 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
862 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2
863 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
864 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
865 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
873 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM
874 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
882 #define TIM_SLAVEMODE_DISABLE 0x00000000U
883 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
884 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
885 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
886 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
894 #define TIM_OCMODE_TIMING 0x00000000U
895 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
896 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
897 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
898 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
899 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
900 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
901 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
909 #define TIM_TS_ITR0 0x00000000U
910 #define TIM_TS_ITR1 TIM_SMCR_TS_0
911 #define TIM_TS_ITR2 TIM_SMCR_TS_1
912 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
913 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2
914 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
915 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
916 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
917 #define TIM_TS_NONE 0x0000FFFFU
925 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
926 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
927 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
928 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
929 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
937 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
938 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
939 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
940 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
948 #define TIM_TI1SELECTION_CH1 0x00000000U
949 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S
957 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
958 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
959 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
960 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
961 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
962 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
963 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
964 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
965 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
966 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
967 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
968 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
969 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
970 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
971 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
972 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
973 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
974 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
982 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)
983 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001)
984 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002)
985 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003)
986 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004)
987 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)
988 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)
996 #define TIM_CCx_ENABLE 0x00000001U
997 #define TIM_CCx_DISABLE 0x00000000U
998 #define TIM_CCxN_ENABLE 0x00000004U
999 #define TIM_CCxN_DISABLE 0x00000000U
1007 /* End of exported constants -------------------------------------------------*/
1008 
1009 /* Exported macros -----------------------------------------------------------*/
1018 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1019 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
1020  (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
1021  (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1022  (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1023  (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1024  (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1025  (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1026  (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1027  (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1028  (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1029  (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
1030  (__HANDLE__)->Base_MspInitCallback = NULL; \
1031  (__HANDLE__)->Base_MspDeInitCallback = NULL; \
1032  (__HANDLE__)->IC_MspInitCallback = NULL; \
1033  (__HANDLE__)->IC_MspDeInitCallback = NULL; \
1034  (__HANDLE__)->OC_MspInitCallback = NULL; \
1035  (__HANDLE__)->OC_MspDeInitCallback = NULL; \
1036  (__HANDLE__)->PWM_MspInitCallback = NULL; \
1037  (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
1038  (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
1039  (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
1040  (__HANDLE__)->Encoder_MspInitCallback = NULL; \
1041  (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
1042  (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
1043  (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
1044  } while(0)
1045 #else
1046 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
1047  (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
1048  (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1049  (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1050  (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1051  (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1052  (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1053  (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1054  (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1055  (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1056  (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
1057  } while(0)
1058 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1059 
1065 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1066 
1072 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1073 
1079 #define __HAL_TIM_DISABLE(__HANDLE__) \
1080  do { \
1081  if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1082  { \
1083  if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1084  { \
1085  (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1086  } \
1087  } \
1088  } while(0)
1089 
1097 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1098  do { \
1099  if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1100  { \
1101  if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1102  { \
1103  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1104  } \
1105  } \
1106  } while(0)
1107 
1114 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
1115 
1130 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1131 
1146 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1147 
1161 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1162 
1176 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1177 
1196 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1197 
1216 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1217 
1233 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
1234  == (__INTERRUPT__)) ? SET : RESET)
1235 
1250 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1251 
1259 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1260 
1267 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1268 
1275 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1276 
1282 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
1283 
1290 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1291  do{ \
1292  (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1293  (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1294  } while(0)
1295 
1301 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
1302 
1313 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1314  do{ \
1315  (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
1316  (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1317  (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1318  } while(0)
1319 
1328 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1329 
1348 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1349  do{ \
1350  TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1351  TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1352  } while(0)
1353 
1369 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1370  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1371  ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1372  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1373  (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1374 
1387 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1388  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
1389  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
1390  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
1391  ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
1392 
1404 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1405  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
1406  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
1407  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
1408  ((__HANDLE__)->Instance->CCR4))
1409 
1421 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1422  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
1423  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
1424  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
1425  ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
1426 
1438 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1439  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
1440  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
1441  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
1442  ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
1443 
1459 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
1460  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
1461  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
1462  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
1463  ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
1464 
1480 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
1481  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
1482  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
1483  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
1484  ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
1485 
1494 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
1495 
1507 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
1508 
1524 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1525  do{ \
1526  TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1527  TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1528  }while(0)
1529 
1533 /* End of exported macros ----------------------------------------------------*/
1534 
1535 /* Private constants ---------------------------------------------------------*/
1539 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1540  channels have been disabled */
1541 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1542 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1543 
1546 /* End of private constants --------------------------------------------------*/
1547 
1548 /* Private macros ------------------------------------------------------------*/
1552 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
1553  ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
1554 
1555 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
1556  ((__BASE__) == TIM_DMABASE_CR2) || \
1557  ((__BASE__) == TIM_DMABASE_SMCR) || \
1558  ((__BASE__) == TIM_DMABASE_DIER) || \
1559  ((__BASE__) == TIM_DMABASE_SR) || \
1560  ((__BASE__) == TIM_DMABASE_EGR) || \
1561  ((__BASE__) == TIM_DMABASE_CCMR1) || \
1562  ((__BASE__) == TIM_DMABASE_CCMR2) || \
1563  ((__BASE__) == TIM_DMABASE_CCER) || \
1564  ((__BASE__) == TIM_DMABASE_CNT) || \
1565  ((__BASE__) == TIM_DMABASE_PSC) || \
1566  ((__BASE__) == TIM_DMABASE_ARR) || \
1567  ((__BASE__) == TIM_DMABASE_RCR) || \
1568  ((__BASE__) == TIM_DMABASE_CCR1) || \
1569  ((__BASE__) == TIM_DMABASE_CCR2) || \
1570  ((__BASE__) == TIM_DMABASE_CCR3) || \
1571  ((__BASE__) == TIM_DMABASE_CCR4) || \
1572  ((__BASE__) == TIM_DMABASE_BDTR))
1573 
1574 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1575 
1576 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
1577  ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
1578  ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
1579  ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
1580  ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
1581 
1582 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
1583  ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
1584  ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
1585 
1586 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
1587  ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
1588 
1589 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
1590  ((__STATE__) == TIM_OCFAST_ENABLE))
1591 
1592 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
1593  ((__POLARITY__) == TIM_OCPOLARITY_LOW))
1594 
1595 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
1596  ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
1597 
1598 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
1599  ((__STATE__) == TIM_OCIDLESTATE_RESET))
1600 
1601 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
1602  ((__STATE__) == TIM_OCNIDLESTATE_RESET))
1603 
1604 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
1605  ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
1606 
1607 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
1608  ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
1609  ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
1610 
1611 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
1612  ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
1613  ((__SELECTION__) == TIM_ICSELECTION_TRC))
1614 
1615 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
1616  ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
1617  ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
1618  ((__PRESCALER__) == TIM_ICPSC_DIV8))
1619 
1620 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
1621  ((__MODE__) == TIM_OPMODE_REPETITIVE))
1622 
1623 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
1624  ((__MODE__) == TIM_ENCODERMODE_TI2) || \
1625  ((__MODE__) == TIM_ENCODERMODE_TI12))
1626 
1627 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1628 
1629 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1630  ((__CHANNEL__) == TIM_CHANNEL_2) || \
1631  ((__CHANNEL__) == TIM_CHANNEL_3) || \
1632  ((__CHANNEL__) == TIM_CHANNEL_4) || \
1633  ((__CHANNEL__) == TIM_CHANNEL_ALL))
1634 
1635 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1636  ((__CHANNEL__) == TIM_CHANNEL_2))
1637 
1638 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1639  ((__CHANNEL__) == TIM_CHANNEL_2) || \
1640  ((__CHANNEL__) == TIM_CHANNEL_3))
1641 
1642 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1643  ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1644  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
1645  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
1646  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
1647  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
1648  ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
1649  ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
1650  ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
1651  ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
1652 
1653 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
1654  ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1655  ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
1656  ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
1657  ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
1658 
1659 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
1660  ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
1661  ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
1662  ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
1663 
1664 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1665 
1666 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1667  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1668 
1669 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1670  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1671  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1672  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
1673 
1674 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1675 
1676 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
1677  ((__STATE__) == TIM_OSSR_DISABLE))
1678 
1679 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
1680  ((__STATE__) == TIM_OSSI_DISABLE))
1681 
1682 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
1683  ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
1684  ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
1685  ((__LEVEL__) == TIM_LOCKLEVEL_3))
1686 
1687 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
1688 
1689 
1690 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
1691  ((__STATE__) == TIM_BREAK_DISABLE))
1692 
1693 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
1694  ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
1695 
1696 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1697  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
1698 
1699 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
1700  ((__SOURCE__) == TIM_TRGO_ENABLE) || \
1701  ((__SOURCE__) == TIM_TRGO_UPDATE) || \
1702  ((__SOURCE__) == TIM_TRGO_OC1) || \
1703  ((__SOURCE__) == TIM_TRGO_OC1REF) || \
1704  ((__SOURCE__) == TIM_TRGO_OC2REF) || \
1705  ((__SOURCE__) == TIM_TRGO_OC3REF) || \
1706  ((__SOURCE__) == TIM_TRGO_OC4REF))
1707 
1708 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
1709  ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
1710 
1711 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
1712  ((__MODE__) == TIM_SLAVEMODE_RESET) || \
1713  ((__MODE__) == TIM_SLAVEMODE_GATED) || \
1714  ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
1715  ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
1716 
1717 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
1718  ((__MODE__) == TIM_OCMODE_PWM2))
1719 
1720 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
1721  ((__MODE__) == TIM_OCMODE_ACTIVE) || \
1722  ((__MODE__) == TIM_OCMODE_INACTIVE) || \
1723  ((__MODE__) == TIM_OCMODE_TOGGLE) || \
1724  ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
1725  ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
1726 
1727 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1728  ((__SELECTION__) == TIM_TS_ITR1) || \
1729  ((__SELECTION__) == TIM_TS_ITR2) || \
1730  ((__SELECTION__) == TIM_TS_ITR3) || \
1731  ((__SELECTION__) == TIM_TS_TI1F_ED) || \
1732  ((__SELECTION__) == TIM_TS_TI1FP1) || \
1733  ((__SELECTION__) == TIM_TS_TI2FP2) || \
1734  ((__SELECTION__) == TIM_TS_ETRF))
1735 
1736 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1737  ((__SELECTION__) == TIM_TS_ITR1) || \
1738  ((__SELECTION__) == TIM_TS_ITR2) || \
1739  ((__SELECTION__) == TIM_TS_ITR3) || \
1740  ((__SELECTION__) == TIM_TS_NONE))
1741 
1742 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
1743  ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
1744  ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
1745  ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
1746  ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
1747 
1748 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
1749  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
1750  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
1751  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
1752 
1753 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1754 
1755 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
1756  ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
1757 
1758 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
1759  ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
1760  ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
1761  ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
1762  ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
1763  ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
1764  ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
1765  ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
1766  ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
1767  ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
1768  ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
1769  ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
1770  ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
1771  ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
1772  ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
1773  ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
1774  ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
1775  ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
1776 
1777 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
1778 
1779 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1780 
1781 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
1782 
1783 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
1784 
1785 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
1786  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1787  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
1788  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1789  ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
1790 
1791 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
1792  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
1793  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
1794  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
1795  ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
1796 
1797 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1798  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
1799  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
1800  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
1801  ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
1802 
1803 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
1804  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
1805  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
1806  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\
1807  ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
1808 
1809 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
1810  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
1811  ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
1812  ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
1813  (__HANDLE__)->ChannelState[3])
1814 
1815 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
1816  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
1817  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
1818  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
1819  ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
1820 
1821 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
1822  (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
1823  (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
1824  (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
1825  (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
1826  } while(0)
1827 
1828 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
1829  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
1830  ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
1831  ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
1832  (__HANDLE__)->ChannelNState[3])
1833 
1834 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
1835  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
1836  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
1837  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
1838  ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
1839 
1840 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
1841  (__HANDLE__)->ChannelNState[0] = \
1842  (__CHANNEL_STATE__); \
1843  (__HANDLE__)->ChannelNState[1] = \
1844  (__CHANNEL_STATE__); \
1845  (__HANDLE__)->ChannelNState[2] = \
1846  (__CHANNEL_STATE__); \
1847  (__HANDLE__)->ChannelNState[3] = \
1848  (__CHANNEL_STATE__); \
1849  } while(0)
1850 
1854 /* End of private macros -----------------------------------------------------*/
1855 
1856 /* Include TIM HAL Extended module */
1857 #include "stm32f1xx_hal_tim_ex.h"
1858 
1859 /* Exported functions --------------------------------------------------------*/
1868 /* Time Base functions ********************************************************/
1869 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1870 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1871 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1872 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1873 /* Blocking mode: Polling */
1874 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1875 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1876 /* Non-Blocking mode: Interrupt */
1877 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1878 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1879 /* Non-Blocking mode: DMA */
1880 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1881 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1890 /* Timer Output Compare functions *********************************************/
1891 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1892 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1893 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1894 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1895 /* Blocking mode: Polling */
1896 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1897 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1898 /* Non-Blocking mode: Interrupt */
1899 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1900 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1901 /* Non-Blocking mode: DMA */
1902 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1903 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1912 /* Timer PWM functions ********************************************************/
1913 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1914 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1915 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1916 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1917 /* Blocking mode: Polling */
1918 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1919 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1920 /* Non-Blocking mode: Interrupt */
1921 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1922 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1923 /* Non-Blocking mode: DMA */
1924 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1925 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1934 /* Timer Input Capture functions **********************************************/
1935 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1936 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1937 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1938 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1939 /* Blocking mode: Polling */
1940 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1941 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1942 /* Non-Blocking mode: Interrupt */
1943 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1944 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1945 /* Non-Blocking mode: DMA */
1946 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1947 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1956 /* Timer One Pulse functions **************************************************/
1957 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1958 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1959 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1960 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1961 /* Blocking mode: Polling */
1962 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1963 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1964 /* Non-Blocking mode: Interrupt */
1965 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1966 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1975 /* Timer Encoder functions ****************************************************/
1976 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
1977 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
1978 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
1979 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
1980 /* Blocking mode: Polling */
1981 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1982 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1983 /* Non-Blocking mode: Interrupt */
1984 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1985 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1986 /* Non-Blocking mode: DMA */
1987 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
1988  uint32_t *pData2, uint16_t Length);
1989 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1998 /* Interrupt Handler functions ***********************************************/
1999 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
2008 /* Control functions *********************************************************/
2009 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
2010 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
2011 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
2012 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
2013  uint32_t OutputChannel, uint32_t InputChannel);
2014 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
2015  uint32_t Channel);
2016 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
2017 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
2018 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
2019 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
2020 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2021  uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2022 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2023  uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
2024  uint32_t BurstLength, uint32_t DataLength);
2025 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2026 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2027  uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2028 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2029  uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
2030  uint32_t BurstLength, uint32_t DataLength);
2031 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2032 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
2033 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
2042 /* Callback in non blocking modes (Interrupt and DMA) *************************/
2043 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
2044 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
2045 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
2046 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
2047 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
2048 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
2049 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
2050 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
2051 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
2052 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
2053 
2054 /* Callbacks Register/UnRegister functions ***********************************/
2055 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2056 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
2057  pTIM_CallbackTypeDef pCallback);
2058 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
2059 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2060 
2069 /* Peripheral State functions ************************************************/
2070 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
2071 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
2072 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
2073 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
2074 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
2075 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
2076 
2077 /* Peripheral Channel state functions ************************************************/
2078 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
2079 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
2080 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
2088 /* End of exported functions -------------------------------------------------*/
2089 
2090 /* Private functions----------------------------------------------------------*/
2094 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
2095 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
2096 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
2097 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
2098  uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
2099 
2100 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
2101 void TIM_DMAError(DMA_HandleTypeDef *hdma);
2102 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
2103 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
2104 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
2105 
2106 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2107 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
2108 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2109 
2113 /* End of private functions --------------------------------------------------*/
2114 
2123 #ifdef __cplusplus
2124 }
2125 #endif
2126 
2127 #endif /* STM32F1xx_HAL_TIM_H */
2128 
2129 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
stm32f1xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
TIM_HandleTypeDef::DMABurstState
__IO HAL_TIM_DMABurstStateTypeDef DMABurstState
Definition: stm32f1xx_hal_tim.h:350
TIM_HandleTypeDef::Channel
HAL_TIM_ActiveChannel Channel
Definition: stm32f1xx_hal_tim.h:343
TIM_IC_InitTypeDef::ICPrescaler
uint32_t ICPrescaler
Definition: stm32f1xx_hal_tim.h:156
TIM_IC_InitTypeDef::ICFilter
uint32_t ICFilter
Definition: stm32f1xx_hal_tim.h:159
HAL_TIM_ActiveChannel
HAL_TIM_ActiveChannel
HAL Active channel structures definition.
Definition: stm32f1xx_hal_tim.h:323
TIM_MasterConfigTypeDef::MasterOutputTrigger
uint32_t MasterOutputTrigger
Definition: stm32f1xx_hal_tim.h:234
TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition.
Definition: stm32f1xx_hal_tim.h:166
TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode
uint32_t OffStateIDLEMode
Definition: stm32f1xx_hal_tim.h:272
TIM_ClockConfigTypeDef::ClockSource
uint32_t ClockSource
Definition: stm32f1xx_hal_tim.h:201
TIM_OnePulse_InitTypeDef::OCNPolarity
uint32_t OCNPolarity
Definition: stm32f1xx_hal_tim.h:123
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f1xx_hal_dma.h:111
TIM_OnePulse_InitTypeDef::ICSelection
uint32_t ICSelection
Definition: stm32f1xx_hal_tim.h:138
TIM_IC_InitTypeDef::ICSelection
uint32_t ICSelection
Definition: stm32f1xx_hal_tim.h:153
HAL_TIM_STATE_TIMEOUT
Definition: stm32f1xx_hal_tim.h:296
TIM_ClearInputConfigTypeDef::ClearInputPrescaler
uint32_t ClearInputPrescaler
Definition: stm32f1xx_hal_tim.h:222
HAL_TIM_DMABurstStateTypeDef
HAL_TIM_DMABurstStateTypeDef
DMA Burst States definition.
Definition: stm32f1xx_hal_tim.h:313
TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition.
Definition: stm32f1xx_hal_tim.h:47
TIM_MasterConfigTypeDef::MasterSlaveMode
uint32_t MasterSlaveMode
Definition: stm32f1xx_hal_tim.h:236
TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode
uint32_t OffStateRunMode
Definition: stm32f1xx_hal_tim.h:270
TIM_Base_InitTypeDef::CounterMode
uint32_t CounterMode
Definition: stm32f1xx_hal_tim.h:52
TIM_Encoder_InitTypeDef::IC2Filter
uint32_t IC2Filter
Definition: stm32f1xx_hal_tim.h:192
TIM_Encoder_InitTypeDef::IC1Filter
uint32_t IC1Filter
Definition: stm32f1xx_hal_tim.h:180
TIM_ClearInputConfigTypeDef::ClearInputPolarity
uint32_t ClearInputPolarity
Definition: stm32f1xx_hal_tim.h:220
TIM_HandleTypeDef::Init
TIM_Base_InitTypeDef Init
Definition: stm32f1xx_hal_tim.h:342
TIM_BreakDeadTimeConfigTypeDef::DeadTime
uint32_t DeadTime
Definition: stm32f1xx_hal_tim.h:276
TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition.
Definition: stm32f1xx_hal_tim.h:80
TIM_SlaveConfigTypeDef::TriggerPrescaler
uint32_t TriggerPrescaler
Definition: stm32f1xx_hal_tim.h:256
TIM_OC_InitTypeDef::OCPolarity
uint32_t OCPolarity
Definition: stm32f1xx_hal_tim.h:88
TIM_Encoder_InitTypeDef::IC1Polarity
uint32_t IC1Polarity
Definition: stm32f1xx_hal_tim.h:171
TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition.
Definition: stm32f1xx_hal_tim.h:148
TIM_OnePulse_InitTypeDef::OCNIdleState
uint32_t OCNIdleState
Definition: stm32f1xx_hal_tim.h:131
TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition.
Definition: stm32f1xx_hal_tim.h:112
TIM_Base_InitTypeDef::ClockDivision
uint32_t ClockDivision
Definition: stm32f1xx_hal_tim.h:59
TIM_Base_InitTypeDef::Period
uint32_t Period
Definition: stm32f1xx_hal_tim.h:55
HAL_TIM_ACTIVE_CHANNEL_4
Definition: stm32f1xx_hal_tim.h:328
HAL_TIM_STATE_READY
Definition: stm32f1xx_hal_tim.h:294
TIM_ClockConfigTypeDef::ClockFilter
uint32_t ClockFilter
Definition: stm32f1xx_hal_tim.h:207
TIM_OnePulse_InitTypeDef::OCPolarity
uint32_t OCPolarity
Definition: stm32f1xx_hal_tim.h:120
HAL_DMA_BURST_STATE_BUSY
Definition: stm32f1xx_hal_tim.h:317
HAL_TIM_ACTIVE_CHANNEL_2
Definition: stm32f1xx_hal_tim.h:326
HAL_TIM_ACTIVE_CHANNEL_CLEARED
Definition: stm32f1xx_hal_tim.h:329
TIM_IC_InitTypeDef::ICPolarity
uint32_t ICPolarity
Definition: stm32f1xx_hal_tim.h:150
TIM_Base_InitTypeDef::AutoReloadPreload
uint32_t AutoReloadPreload
Definition: stm32f1xx_hal_tim.h:73
HAL_TIM_ACTIVE_CHANNEL_3
Definition: stm32f1xx_hal_tim.h:327
TIM_ClockConfigTypeDef::ClockPolarity
uint32_t ClockPolarity
Definition: stm32f1xx_hal_tim.h:203
TIM_OC_InitTypeDef::OCNPolarity
uint32_t OCNPolarity
Definition: stm32f1xx_hal_tim.h:91
TIM_Encoder_InitTypeDef::IC2Prescaler
uint32_t IC2Prescaler
Definition: stm32f1xx_hal_tim.h:189
TIM_Encoder_InitTypeDef::IC1Prescaler
uint32_t IC1Prescaler
Definition: stm32f1xx_hal_tim.h:177
__IO
#define __IO
Definition: core_armv8mbl.h:196
TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition.
Definition: stm32f1xx_hal_tim.h:199
TIM_BreakDeadTimeConfigTypeDef::LockLevel
uint32_t LockLevel
Definition: stm32f1xx_hal_tim.h:274
TIM_OnePulse_InitTypeDef::Pulse
uint32_t Pulse
Definition: stm32f1xx_hal_tim.h:117
TIM_BreakDeadTimeConfigTypeDef::BreakPolarity
uint32_t BreakPolarity
Definition: stm32f1xx_hal_tim.h:280
TIM_ClearInputConfigTypeDef::ClearInputSource
uint32_t ClearInputSource
Definition: stm32f1xx_hal_tim.h:218
TIM_SlaveConfigTypeDef::SlaveMode
uint32_t SlaveMode
Definition: stm32f1xx_hal_tim.h:250
TIM_ClearInputConfigTypeDef::ClearInputState
uint32_t ClearInputState
Definition: stm32f1xx_hal_tim.h:216
TIM_BreakDeadTimeConfigTypeDef::BreakFilter
uint32_t BreakFilter
Definition: stm32f1xx_hal_tim.h:282
HAL_TIM_STATE_BUSY
Definition: stm32f1xx_hal_tim.h:295
HAL_DMA_BURST_STATE_RESET
Definition: stm32f1xx_hal_tim.h:315
TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput
uint32_t AutomaticOutput
Definition: stm32f1xx_hal_tim.h:284
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32f1xx_hal_def.h:50
HAL_TIM_StateTypeDef
HAL_TIM_StateTypeDef
HAL State structures definition.
Definition: stm32f1xx_hal_tim.h:291
TIM_BreakDeadTimeConfigTypeDef::BreakState
uint32_t BreakState
Definition: stm32f1xx_hal_tim.h:278
HAL_TIM_CHANNEL_STATE_RESET
Definition: stm32f1xx_hal_tim.h:305
TIM_Encoder_InitTypeDef::IC1Selection
uint32_t IC1Selection
Definition: stm32f1xx_hal_tim.h:174
TIM_SlaveConfigTypeDef::InputTrigger
uint32_t InputTrigger
Definition: stm32f1xx_hal_tim.h:252
TIM_OC_InitTypeDef::OCNIdleState
uint32_t OCNIdleState
Definition: stm32f1xx_hal_tim.h:104
HAL_TIM_STATE_RESET
Definition: stm32f1xx_hal_tim.h:293
TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition.
Definition: stm32f1xx_hal_tim.h:248
stm32f1xx_hal_tim_ex.h
Header file of TIM HAL Extended module.
TIM_OC_InitTypeDef::Pulse
uint32_t Pulse
Definition: stm32f1xx_hal_tim.h:85
TIM_OnePulse_InitTypeDef::ICFilter
uint32_t ICFilter
Definition: stm32f1xx_hal_tim.h:141
TIM_Encoder_InitTypeDef::EncoderMode
uint32_t EncoderMode
Definition: stm32f1xx_hal_tim.h:168
TIM_Encoder_InitTypeDef::IC2Selection
uint32_t IC2Selection
Definition: stm32f1xx_hal_tim.h:186
TIM_OC_InitTypeDef::OCMode
uint32_t OCMode
Definition: stm32f1xx_hal_tim.h:82
TIM_Base_InitTypeDef::Prescaler
uint32_t Prescaler
Definition: stm32f1xx_hal_tim.h:49
TIM_TypeDef
TIM Timers.
Definition: stm32f103x6.h:472
TIM_Encoder_InitTypeDef::IC2Polarity
uint32_t IC2Polarity
Definition: stm32f1xx_hal_tim.h:183
TIM_OnePulse_InitTypeDef::OCIdleState
uint32_t OCIdleState
Definition: stm32f1xx_hal_tim.h:127
TIM_HandleTypeDef
TIM Time Base Handle Structure definition.
Definition: stm32f1xx_hal_tim.h:338
TIM_MasterConfigTypeDef
TIM Master configuration Structure definition.
Definition: stm32f1xx_hal_tim.h:232
TIM_ClearInputConfigTypeDef::ClearInputFilter
uint32_t ClearInputFilter
Definition: stm32f1xx_hal_tim.h:225
TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition.
Definition: stm32f1xx_hal_tim.h:214
HAL_TIM_ChannelStateTypeDef
HAL_TIM_ChannelStateTypeDef
TIM Channel States definition.
Definition: stm32f1xx_hal_tim.h:303
TIM_SlaveConfigTypeDef::TriggerPolarity
uint32_t TriggerPolarity
Definition: stm32f1xx_hal_tim.h:254
TIM_OnePulse_InitTypeDef::ICPolarity
uint32_t ICPolarity
Definition: stm32f1xx_hal_tim.h:135
HAL_TIM_CHANNEL_STATE_READY
Definition: stm32f1xx_hal_tim.h:306
TIM_OnePulse_InitTypeDef::OCMode
uint32_t OCMode
Definition: stm32f1xx_hal_tim.h:114
TIM_ClockConfigTypeDef::ClockPrescaler
uint32_t ClockPrescaler
Definition: stm32f1xx_hal_tim.h:205
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f1xx_hal_def.h:39
HAL_TIM_ACTIVE_CHANNEL_1
Definition: stm32f1xx_hal_tim.h:325
TIM_HandleTypeDef::State
__IO HAL_TIM_StateTypeDef State
Definition: stm32f1xx_hal_tim.h:347
TIM_SlaveConfigTypeDef::TriggerFilter
uint32_t TriggerFilter
Definition: stm32f1xx_hal_tim.h:258
TIM_OC_InitTypeDef::OCIdleState
uint32_t OCIdleState
Definition: stm32f1xx_hal_tim.h:100
HAL_TIM_CHANNEL_STATE_BUSY
Definition: stm32f1xx_hal_tim.h:307
HAL_TIM_STATE_ERROR
Definition: stm32f1xx_hal_tim.h:297
TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition.
Definition: stm32f1xx_hal_tim.h:268
TIM_HandleTypeDef::Instance
TIM_TypeDef * Instance
Definition: stm32f1xx_hal_tim.h:341
TIM_Base_InitTypeDef::RepetitionCounter
uint32_t RepetitionCounter
Definition: stm32f1xx_hal_tim.h:62
TIM_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32f1xx_hal_tim.h:346
TIM_OC_InitTypeDef::OCFastMode
uint32_t OCFastMode
Definition: stm32f1xx_hal_tim.h:95
HAL_DMA_BURST_STATE_READY
Definition: stm32f1xx_hal_tim.h:316
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