common_ptx_compilation_options.hpp

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#pragma once
#ifndef CUDA_API_WRAPPERS_COMMON_PTX_COMPILATION_OPTIONS_HPP_
#define CUDA_API_WRAPPERS_COMMON_PTX_COMPILATION_OPTIONS_HPP_

#include "types.hpp"
#include "device.hpp"

#include <array>

namespace cuda {

namespace rtc {

using ptx_register_count_t = int16_t;

using optimization_level_t = int;

} // namespace rtc

enum class memory_operation_t { load, store };

template <memory_operation_t Op> struct caching;

template <> struct caching<memory_operation_t::load> {

    enum mode {
        ca = 0, all = ca, cache_all = ca, cache_at_all_levels = ca, cash_in_l1_and_l2 = ca,

        cg = 1, global = cg, cache_global = cg, cache_at_global_level = cg, cache_in_l2_only = cache_at_global_level,

        cs = 2, evict_first = cs, cache_as_evict_first = cs, cache_streaming = cs,

        lu = 3, last_use = lu,

        cv = 4, dont_cache = cv, fetch_again_and_dont_cache = cv,
    };
    static constexpr const char* mode_names[] = { "ca", "cg", "cs", "lu", "cv" };
};

template <> struct caching<memory_operation_t::store> {

    enum mode {
        wb = 0, write_back = wb, write_back_coherent_levels = wb,
        cg = 1, global = cg, cache_global = cg, cache_at_global_level = cg,
        cs = 2, evict_first = cs, cache_as_evict_first = cs, cache_streaming = cs,
        wt = 3, write_through = wt, write_through_to_system_memory = wt
    };

    static constexpr const char* mode_names[] = { "wb", "cg", "cs", "wt" };
};

template <memory_operation_t Op>
using caching_mode_t = typename caching<Op>::mode;

namespace detail_ {

template <memory_operation_t Op>
const char* name(caching_mode_t<Op> mode)
{
    return caching<Op>::mode_names[static_cast<int>(mode)];
}

} // namespace detail_

template <memory_operation_t Op>
inline ::std::ostream& operator<< (::std::ostream& os, caching_mode_t<Op> lcm)
{
    return os << detail_::name(lcm);
}

namespace rtc {

constexpr const struct {
    optimization_level_t minimum;
    optimization_level_t maximum;
} valid_optimization_level_range {0, 4};

struct common_ptx_compilation_options_t {

    optional<ptx_register_count_t> max_num_registers_per_thread{};

    optional<grid::block_dimension_t> min_num_threads_per_block{};

    optional<optimization_level_t> optimization_level{};

    optional<device::compute_capability_t> specific_target;

    bool generate_source_line_info {false};

    bool generate_debug_info {false};

    optional<caching_mode_t<memory_operation_t::load>> default_load_caching_mode_;

    virtual optional<caching_mode_t<memory_operation_t::load>>& default_load_caching_mode()
    {
        return default_load_caching_mode_;
    }

    virtual optional<caching_mode_t<memory_operation_t::load>> default_load_caching_mode() const
    {
        return default_load_caching_mode_;
    }

    bool generate_relocatable_device_code { false };

    // What about store caching?
}; // common_ptx_compilation_options_t

} // namespace rtc
} // namespace cuda

#endif // CUDA_API_WRAPPERS_COMMON_PTX_COMPILATION_OPTIONS_HPP_