25 #ifndef __TBB_machine_H 26 #error Do not include this file directly; include tbb_machine.h instead 30 #if !(__ARM_ARCH_7A__) 31 #error compilation requires an ARMv7-a architecture. 34 #include <sys/param.h> 37 #define __TBB_WORDSIZE 4 44 #if __BIG_ENDIAN__ || (defined(__BYTE_ORDER__) && __BYTE_ORDER__==__ORDER_BIG_ENDIAN__) 45 #define __TBB_ENDIANNESS __TBB_ENDIAN_BIG 46 #elif __LITTLE_ENDIAN__ || (defined(__BYTE_ORDER__) && __BYTE_ORDER__==__ORDER_LITTLE_ENDIAN__) 47 #define __TBB_ENDIANNESS __TBB_ENDIAN_LITTLE 48 #elif defined(__BYTE_ORDER__) 49 #define __TBB_ENDIANNESS __TBB_ENDIAN_UNSUPPORTED 51 #define __TBB_ENDIANNESS __TBB_ENDIAN_DETECT 55 #define __TBB_compiler_fence() __asm__ __volatile__("": : :"memory") 56 #define __TBB_full_memory_fence() __asm__ __volatile__("dmb ish": : :"memory") 57 #define __TBB_control_consistency_helper() __TBB_full_memory_fence() 58 #define __TBB_acquire_consistency_helper() __TBB_full_memory_fence() 59 #define __TBB_release_consistency_helper() __TBB_full_memory_fence() 72 static inline int32_t __TBB_machine_cmpswp4(
volatile void *ptr, int32_t value, int32_t comparand )
76 __TBB_full_memory_fence();
84 "strexeq %0, %5, [%3]\n" 85 :
"=&r" (res),
"=&r" (oldval),
"+Qo" (*(
volatile int32_t*)ptr)
86 :
"r" ((int32_t *)ptr),
"Ir" (comparand),
"r" (value)
90 __TBB_full_memory_fence();
102 static inline int64_t __TBB_machine_cmpswp8(
volatile void *ptr, int64_t value, int64_t comparand )
107 __TBB_full_memory_fence();
110 __asm__ __volatile__(
112 "ldrexd %1, %H1, [%3]\n" 117 "strexdeq %0, %5, %H5, [%3]" 118 :
"=&r" (res),
"=&r" (oldval),
"+Qo" (*(
volatile int64_t*)ptr)
119 :
"r" ((int64_t *)ptr),
"r" (comparand),
"r" (value)
123 __TBB_full_memory_fence();
128 static inline int32_t __TBB_machine_fetchadd4(
volatile void* ptr, int32_t addend)
131 int32_t result, tmp2;
133 __TBB_full_memory_fence();
135 __asm__ __volatile__(
136 "1: ldrex %0, [%4]\n" 138 " strex %1, %3, [%4]\n" 141 :
"=&r" (result),
"=&r" (tmp),
"+Qo" (*(
volatile int32_t*)ptr),
"=&r"(tmp2)
142 :
"r" ((int32_t *)ptr),
"Ir" (addend)
145 __TBB_full_memory_fence();
150 static inline int64_t __TBB_machine_fetchadd8(
volatile void *ptr, int64_t addend)
153 int64_t result, tmp2;
155 __TBB_full_memory_fence();
157 __asm__ __volatile__(
158 "1: ldrexd %0, %H0, [%4]\n" 160 " adc %H3, %H0, %H5\n" 161 " strexd %1, %3, %H3, [%4]\n" 164 :
"=&r" (result),
"=&r" (tmp),
"+Qo" (*(
volatile int64_t*)ptr),
"=&r"(tmp2)
165 :
"r" ((int64_t *)ptr),
"r" (addend)
169 __TBB_full_memory_fence();
174 inline void __TBB_machine_pause (int32_t delay )
178 __TBB_compiler_fence();
185 template <
typename T,
size_t S>
187 static inline T load (
const volatile T& location ) {
188 const T value = location;
194 __TBB_acquire_consistency_helper();
198 static inline void store (
volatile T& location, T value ) {
206 #define __TBB_CompareAndSwap4(P,V,C) __TBB_machine_cmpswp4(P,V,C) 207 #define __TBB_CompareAndSwap8(P,V,C) __TBB_machine_cmpswp8(P,V,C) 208 #define __TBB_Pause(V) __TBB_machine_pause(V) 211 #define __TBB_USE_GENERIC_PART_WORD_CAS 1 212 #define __TBB_USE_GENERIC_PART_WORD_FETCH_ADD 1 213 #define __TBB_USE_GENERIC_PART_WORD_FETCH_STORE 1 214 #define __TBB_USE_GENERIC_FETCH_STORE 1 215 #define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1 216 #define __TBB_USE_GENERIC_DWORD_LOAD_STORE 1 217 #define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1 Definition: gcc_armv7.h:186
Definition: _flow_graph_async_msg_impl.h:32
The namespace tbb contains all components of the library.
Definition: parallel_for.h:44