BRE12
linux_ia32.h
1 /*
2  Copyright 2005-2016 Intel Corporation. All Rights Reserved.
3 
4  This file is part of Threading Building Blocks. Threading Building Blocks is free software;
5  you can redistribute it and/or modify it under the terms of the GNU General Public License
6  version 2 as published by the Free Software Foundation. Threading Building Blocks is
7  distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the
8  implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
9  See the GNU General Public License for more details. You should have received a copy of
10  the GNU General Public License along with Threading Building Blocks; if not, write to the
11  Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
12 
13  As a special exception, you may use this file as part of a free software library without
14  restriction. Specifically, if other files instantiate templates or use macros or inline
15  functions from this file, or you compile this file and link it with other files to produce
16  an executable, this file does not by itself cause the resulting executable to be covered
17  by the GNU General Public License. This exception does not however invalidate any other
18  reasons why the executable file might be covered by the GNU General Public License.
19 */
20 
21 #if !defined(__TBB_machine_H) || defined(__TBB_machine_linux_ia32_H)
22 #error Do not #include this internal file directly; use public TBB headers instead.
23 #endif
24 
25 #define __TBB_machine_linux_ia32_H
26 
27 #include <stdint.h>
28 #include "gcc_ia32_common.h"
29 
30 #define __TBB_WORDSIZE 4
31 #define __TBB_ENDIANNESS __TBB_ENDIAN_LITTLE
32 
33 #define __TBB_compiler_fence() __asm__ __volatile__("": : :"memory")
34 #define __TBB_control_consistency_helper() __TBB_compiler_fence()
35 #define __TBB_acquire_consistency_helper() __TBB_compiler_fence()
36 #define __TBB_release_consistency_helper() __TBB_compiler_fence()
37 #define __TBB_full_memory_fence() __asm__ __volatile__("mfence": : :"memory")
38 
39 #if __TBB_ICC_ASM_VOLATILE_BROKEN
40 #define __TBB_VOLATILE
41 #else
42 #define __TBB_VOLATILE volatile
43 #endif
44 
45 #define __TBB_MACHINE_DEFINE_ATOMICS(S,T,X,R) \
46 static inline T __TBB_machine_cmpswp##S (volatile void *ptr, T value, T comparand ) \
47 { \
48  T result; \
49  \
50  __asm__ __volatile__("lock\ncmpxchg" X " %2,%1" \
51  : "=a"(result), "=m"(*(__TBB_VOLATILE T*)ptr) \
52  : "q"(value), "0"(comparand), "m"(*(__TBB_VOLATILE T*)ptr) \
53  : "memory"); \
54  return result; \
55 } \
56  \
57 static inline T __TBB_machine_fetchadd##S(volatile void *ptr, T addend) \
58 { \
59  T result; \
60  __asm__ __volatile__("lock\nxadd" X " %0,%1" \
61  : R (result), "=m"(*(__TBB_VOLATILE T*)ptr) \
62  : "0"(addend), "m"(*(__TBB_VOLATILE T*)ptr) \
63  : "memory"); \
64  return result; \
65 } \
66  \
67 static inline T __TBB_machine_fetchstore##S(volatile void *ptr, T value) \
68 { \
69  T result; \
70  __asm__ __volatile__("lock\nxchg" X " %0,%1" \
71  : R (result), "=m"(*(__TBB_VOLATILE T*)ptr) \
72  : "0"(value), "m"(*(__TBB_VOLATILE T*)ptr) \
73  : "memory"); \
74  return result; \
75 } \
76 
77 __TBB_MACHINE_DEFINE_ATOMICS(1,int8_t,"","=q")
78 __TBB_MACHINE_DEFINE_ATOMICS(2,int16_t,"","=r")
79 __TBB_MACHINE_DEFINE_ATOMICS(4,int32_t,"l","=r")
80 
81 #if __INTEL_COMPILER
82 #pragma warning( push )
83 // reference to EBX in a function requiring stack alignment
84 #pragma warning( disable: 998 )
85 #endif
86 
87 #if __TBB_GCC_CAS8_BUILTIN_INLINING_BROKEN
88 #define __TBB_IA32_CAS8_NOINLINE __attribute__ ((noinline))
89 #else
90 #define __TBB_IA32_CAS8_NOINLINE
91 #endif
92 
93 static inline __TBB_IA32_CAS8_NOINLINE int64_t __TBB_machine_cmpswp8 (volatile void *ptr, int64_t value, int64_t comparand ) {
94 //TODO: remove the extra part of condition once __TBB_GCC_BUILTIN_ATOMICS_PRESENT is lowered to gcc version 4.1.2
95 #if (__TBB_GCC_BUILTIN_ATOMICS_PRESENT || (__TBB_GCC_VERSION >= 40102)) && !__TBB_GCC_64BIT_ATOMIC_BUILTINS_BROKEN
96  return __sync_val_compare_and_swap( reinterpret_cast<volatile int64_t*>(ptr), comparand, value );
97 #else /* !__TBB_GCC_BUILTIN_ATOMICS_PRESENT */
98  //TODO: look like ICC 13.0 has some issues with this code, investigate it more deeply
99  int64_t result;
100  union {
101  int64_t i64;
102  int32_t i32[2];
103  };
104  i64 = value;
105 #if __PIC__
106  /* compiling position-independent code */
107  // EBX register preserved for compliance with position-independent code rules on IA32
108  int32_t tmp;
109  __asm__ __volatile__ (
110  "movl %%ebx,%2\n\t"
111  "movl %5,%%ebx\n\t"
112 #if __GNUC__==3
113  "lock\n\t cmpxchg8b %1\n\t"
114 #else
115  "lock\n\t cmpxchg8b (%3)\n\t"
116 #endif
117  "movl %2,%%ebx"
118  : "=A"(result)
119  , "=m"(*(__TBB_VOLATILE int64_t *)ptr)
120  , "=m"(tmp)
121 #if __GNUC__==3
122  : "m"(*(__TBB_VOLATILE int64_t *)ptr)
123 #else
124  : "SD"(ptr)
125 #endif
126  , "0"(comparand)
127  , "m"(i32[0]), "c"(i32[1])
128  : "memory"
129 #if __INTEL_COMPILER
130  ,"ebx"
131 #endif
132  );
133 #else /* !__PIC__ */
134  __asm__ __volatile__ (
135  "lock\n\t cmpxchg8b %1\n\t"
136  : "=A"(result), "=m"(*(__TBB_VOLATILE int64_t *)ptr)
137  : "m"(*(__TBB_VOLATILE int64_t *)ptr)
138  , "0"(comparand)
139  , "b"(i32[0]), "c"(i32[1])
140  : "memory"
141  );
142 #endif /* __PIC__ */
143  return result;
144 #endif /* !__TBB_GCC_BUILTIN_ATOMICS_PRESENT */
145 }
146 
147 #undef __TBB_IA32_CAS8_NOINLINE
148 
149 #if __INTEL_COMPILER
150 #pragma warning( pop )
151 #endif // warning 998 is back
152 
153 static inline void __TBB_machine_or( volatile void *ptr, uint32_t addend ) {
154  __asm__ __volatile__("lock\norl %1,%0" : "=m"(*(__TBB_VOLATILE uint32_t *)ptr) : "r"(addend), "m"(*(__TBB_VOLATILE uint32_t *)ptr) : "memory");
155 }
156 
157 static inline void __TBB_machine_and( volatile void *ptr, uint32_t addend ) {
158  __asm__ __volatile__("lock\nandl %1,%0" : "=m"(*(__TBB_VOLATILE uint32_t *)ptr) : "r"(addend), "m"(*(__TBB_VOLATILE uint32_t *)ptr) : "memory");
159 }
160 
161 //TODO: Check if it possible and profitable for IA-32 architecture on (Linux* and Windows*)
162 //to use of 64-bit load/store via floating point registers together with full fence
163 //for sequentially consistent load/store, instead of CAS.
164 
165 #if __clang__
166 #define __TBB_fildq "fildll"
167 #define __TBB_fistpq "fistpll"
168 #else
169 #define __TBB_fildq "fildq"
170 #define __TBB_fistpq "fistpq"
171 #endif
172 
173 static inline int64_t __TBB_machine_aligned_load8 (const volatile void *ptr) {
174  __TBB_ASSERT(tbb::internal::is_aligned(ptr,8),"__TBB_machine_aligned_load8 should be used with 8 byte aligned locations only \n");
175  int64_t result;
176  __asm__ __volatile__ ( __TBB_fildq " %1\n\t"
177  __TBB_fistpq " %0" : "=m"(result) : "m"(*(const __TBB_VOLATILE uint64_t*)ptr) : "memory" );
178  return result;
179 }
180 
181 static inline void __TBB_machine_aligned_store8 (volatile void *ptr, int64_t value ) {
182  __TBB_ASSERT(tbb::internal::is_aligned(ptr,8),"__TBB_machine_aligned_store8 should be used with 8 byte aligned locations only \n");
183  // Aligned store
184  __asm__ __volatile__ ( __TBB_fildq " %1\n\t"
185  __TBB_fistpq " %0" : "=m"(*(__TBB_VOLATILE int64_t*)ptr) : "m"(value) : "memory" );
186 }
187 
188 static inline int64_t __TBB_machine_load8 (const volatile void *ptr) {
189 #if __TBB_FORCE_64BIT_ALIGNMENT_BROKEN
190  if( tbb::internal::is_aligned(ptr,8)) {
191 #endif
192  return __TBB_machine_aligned_load8(ptr);
193 #if __TBB_FORCE_64BIT_ALIGNMENT_BROKEN
194  } else {
195  // Unaligned load
196  return __TBB_machine_cmpswp8(const_cast<void*>(ptr),0,0);
197  }
198 #endif
199 }
200 
202 
203 extern "C" void __TBB_machine_store8_slow( volatile void *ptr, int64_t value );
204 extern "C" void __TBB_machine_store8_slow_perf_warning( volatile void *ptr );
205 
206 static inline void __TBB_machine_store8(volatile void *ptr, int64_t value) {
207 #if __TBB_FORCE_64BIT_ALIGNMENT_BROKEN
208  if( tbb::internal::is_aligned(ptr,8)) {
209 #endif
210  __TBB_machine_aligned_store8(ptr,value);
211 #if __TBB_FORCE_64BIT_ALIGNMENT_BROKEN
212  } else {
213  // Unaligned store
214 #if TBB_USE_PERFORMANCE_WARNINGS
215  __TBB_machine_store8_slow_perf_warning(ptr);
216 #endif /* TBB_USE_PERFORMANCE_WARNINGS */
217  __TBB_machine_store8_slow(ptr,value);
218  }
219 #endif
220 }
221 
222 // Machine specific atomic operations
223 #define __TBB_AtomicOR(P,V) __TBB_machine_or(P,V)
224 #define __TBB_AtomicAND(P,V) __TBB_machine_and(P,V)
225 
226 #define __TBB_USE_GENERIC_DWORD_FETCH_ADD 1
227 #define __TBB_USE_GENERIC_DWORD_FETCH_STORE 1
228 #define __TBB_USE_FETCHSTORE_AS_FULL_FENCED_STORE 1
229 #define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1
230 #define __TBB_USE_GENERIC_RELAXED_LOAD_STORE 1
231 #define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1
232 
*/
Definition: material.h:665