BRE12
sunos_sparc.h
1 /*
2  Copyright 2005-2016 Intel Corporation. All Rights Reserved.
3 
4  This file is part of Threading Building Blocks. Threading Building Blocks is free software;
5  you can redistribute it and/or modify it under the terms of the GNU General Public License
6  version 2 as published by the Free Software Foundation. Threading Building Blocks is
7  distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the
8  implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
9  See the GNU General Public License for more details. You should have received a copy of
10  the GNU General Public License along with Threading Building Blocks; if not, write to the
11  Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
12 
13  As a special exception, you may use this file as part of a free software library without
14  restriction. Specifically, if other files instantiate templates or use macros or inline
15  functions from this file, or you compile this file and link it with other files to produce
16  an executable, this file does not by itself cause the resulting executable to be covered
17  by the GNU General Public License. This exception does not however invalidate any other
18  reasons why the executable file might be covered by the GNU General Public License.
19 */
20 
21 
22 #if !defined(__TBB_machine_H) || defined(__TBB_machine_sunos_sparc_H)
23 #error Do not #include this internal file directly; use public TBB headers instead.
24 #endif
25 
26 #define __TBB_machine_sunos_sparc_H
27 
28 #include <stdint.h>
29 #include <unistd.h>
30 
31 #define __TBB_WORDSIZE 8
32 // Big endian is assumed for SPARC.
33 // While hardware may support page-specific bi-endianness, only big endian pages may be exposed to TBB
34 #define __TBB_ENDIANNESS __TBB_ENDIAN_BIG
35 
38 #define __TBB_compiler_fence() __asm__ __volatile__ ("": : :"memory")
39 #define __TBB_control_consistency_helper() __TBB_compiler_fence()
40 #define __TBB_acquire_consistency_helper() __TBB_compiler_fence()
41 #define __TBB_release_consistency_helper() __TBB_compiler_fence()
42 #define __TBB_full_memory_fence() __asm__ __volatile__("membar #LoadLoad|#LoadStore|#StoreStore|#StoreLoad": : : "memory")
43 
44 //--------------------------------------------------
45 // Compare and swap
46 //--------------------------------------------------
47 
55 static inline int32_t __TBB_machine_cmpswp4(volatile void *ptr, int32_t value, int32_t comparand ){
56  int32_t result;
57  __asm__ __volatile__(
58  "cas\t[%5],%4,%1"
59  : "=m"(*(int32_t *)ptr), "=r"(result)
60  : "m"(*(int32_t *)ptr), "1"(value), "r"(comparand), "r"(ptr)
61  : "memory");
62  return result;
63 }
64 
72 static inline int64_t __TBB_machine_cmpswp8(volatile void *ptr, int64_t value, int64_t comparand ){
73  int64_t result;
74  __asm__ __volatile__(
75  "casx\t[%5],%4,%1"
76  : "=m"(*(int64_t *)ptr), "=r"(result)
77  : "m"(*(int64_t *)ptr), "1"(value), "r"(comparand), "r"(ptr)
78  : "memory");
79  return result;
80 }
81 
82 //---------------------------------------------------
83 // Fetch and add
84 //---------------------------------------------------
85 
92 static inline int32_t __TBB_machine_fetchadd4(volatile void *ptr, int32_t addend){
93  int32_t result;
94  __asm__ __volatile__ (
95  "0:\t add\t %3, %4, %0\n" // do addition
96  "\t cas\t [%2], %3, %0\n" // cas to store result in memory
97  "\t cmp\t %3, %0\n" // check if value from memory is original
98  "\t bne,a,pn\t %%icc, 0b\n" // if not try again
99  "\t mov %0, %3\n" // use branch delay slot to move new value in memory to be added
100  : "=&r"(result), "=m"(*(int32_t *)ptr)
101  : "r"(ptr), "r"(*(int32_t *)ptr), "r"(addend), "m"(*(int32_t *)ptr)
102  : "ccr", "memory");
103  return result;
104 }
105 
112 static inline int64_t __TBB_machine_fetchadd8(volatile void *ptr, int64_t addend){
113  int64_t result;
114  __asm__ __volatile__ (
115  "0:\t add\t %3, %4, %0\n" // do addition
116  "\t casx\t [%2], %3, %0\n" // cas to store result in memory
117  "\t cmp\t %3, %0\n" // check if value from memory is original
118  "\t bne,a,pn\t %%xcc, 0b\n" // if not try again
119  "\t mov %0, %3\n" // use branch delay slot to move new value in memory to be added
120  : "=&r"(result), "=m"(*(int64_t *)ptr)
121  : "r"(ptr), "r"(*(int64_t *)ptr), "r"(addend), "m"(*(int64_t *)ptr)
122  : "ccr", "memory");
123  return result;
124 }
125 
126 //--------------------------------------------------------
127 // Logarithm (base two, integer)
128 //--------------------------------------------------------
129 
130 static inline int64_t __TBB_machine_lg( uint64_t x ) {
131  __TBB_ASSERT(x, "__TBB_Log2(0) undefined");
132  uint64_t count;
133  // one hot encode
134  x |= (x >> 1);
135  x |= (x >> 2);
136  x |= (x >> 4);
137  x |= (x >> 8);
138  x |= (x >> 16);
139  x |= (x >> 32);
140  // count 1's
141  __asm__ ("popc %1, %0" : "=r"(count) : "r"(x) );
142  return count-1;
143 }
144 
145 //--------------------------------------------------------
146 
147 static inline void __TBB_machine_or( volatile void *ptr, uint64_t value ) {
148  __asm__ __volatile__ (
149  "0:\t or\t %2, %3, %%g1\n" // do operation
150  "\t casx\t [%1], %2, %%g1\n" // cas to store result in memory
151  "\t cmp\t %2, %%g1\n" // check if value from memory is original
152  "\t bne,a,pn\t %%xcc, 0b\n" // if not try again
153  "\t mov %%g1, %2\n" // use branch delay slot to move new value in memory to be added
154  : "=m"(*(int64_t *)ptr)
155  : "r"(ptr), "r"(*(int64_t *)ptr), "r"(value), "m"(*(int64_t *)ptr)
156  : "ccr", "g1", "memory");
157 }
158 
159 static inline void __TBB_machine_and( volatile void *ptr, uint64_t value ) {
160  __asm__ __volatile__ (
161  "0:\t and\t %2, %3, %%g1\n" // do operation
162  "\t casx\t [%1], %2, %%g1\n" // cas to store result in memory
163  "\t cmp\t %2, %%g1\n" // check if value from memory is original
164  "\t bne,a,pn\t %%xcc, 0b\n" // if not try again
165  "\t mov %%g1, %2\n" // use branch delay slot to move new value in memory to be added
166  : "=m"(*(int64_t *)ptr)
167  : "r"(ptr), "r"(*(int64_t *)ptr), "r"(value), "m"(*(int64_t *)ptr)
168  : "ccr", "g1", "memory");
169 }
170 
171 
172 static inline void __TBB_machine_pause( int32_t delay ) {
173  // do nothing, inlined, doesn't matter
174 }
175 
176 // put 0xff in memory location, return memory value,
177 // generic trylockbyte puts 0x01, however this is fine
178 // because all that matters is that 0 is unlocked
179 static inline bool __TBB_machine_trylockbyte(unsigned char &flag){
180  unsigned char result;
181  __asm__ __volatile__ (
182  "ldstub\t [%2], %0\n"
183  : "=r"(result), "=m"(flag)
184  : "r"(&flag), "m"(flag)
185  : "memory");
186  return result == 0;
187 }
188 
189 #define __TBB_USE_GENERIC_PART_WORD_CAS 1
190 #define __TBB_USE_GENERIC_PART_WORD_FETCH_ADD 1
191 #define __TBB_USE_GENERIC_FETCH_STORE 1
192 #define __TBB_USE_GENERIC_HALF_FENCED_LOAD_STORE 1
193 #define __TBB_USE_GENERIC_RELAXED_LOAD_STORE 1
194 #define __TBB_USE_GENERIC_SEQUENTIAL_CONSISTENCY_LOAD_STORE 1
195 
196 #define __TBB_AtomicOR(P,V) __TBB_machine_or(P,V)
197 #define __TBB_AtomicAND(P,V) __TBB_machine_and(P,V)
198 
199 // Definition of other functions
200 #define __TBB_Pause(V) __TBB_machine_pause(V)
201 #define __TBB_Log2(V) __TBB_machine_lg(V)
202 
203 #define __TBB_TryLockByte(P) __TBB_machine_trylockbyte(P)
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