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core_cm1.h
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1 /**************************************************************************/
7 /*
8  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #endif
30 
31 #ifndef __CORE_CM1_H_GENERIC
32 #define __CORE_CM1_H_GENERIC
33 
34 #include <stdint.h>
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif
39 
55 /*******************************************************************************
56  * CMSIS definitions
57  ******************************************************************************/
63 #include "cmsis_version.h"
64 
65 /* CMSIS CM1 definitions */
66 #define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67 #define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68 #define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \
69  __CM1_CMSIS_VERSION_SUB )
71 #define __CORTEX_M (1U)
76 #define __FPU_USED 0U
77 
78 #if defined ( __CC_ARM )
79  #if defined __TARGET_FPU_VFP
80  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81  #endif
82 
83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84  #if defined __ARM_PCS_VFP
85  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86  #endif
87 
88 #elif defined ( __GNUC__ )
89  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91  #endif
92 
93 #elif defined ( __ICCARM__ )
94  #if defined __ARMVFP__
95  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96  #endif
97 
98 #elif defined ( __TI_ARM__ )
99  #if defined __TI_VFP_SUPPORT__
100  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101  #endif
102 
103 #elif defined ( __TASKING__ )
104  #if defined __FPU_VFP__
105  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106  #endif
107 
108 #elif defined ( __CSMC__ )
109  #if ( __CSMC__ & 0x400U)
110  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111  #endif
112 
113 #endif
114 
115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
116 
117 
118 #ifdef __cplusplus
119 }
120 #endif
121 
122 #endif /* __CORE_CM1_H_GENERIC */
123 
124 #ifndef __CMSIS_GENERIC
125 
126 #ifndef __CORE_CM1_H_DEPENDANT
127 #define __CORE_CM1_H_DEPENDANT
128 
129 #ifdef __cplusplus
130  extern "C" {
131 #endif
132 
133 /* check device defines and use defaults */
134 #if defined __CHECK_DEVICE_DEFINES
135  #ifndef __CM1_REV
136  #define __CM1_REV 0x0100U
137  #warning "__CM1_REV not defined in device header file; using default!"
138  #endif
139 
140  #ifndef __NVIC_PRIO_BITS
141  #define __NVIC_PRIO_BITS 2U
142  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
143  #endif
144 
145  #ifndef __Vendor_SysTickConfig
146  #define __Vendor_SysTickConfig 0U
147  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
148  #endif
149 #endif
150 
151 /* IO definitions (access restrictions to peripheral registers) */
159 #ifdef __cplusplus
160  #define __I volatile
161 #else
162  #define __I volatile const
163 #endif
164 #define __O volatile
165 #define __IO volatile
167 /* following defines should be used for structure members */
168 #define __IM volatile const
169 #define __OM volatile
170 #define __IOM volatile
172 
176 /*******************************************************************************
177  * Register Abstraction
178  Core Register contain:
179  - Core Register
180  - Core NVIC Register
181  - Core SCB Register
182  - Core SysTick Register
183  ******************************************************************************/
184 
199 typedef union
200 {
201  struct
202  {
203  uint32_t _reserved0:28;
204  uint32_t V:1;
205  uint32_t C:1;
206  uint32_t Z:1;
207  uint32_t N:1;
208  } b;
209  uint32_t w;
210 } APSR_Type;
211 
212 /* APSR Register Definitions */
213 #define APSR_N_Pos 31U
214 #define APSR_N_Msk (1UL << APSR_N_Pos)
216 #define APSR_Z_Pos 30U
217 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
219 #define APSR_C_Pos 29U
220 #define APSR_C_Msk (1UL << APSR_C_Pos)
222 #define APSR_V_Pos 28U
223 #define APSR_V_Msk (1UL << APSR_V_Pos)
229 typedef union
230 {
231  struct
232  {
233  uint32_t ISR:9;
234  uint32_t _reserved0:23;
235  } b;
236  uint32_t w;
237 } IPSR_Type;
238 
239 /* IPSR Register Definitions */
240 #define IPSR_ISR_Pos 0U
241 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
247 typedef union
248 {
249  struct
250  {
251  uint32_t ISR:9;
252  uint32_t _reserved0:15;
253  uint32_t T:1;
254  uint32_t _reserved1:3;
255  uint32_t V:1;
256  uint32_t C:1;
257  uint32_t Z:1;
258  uint32_t N:1;
259  } b;
260  uint32_t w;
261 } xPSR_Type;
262 
263 /* xPSR Register Definitions */
264 #define xPSR_N_Pos 31U
265 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
267 #define xPSR_Z_Pos 30U
268 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
270 #define xPSR_C_Pos 29U
271 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
273 #define xPSR_V_Pos 28U
274 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
276 #define xPSR_T_Pos 24U
277 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
279 #define xPSR_ISR_Pos 0U
280 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
286 typedef union
287 {
288  struct
289  {
290  uint32_t _reserved0:1;
291  uint32_t SPSEL:1;
292  uint32_t _reserved1:30;
293  } b;
294  uint32_t w;
295 } CONTROL_Type;
296 
297 /* CONTROL Register Definitions */
298 #define CONTROL_SPSEL_Pos 1U
299 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
301 
314 typedef struct
315 {
316  __IOM uint32_t ISER[1U];
317  uint32_t RESERVED0[31U];
318  __IOM uint32_t ICER[1U];
319  uint32_t RSERVED1[31U];
320  __IOM uint32_t ISPR[1U];
321  uint32_t RESERVED2[31U];
322  __IOM uint32_t ICPR[1U];
323  uint32_t RESERVED3[31U];
324  uint32_t RESERVED4[64U];
325  __IOM uint32_t IP[8U];
326 } NVIC_Type;
327 
341 typedef struct
342 {
343  __IM uint32_t CPUID;
344  __IOM uint32_t ICSR;
345  uint32_t RESERVED0;
346  __IOM uint32_t AIRCR;
347  __IOM uint32_t SCR;
348  __IOM uint32_t CCR;
349  uint32_t RESERVED1;
350  __IOM uint32_t SHP[2U];
351  __IOM uint32_t SHCSR;
352 } SCB_Type;
353 
354 /* SCB CPUID Register Definitions */
355 #define SCB_CPUID_IMPLEMENTER_Pos 24U
356 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
358 #define SCB_CPUID_VARIANT_Pos 20U
359 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
361 #define SCB_CPUID_ARCHITECTURE_Pos 16U
362 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
364 #define SCB_CPUID_PARTNO_Pos 4U
365 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
367 #define SCB_CPUID_REVISION_Pos 0U
368 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
370 /* SCB Interrupt Control State Register Definitions */
371 #define SCB_ICSR_NMIPENDSET_Pos 31U
372 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
374 #define SCB_ICSR_PENDSVSET_Pos 28U
375 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
377 #define SCB_ICSR_PENDSVCLR_Pos 27U
378 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
380 #define SCB_ICSR_PENDSTSET_Pos 26U
381 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
383 #define SCB_ICSR_PENDSTCLR_Pos 25U
384 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
386 #define SCB_ICSR_ISRPREEMPT_Pos 23U
387 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
389 #define SCB_ICSR_ISRPENDING_Pos 22U
390 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
392 #define SCB_ICSR_VECTPENDING_Pos 12U
393 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
395 #define SCB_ICSR_VECTACTIVE_Pos 0U
396 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
398 /* SCB Application Interrupt and Reset Control Register Definitions */
399 #define SCB_AIRCR_VECTKEY_Pos 16U
400 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
402 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
403 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
405 #define SCB_AIRCR_ENDIANESS_Pos 15U
406 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
408 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
409 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
411 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
412 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
414 /* SCB System Control Register Definitions */
415 #define SCB_SCR_SEVONPEND_Pos 4U
416 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
418 #define SCB_SCR_SLEEPDEEP_Pos 2U
419 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
421 #define SCB_SCR_SLEEPONEXIT_Pos 1U
422 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
424 /* SCB Configuration Control Register Definitions */
425 #define SCB_CCR_STKALIGN_Pos 9U
426 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
428 #define SCB_CCR_UNALIGN_TRP_Pos 3U
429 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
431 /* SCB System Handler Control and State Register Definitions */
432 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
433 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
435 
448 typedef struct
449 {
450  uint32_t RESERVED0[2U];
451  __IOM uint32_t ACTLR;
452 } SCnSCB_Type;
453 
454 /* Auxiliary Control Register Definitions */
455 #define SCnSCB_ACTLR_ITCMUAEN_Pos 4U
456 #define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos)
458 #define SCnSCB_ACTLR_ITCMLAEN_Pos 3U
459 #define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos)
461 
474 typedef struct
475 {
476  __IOM uint32_t CTRL;
477  __IOM uint32_t LOAD;
478  __IOM uint32_t VAL;
479  __IM uint32_t CALIB;
480 } SysTick_Type;
481 
482 /* SysTick Control / Status Register Definitions */
483 #define SysTick_CTRL_COUNTFLAG_Pos 16U
484 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
486 #define SysTick_CTRL_CLKSOURCE_Pos 2U
487 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
489 #define SysTick_CTRL_TICKINT_Pos 1U
490 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
492 #define SysTick_CTRL_ENABLE_Pos 0U
493 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
495 /* SysTick Reload Register Definitions */
496 #define SysTick_LOAD_RELOAD_Pos 0U
497 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
499 /* SysTick Current Register Definitions */
500 #define SysTick_VAL_CURRENT_Pos 0U
501 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
503 /* SysTick Calibration Register Definitions */
504 #define SysTick_CALIB_NOREF_Pos 31U
505 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
507 #define SysTick_CALIB_SKEW_Pos 30U
508 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
510 #define SysTick_CALIB_TENMS_Pos 0U
511 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
513 
523 
539 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
540 
547 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
548 
559 /* Memory mapping of Core Hardware */
560 #define SCS_BASE (0xE000E000UL)
561 #define SysTick_BASE (SCS_BASE + 0x0010UL)
562 #define NVIC_BASE (SCS_BASE + 0x0100UL)
563 #define SCB_BASE (SCS_BASE + 0x0D00UL)
565 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
566 #define SCB ((SCB_Type *) SCB_BASE )
567 #define SysTick ((SysTick_Type *) SysTick_BASE )
568 #define NVIC ((NVIC_Type *) NVIC_BASE )
571 
575 /*******************************************************************************
576  * Hardware Abstraction Layer
577  Core Function Interface contains:
578  - Core NVIC Functions
579  - Core SysTick Functions
580  - Core Register Access Functions
581  ******************************************************************************/
582 
588 /* ########################## NVIC functions #################################### */
596 #ifdef CMSIS_NVIC_VIRTUAL
597  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
598  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
599  #endif
600  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
601 #else
602  #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
603  #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
604  #define NVIC_EnableIRQ __NVIC_EnableIRQ
605  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
606  #define NVIC_DisableIRQ __NVIC_DisableIRQ
607  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
608  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
609  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
610 /*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */
611  #define NVIC_SetPriority __NVIC_SetPriority
612  #define NVIC_GetPriority __NVIC_GetPriority
613  #define NVIC_SystemReset __NVIC_SystemReset
614 #endif /* CMSIS_NVIC_VIRTUAL */
615 
616 #ifdef CMSIS_VECTAB_VIRTUAL
617  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
618  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
619  #endif
620  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
621 #else
622  #define NVIC_SetVector __NVIC_SetVector
623  #define NVIC_GetVector __NVIC_GetVector
624 #endif /* (CMSIS_VECTAB_VIRTUAL) */
625 
626 #define NVIC_USER_IRQ_OFFSET 16
627 
628 
629 /* The following EXC_RETURN values are saved the LR on exception entry */
630 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
631 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
632 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
633 
634 
635 /* Interrupt Priorities are WORD accessible only under Armv6-M */
636 /* The following MACROS handle generation of the register offset and byte masks */
637 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
638 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
639 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
640 
641 #define __NVIC_SetPriorityGrouping(X) (void)(X)
642 #define __NVIC_GetPriorityGrouping() (0U)
643 
650 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
651 {
652  if ((int32_t)(IRQn) >= 0)
653  {
654  NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
655  }
656 }
657 
658 
667 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
668 {
669  if ((int32_t)(IRQn) >= 0)
670  {
671  return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
672  }
673  else
674  {
675  return(0U);
676  }
677 }
678 
679 
686 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
687 {
688  if ((int32_t)(IRQn) >= 0)
689  {
690  NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
691  __DSB();
692  __ISB();
693  }
694 }
695 
696 
705 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
706 {
707  if ((int32_t)(IRQn) >= 0)
708  {
709  return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
710  }
711  else
712  {
713  return(0U);
714  }
715 }
716 
717 
724 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
725 {
726  if ((int32_t)(IRQn) >= 0)
727  {
728  NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
729  }
730 }
731 
732 
739 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
740 {
741  if ((int32_t)(IRQn) >= 0)
742  {
743  NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
744  }
745 }
746 
747 
757 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
758 {
759  if ((int32_t)(IRQn) >= 0)
760  {
761  NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
762  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
763  }
764  else
765  {
766  SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
767  (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
768  }
769 }
770 
771 
781 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
782 {
783 
784  if ((int32_t)(IRQn) >= 0)
785  {
786  return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
787  }
788  else
789  {
790  return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
791  }
792 }
793 
794 
806 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
807 {
808  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
809  uint32_t PreemptPriorityBits;
810  uint32_t SubPriorityBits;
811 
812  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
813  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
814 
815  return (
816  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
817  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
818  );
819 }
820 
821 
833 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
834 {
835  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
836  uint32_t PreemptPriorityBits;
837  uint32_t SubPriorityBits;
838 
839  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
840  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
841 
842  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
843  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
844 }
845 
846 
847 
857 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
858 {
859  uint32_t *vectors = (uint32_t *)0x0U;
860  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
861 }
862 
863 
872 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
873 {
874  uint32_t *vectors = (uint32_t *)0x0U;
875  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
876 }
877 
878 
883 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
884 {
885  __DSB(); /* Ensure all outstanding memory accesses included
886  buffered write are completed before reset */
887  SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
888  SCB_AIRCR_SYSRESETREQ_Msk);
889  __DSB(); /* Ensure completion of memory access */
890 
891  for(;;) /* wait until reset */
892  {
893  __NOP();
894  }
895 }
896 
900 /* ########################## FPU functions #################################### */
916 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
917 {
918  return 0U; /* No FPU */
919 }
920 
921 
926 /* ################################## SysTick function ############################################ */
934 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
935 
947 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
948 {
949  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
950  {
951  return (1UL); /* Reload value impossible */
952  }
953 
954  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
955  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
956  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
957  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
958  SysTick_CTRL_TICKINT_Msk |
959  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
960  return (0UL); /* Function successful */
961 }
962 
963 #endif
964 
970 #ifdef __cplusplus
971 }
972 #endif
973 
974 #endif /* __CORE_CM1_H_DEPENDANT */
975 
976 #endif /* __CMSIS_GENERIC */
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv8mbl.h:1269
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv8mbl.h:1523
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv8mbl.h:1791
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm1.h:399
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv8mbl.h:351
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm1.h:487
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_armv8mbl.h:381
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv8mbl.h:1496
SysTick_IRQn
Definition: stm32f103xb.h:80
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:877
__NOP
#define __NOP
No Operation.
Definition: cmsis_armcc.h:387
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv8mbl.h:1326
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv8mbl.h:1341
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm1.h:490
SCB
#define SCB
Definition: core_cm1.h:566
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_armv8mbl.h:558
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_armv8mbl.h:233
cmsis_version.h
CMSIS Core(M) Version definitions.
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv8mbl.h:1252
SysTick
#define SysTick
Definition: core_cm1.h:567
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv8mbl.h:1547
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_armv8mbl.h:320
NVIC
#define NVIC
Definition: core_cm1.h:568
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm1.h:497
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_armv8mml.h:1009
IRQn_Type
IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f103xb.h:69
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv8mbl.h:263
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:866
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv8mbl.h:281
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv8mbl.h:1288
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm1.h:493
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv8mbl.h:1566
cmsis_compiler.h
CMSIS compiler generic header file.
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: stm32f103xb.h:52
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm1.h:409
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv8mbl.h:1581
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv8mbl.h:1447
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv8mbl.h:1307
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv8mbl.h:1471
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