Enable or disable the AHB1 peripheral clock. More...
Collaboration diagram for Peripheral Clock Enable Disable:
|
Macros | |
| #define | __HAL_RCC_DMA1_CLK_ENABLE() |
| #define | __HAL_RCC_SRAM_CLK_ENABLE() |
| #define | __HAL_RCC_FLITF_CLK_ENABLE() |
| #define | __HAL_RCC_CRC_CLK_ENABLE() |
| #define | __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) |
| #define | __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) |
| #define | __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) |
| #define | __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) |
Detailed Description
Enable or disable the AHB1 peripheral clock.
- Note
- After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Macro Definition Documentation
◆ __HAL_RCC_CRC_CLK_ENABLE
| #define __HAL_RCC_CRC_CLK_ENABLE | ( | ) |
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
UNUSED(tmpreg); \
} while(0U)
◆ __HAL_RCC_DMA1_CLK_ENABLE
| #define __HAL_RCC_DMA1_CLK_ENABLE | ( | ) |
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
UNUSED(tmpreg); \
} while(0U)
◆ __HAL_RCC_FLITF_CLK_ENABLE
| #define __HAL_RCC_FLITF_CLK_ENABLE | ( | ) |
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
UNUSED(tmpreg); \
} while(0U)
◆ __HAL_RCC_SRAM_CLK_ENABLE
| #define __HAL_RCC_SRAM_CLK_ENABLE | ( | ) |
Value:
do { \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
/* Delay after an RCC peripheral clock enabling */\
tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
UNUSED(tmpreg); \
} while(0U)
