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stm32f1xx_hal_cortex.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F1xx_HAL_CORTEX_H
22 #define __STM32F1xx_HAL_CORTEX_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f1xx_hal_def.h"
30 
38 /* Exported types ------------------------------------------------------------*/
43 #if (__MPU_PRESENT == 1U)
44 
48 typedef struct
49 {
50  uint8_t Enable;
52  uint8_t Number;
54  uint32_t BaseAddress;
55  uint8_t Size;
57  uint8_t SubRegionDisable;
59  uint8_t TypeExtField;
61  uint8_t AccessPermission;
63  uint8_t DisableExec;
65  uint8_t IsShareable;
67  uint8_t IsCacheable;
69  uint8_t IsBufferable;
71 }MPU_Region_InitTypeDef;
75 #endif /* __MPU_PRESENT */
76 
81 /* Exported constants --------------------------------------------------------*/
82 
90 #define NVIC_PRIORITYGROUP_0 0x00000007U
92 #define NVIC_PRIORITYGROUP_1 0x00000006U
94 #define NVIC_PRIORITYGROUP_2 0x00000005U
96 #define NVIC_PRIORITYGROUP_3 0x00000004U
98 #define NVIC_PRIORITYGROUP_4 0x00000003U
107 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U
108 #define SYSTICK_CLKSOURCE_HCLK 0x00000004U
109 
114 #if (__MPU_PRESENT == 1)
115 
118 #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U
119 #define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk
120 #define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk
121 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk)
122 
130 #define MPU_REGION_ENABLE ((uint8_t)0x01)
131 #define MPU_REGION_DISABLE ((uint8_t)0x00)
132 
139 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
140 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
141 
148 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
149 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
150 
157 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
158 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
159 
166 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
167 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
168 
175 #define MPU_TEX_LEVEL0 ((uint8_t)0x00)
176 #define MPU_TEX_LEVEL1 ((uint8_t)0x01)
177 #define MPU_TEX_LEVEL2 ((uint8_t)0x02)
178 
185 #define MPU_REGION_SIZE_32B ((uint8_t)0x04)
186 #define MPU_REGION_SIZE_64B ((uint8_t)0x05)
187 #define MPU_REGION_SIZE_128B ((uint8_t)0x06)
188 #define MPU_REGION_SIZE_256B ((uint8_t)0x07)
189 #define MPU_REGION_SIZE_512B ((uint8_t)0x08)
190 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
191 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
192 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
193 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
194 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
195 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
196 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
197 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
198 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
199 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
200 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
201 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
202 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
203 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
204 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
205 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
206 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
207 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
208 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
209 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
210 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
211 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
212 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
213 
220 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
221 #define MPU_REGION_PRIV_RW ((uint8_t)0x01)
222 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
223 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
224 #define MPU_REGION_PRIV_RO ((uint8_t)0x05)
225 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
226 
233 #define MPU_REGION_NUMBER0 ((uint8_t)0x00)
234 #define MPU_REGION_NUMBER1 ((uint8_t)0x01)
235 #define MPU_REGION_NUMBER2 ((uint8_t)0x02)
236 #define MPU_REGION_NUMBER3 ((uint8_t)0x03)
237 #define MPU_REGION_NUMBER4 ((uint8_t)0x04)
238 #define MPU_REGION_NUMBER5 ((uint8_t)0x05)
239 #define MPU_REGION_NUMBER6 ((uint8_t)0x06)
240 #define MPU_REGION_NUMBER7 ((uint8_t)0x07)
241 
244 #endif /* __MPU_PRESENT */
245 
251 /* Exported Macros -----------------------------------------------------------*/
252 
253 /* Exported functions --------------------------------------------------------*/
261 /* Initialization and de-initialization functions *****************************/
262 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
263 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
264 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
265 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
266 void HAL_NVIC_SystemReset(void);
267 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
275 /* Peripheral Control functions ***********************************************/
276 uint32_t HAL_NVIC_GetPriorityGrouping(void);
277 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
278 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
279 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
280 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
281 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
282 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
283 void HAL_SYSTICK_IRQHandler(void);
284 void HAL_SYSTICK_Callback(void);
285 
286 #if (__MPU_PRESENT == 1U)
287 void HAL_MPU_Enable(uint32_t MPU_Control);
288 void HAL_MPU_Disable(void);
289 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
290 #endif /* __MPU_PRESENT */
291 
299 /* Private types -------------------------------------------------------------*/
300 /* Private variables ---------------------------------------------------------*/
301 /* Private constants ---------------------------------------------------------*/
302 /* Private macros ------------------------------------------------------------*/
306 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
307  ((GROUP) == NVIC_PRIORITYGROUP_1) || \
308  ((GROUP) == NVIC_PRIORITYGROUP_2) || \
309  ((GROUP) == NVIC_PRIORITYGROUP_3) || \
310  ((GROUP) == NVIC_PRIORITYGROUP_4))
311 
312 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
313 
314 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
315 
316 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U)
317 
318 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
319  ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
320 
321 #if (__MPU_PRESENT == 1U)
322 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
323  ((STATE) == MPU_REGION_DISABLE))
324 
325 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
326  ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
327 
328 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \
329  ((STATE) == MPU_ACCESS_NOT_SHAREABLE))
330 
331 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \
332  ((STATE) == MPU_ACCESS_NOT_CACHEABLE))
333 
334 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \
335  ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))
336 
337 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \
338  ((TYPE) == MPU_TEX_LEVEL1) || \
339  ((TYPE) == MPU_TEX_LEVEL2))
340 
341 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \
342  ((TYPE) == MPU_REGION_PRIV_RW) || \
343  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \
344  ((TYPE) == MPU_REGION_FULL_ACCESS) || \
345  ((TYPE) == MPU_REGION_PRIV_RO) || \
346  ((TYPE) == MPU_REGION_PRIV_RO_URO))
347 
348 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
349  ((NUMBER) == MPU_REGION_NUMBER1) || \
350  ((NUMBER) == MPU_REGION_NUMBER2) || \
351  ((NUMBER) == MPU_REGION_NUMBER3) || \
352  ((NUMBER) == MPU_REGION_NUMBER4) || \
353  ((NUMBER) == MPU_REGION_NUMBER5) || \
354  ((NUMBER) == MPU_REGION_NUMBER6) || \
355  ((NUMBER) == MPU_REGION_NUMBER7))
356 
357 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \
358  ((SIZE) == MPU_REGION_SIZE_64B) || \
359  ((SIZE) == MPU_REGION_SIZE_128B) || \
360  ((SIZE) == MPU_REGION_SIZE_256B) || \
361  ((SIZE) == MPU_REGION_SIZE_512B) || \
362  ((SIZE) == MPU_REGION_SIZE_1KB) || \
363  ((SIZE) == MPU_REGION_SIZE_2KB) || \
364  ((SIZE) == MPU_REGION_SIZE_4KB) || \
365  ((SIZE) == MPU_REGION_SIZE_8KB) || \
366  ((SIZE) == MPU_REGION_SIZE_16KB) || \
367  ((SIZE) == MPU_REGION_SIZE_32KB) || \
368  ((SIZE) == MPU_REGION_SIZE_64KB) || \
369  ((SIZE) == MPU_REGION_SIZE_128KB) || \
370  ((SIZE) == MPU_REGION_SIZE_256KB) || \
371  ((SIZE) == MPU_REGION_SIZE_512KB) || \
372  ((SIZE) == MPU_REGION_SIZE_1MB) || \
373  ((SIZE) == MPU_REGION_SIZE_2MB) || \
374  ((SIZE) == MPU_REGION_SIZE_4MB) || \
375  ((SIZE) == MPU_REGION_SIZE_8MB) || \
376  ((SIZE) == MPU_REGION_SIZE_16MB) || \
377  ((SIZE) == MPU_REGION_SIZE_32MB) || \
378  ((SIZE) == MPU_REGION_SIZE_64MB) || \
379  ((SIZE) == MPU_REGION_SIZE_128MB) || \
380  ((SIZE) == MPU_REGION_SIZE_256MB) || \
381  ((SIZE) == MPU_REGION_SIZE_512MB) || \
382  ((SIZE) == MPU_REGION_SIZE_1GB) || \
383  ((SIZE) == MPU_REGION_SIZE_2GB) || \
384  ((SIZE) == MPU_REGION_SIZE_4GB))
385 
386 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
387 #endif /* __MPU_PRESENT */
388 
393 /* Private functions ---------------------------------------------------------*/
394 
403 #ifdef __cplusplus
404 }
405 #endif
406 
407 #endif /* __STM32F1xx_HAL_CORTEX_H */
408 
409 
410 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
stm32f1xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
IRQn_Type
IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f103xb.h:69
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