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stm32f1xx_hal_flash_ex.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F1xx_HAL_FLASH_EX_H
22 #define __STM32F1xx_HAL_FLASH_EX_H
23 
24 #ifdef __cplusplus
25  extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f1xx_hal_def.h"
30 
43 #define FLASH_SIZE_DATA_REGISTER 0x1FFFF7E0U
44 #define OBR_REG_INDEX 1U
45 #define SR_FLAG_MASK ((uint32_t)(FLASH_SR_BSY | FLASH_SR_PGERR | FLASH_SR_WRPRTERR | FLASH_SR_EOP))
46 
55 #define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || ((VALUE) == FLASH_TYPEERASE_MASSERASE))
56 
57 #define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_DATA)))
58 
59 #define IS_WRPSTATE(VALUE) (((VALUE) == OB_WRPSTATE_DISABLE) || ((VALUE) == OB_WRPSTATE_ENABLE))
60 
61 #define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) || ((LEVEL) == OB_RDP_LEVEL_1))
62 
63 #define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == OB_DATA_ADDRESS_DATA0) || ((ADDRESS) == OB_DATA_ADDRESS_DATA1))
64 
65 #define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
66 
67 #define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))
68 
69 #define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))
70 
71 #if defined(FLASH_BANK2_END)
72 #define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
73 #endif /* FLASH_BANK2_END */
74 
75 /* Low Density */
76 #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
77 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08007FFFU) : \
78  ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)- 1 <= 0x08003FFFU))
79 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
80 
81 /* Medium Density */
82 #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
83 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
84  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU) : \
85  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08007FFFU) : \
86  ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x08003FFFU))))
87 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
88 
89 /* High Density */
90 #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
91 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0807FFFFU) : \
92  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0805FFFFU) : \
93  ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU)))
94 #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
95 
96 /* XL Density */
97 #if defined(FLASH_BANK2_END)
98 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080FFFFFU) : \
99  ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x080BFFFFU))
100 #endif /* FLASH_BANK2_END */
101 
102 /* Connectivity Line */
103 #if (defined(STM32F105xC) || defined(STM32F107xC))
104 #define IS_FLASH_NB_PAGES(ADDRESS,NBPAGES) (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0803FFFFU) : \
105  (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0801FFFFU) : \
106  ((ADDRESS)+((NBPAGES)*FLASH_PAGE_SIZE)-1 <= 0x0800FFFFU)))
107 #endif /* STM32F105xC || STM32F107xC */
108 
109 #define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000U))
110 
111 #if defined(FLASH_BANK2_END)
112 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
113  ((BANK) == FLASH_BANK_2) || \
114  ((BANK) == FLASH_BANK_BOTH))
115 #else
116 #define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1))
117 #endif /* FLASH_BANK2_END */
118 
119 /* Low Density */
120 #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6))
121 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
122  ((ADDRESS) <= FLASH_BANK1_END) : ((ADDRESS) <= 0x08003FFFU)))
123 
124 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
125 
126 /* Medium Density */
127 #if (defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
128 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
129  ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x40U) ? \
130  ((ADDRESS) <= 0x0800FFFF) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x20U) ? \
131  ((ADDRESS) <= 0x08007FFF) : ((ADDRESS) <= 0x08003FFFU)))))
132 
133 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
134 
135 /* High Density */
136 #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE))
137 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x200U) ? \
138  ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x180U) ? \
139  ((ADDRESS) <= 0x0805FFFFU) : ((ADDRESS) <= 0x0803FFFFU))))
140 
141 #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
142 
143 /* XL Density */
144 #if defined(FLASH_BANK2_END)
145 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x400U) ? \
146  ((ADDRESS) <= FLASH_BANK2_END) : ((ADDRESS) <= 0x080BFFFFU)))
147 
148 #endif /* FLASH_BANK2_END */
149 
150 /* Connectivity Line */
151 #if (defined(STM32F105xC) || defined(STM32F107xC))
152 #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x100U) ? \
153  ((ADDRESS) <= FLASH_BANK1_END) : (((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x80U) ? \
154  ((ADDRESS) <= 0x0801FFFFU) : ((ADDRESS) <= 0x0800FFFFU))))
155 
156 #endif /* STM32F105xC || STM32F107xC */
157 
162 /* Exported types ------------------------------------------------------------*/
170 typedef struct
171 {
172  uint32_t TypeErase;
175  uint32_t Banks;
178  uint32_t PageAddress;
182  uint32_t NbPages;
185 } FLASH_EraseInitTypeDef;
186 
190 typedef struct
191 {
192  uint32_t OptionType;
195  uint32_t WRPState;
198  uint32_t WRPPage;
201  uint32_t Banks;
204  uint8_t RDPLevel;
207 #if defined(FLASH_BANK2_END)
208  uint8_t USERConfig;
212 #else
213  uint8_t USERConfig;
217 #endif /* FLASH_BANK2_END */
218 
219  uint32_t DATAAddress;
222  uint8_t DATAData;
224 } FLASH_OBProgramInitTypeDef;
225 
230 /* Exported constants --------------------------------------------------------*/
242 #if (defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB))
243 #define FLASH_PAGE_SIZE 0x400U
244 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
245  /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
246 
247 #if (defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) || defined(STM32F101xG) || defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC))
248 #define FLASH_PAGE_SIZE 0x800U
249 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
250  /* STM32F101xG || STM32F103xG */
251  /* STM32F105xC || STM32F107xC */
252 
260 #define FLASH_TYPEERASE_PAGES 0x00U
261 #define FLASH_TYPEERASE_MASSERASE 0x02U
270 #if defined(FLASH_BANK2_END)
271 #define FLASH_BANK_1 1U
272 #define FLASH_BANK_2 2U
273 #define FLASH_BANK_BOTH ((uint32_t)FLASH_BANK_1 | FLASH_BANK_2)
275 #else
276 #define FLASH_BANK_1 1U
277 #endif
278 
293 #define OPTIONBYTE_WRP 0x01U
294 #define OPTIONBYTE_RDP 0x02U
295 #define OPTIONBYTE_USER 0x04U
296 #define OPTIONBYTE_DATA 0x08U
305 #define OB_WRPSTATE_DISABLE 0x00U
306 #define OB_WRPSTATE_ENABLE 0x01U
315 /* STM32 Low and Medium density devices */
316 #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6) \
317  || defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) \
318  || defined(STM32F103xB)
319 #define OB_WRP_PAGES0TO3 0x00000001U
320 #define OB_WRP_PAGES4TO7 0x00000002U
321 #define OB_WRP_PAGES8TO11 0x00000004U
322 #define OB_WRP_PAGES12TO15 0x00000008U
323 #define OB_WRP_PAGES16TO19 0x00000010U
324 #define OB_WRP_PAGES20TO23 0x00000020U
325 #define OB_WRP_PAGES24TO27 0x00000040U
326 #define OB_WRP_PAGES28TO31 0x00000080U
327 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
328  /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
329 
330 /* STM32 Medium-density devices */
331 #if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
332 #define OB_WRP_PAGES32TO35 0x00000100U
333 #define OB_WRP_PAGES36TO39 0x00000200U
334 #define OB_WRP_PAGES40TO43 0x00000400U
335 #define OB_WRP_PAGES44TO47 0x00000800U
336 #define OB_WRP_PAGES48TO51 0x00001000U
337 #define OB_WRP_PAGES52TO55 0x00002000U
338 #define OB_WRP_PAGES56TO59 0x00004000U
339 #define OB_WRP_PAGES60TO63 0x00008000U
340 #define OB_WRP_PAGES64TO67 0x00010000U
341 #define OB_WRP_PAGES68TO71 0x00020000U
342 #define OB_WRP_PAGES72TO75 0x00040000U
343 #define OB_WRP_PAGES76TO79 0x00080000U
344 #define OB_WRP_PAGES80TO83 0x00100000U
345 #define OB_WRP_PAGES84TO87 0x00200000U
346 #define OB_WRP_PAGES88TO91 0x00400000U
347 #define OB_WRP_PAGES92TO95 0x00800000U
348 #define OB_WRP_PAGES96TO99 0x01000000U
349 #define OB_WRP_PAGES100TO103 0x02000000U
350 #define OB_WRP_PAGES104TO107 0x04000000U
351 #define OB_WRP_PAGES108TO111 0x08000000U
352 #define OB_WRP_PAGES112TO115 0x10000000U
353 #define OB_WRP_PAGES116TO119 0x20000000U
354 #define OB_WRP_PAGES120TO123 0x40000000U
355 #define OB_WRP_PAGES124TO127 0x80000000U
356 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
357 
358 
359 /* STM32 High-density, XL-density and Connectivity line devices */
360 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE) \
361  || defined(STM32F101xG) || defined(STM32F103xG) \
362  || defined(STM32F105xC) || defined(STM32F107xC)
363 #define OB_WRP_PAGES0TO1 0x00000001U
364 #define OB_WRP_PAGES2TO3 0x00000002U
365 #define OB_WRP_PAGES4TO5 0x00000004U
366 #define OB_WRP_PAGES6TO7 0x00000008U
367 #define OB_WRP_PAGES8TO9 0x00000010U
368 #define OB_WRP_PAGES10TO11 0x00000020U
369 #define OB_WRP_PAGES12TO13 0x00000040U
370 #define OB_WRP_PAGES14TO15 0x00000080U
371 #define OB_WRP_PAGES16TO17 0x00000100U
372 #define OB_WRP_PAGES18TO19 0x00000200U
373 #define OB_WRP_PAGES20TO21 0x00000400U
374 #define OB_WRP_PAGES22TO23 0x00000800U
375 #define OB_WRP_PAGES24TO25 0x00001000U
376 #define OB_WRP_PAGES26TO27 0x00002000U
377 #define OB_WRP_PAGES28TO29 0x00004000U
378 #define OB_WRP_PAGES30TO31 0x00008000U
379 #define OB_WRP_PAGES32TO33 0x00010000U
380 #define OB_WRP_PAGES34TO35 0x00020000U
381 #define OB_WRP_PAGES36TO37 0x00040000U
382 #define OB_WRP_PAGES38TO39 0x00080000U
383 #define OB_WRP_PAGES40TO41 0x00100000U
384 #define OB_WRP_PAGES42TO43 0x00200000U
385 #define OB_WRP_PAGES44TO45 0x00400000U
386 #define OB_WRP_PAGES46TO47 0x00800000U
387 #define OB_WRP_PAGES48TO49 0x01000000U
388 #define OB_WRP_PAGES50TO51 0x02000000U
389 #define OB_WRP_PAGES52TO53 0x04000000U
390 #define OB_WRP_PAGES54TO55 0x08000000U
391 #define OB_WRP_PAGES56TO57 0x10000000U
392 #define OB_WRP_PAGES58TO59 0x20000000U
393 #define OB_WRP_PAGES60TO61 0x40000000U
394 #define OB_WRP_PAGES62TO127 0x80000000U
395 #define OB_WRP_PAGES62TO255 0x80000000U
396 #define OB_WRP_PAGES62TO511 0x80000000U
397 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB */
398  /* STM32F101xG || STM32F103xG */
399  /* STM32F105xC || STM32F107xC */
400 
401 #define OB_WRP_ALLPAGES 0xFFFFFFFFU
403 /* Low Density */
404 #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F103x6)
405 #define OB_WRP_PAGES0TO31MASK 0x000000FFU
406 #endif /* STM32F101x6 || STM32F102x6 || STM32F103x6 */
407 
408 /* Medium Density */
409 #if defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F102xB) || defined(STM32F103xB)
410 #define OB_WRP_PAGES0TO31MASK 0x000000FFU
411 #define OB_WRP_PAGES32TO63MASK 0x0000FF00U
412 #define OB_WRP_PAGES64TO95MASK 0x00FF0000U
413 #define OB_WRP_PAGES96TO127MASK 0xFF000000U
414 #endif /* STM32F100xB || STM32F101xB || STM32F102xB || STM32F103xB*/
415 
416 /* High Density */
417 #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F103xE)
418 #define OB_WRP_PAGES0TO15MASK 0x000000FFU
419 #define OB_WRP_PAGES16TO31MASK 0x0000FF00U
420 #define OB_WRP_PAGES32TO47MASK 0x00FF0000U
421 #define OB_WRP_PAGES48TO255MASK 0xFF000000U
422 #endif /* STM32F100xE || STM32F101xE || STM32F103xE */
423 
424 /* XL Density */
425 #if defined(STM32F101xG) || defined(STM32F103xG)
426 #define OB_WRP_PAGES0TO15MASK 0x000000FFU
427 #define OB_WRP_PAGES16TO31MASK 0x0000FF00U
428 #define OB_WRP_PAGES32TO47MASK 0x00FF0000U
429 #define OB_WRP_PAGES48TO511MASK 0xFF000000U
430 #endif /* STM32F101xG || STM32F103xG */
431 
432 /* Connectivity line devices */
433 #if defined(STM32F105xC) || defined(STM32F107xC)
434 #define OB_WRP_PAGES0TO15MASK 0x000000FFU
435 #define OB_WRP_PAGES16TO31MASK 0x0000FF00U
436 #define OB_WRP_PAGES32TO47MASK 0x00FF0000U
437 #define OB_WRP_PAGES48TO127MASK 0xFF000000U
438 #endif /* STM32F105xC || STM32F107xC */
439 
447 #define OB_RDP_LEVEL_0 ((uint8_t)0xA5)
448 #define OB_RDP_LEVEL_1 ((uint8_t)0x00)
449 
456 #define OB_IWDG_SW ((uint16_t)0x0001)
457 #define OB_IWDG_HW ((uint16_t)0x0000)
465 #define OB_STOP_NO_RST ((uint16_t)0x0002)
466 #define OB_STOP_RST ((uint16_t)0x0000)
474 #define OB_STDBY_NO_RST ((uint16_t)0x0004)
475 #define OB_STDBY_RST ((uint16_t)0x0000)
480 #if defined(FLASH_BANK2_END)
481 
484 #define OB_BOOT1_RESET ((uint16_t)0x0000)
485 #define OB_BOOT1_SET ((uint16_t)0x0008)
489 #endif /* FLASH_BANK2_END */
490 
494 #define OB_DATA_ADDRESS_DATA0 0x1FFFF804U
495 #define OB_DATA_ADDRESS_DATA1 0x1FFFF806U
496 
512 #if defined(FLASH_BANK2_END)
513  #define FLASH_FLAG_BSY FLASH_FLAG_BSY_BANK1
514  #define FLASH_FLAG_PGERR FLASH_FLAG_PGERR_BANK1
515  #define FLASH_FLAG_WRPERR FLASH_FLAG_WRPERR_BANK1
516  #define FLASH_FLAG_EOP FLASH_FLAG_EOP_BANK1
518  #define FLASH_FLAG_BSY_BANK1 FLASH_SR_BSY
519  #define FLASH_FLAG_PGERR_BANK1 FLASH_SR_PGERR
520  #define FLASH_FLAG_WRPERR_BANK1 FLASH_SR_WRPRTERR
521  #define FLASH_FLAG_EOP_BANK1 FLASH_SR_EOP
523  #define FLASH_FLAG_BSY_BANK2 (FLASH_SR2_BSY << 16U)
524  #define FLASH_FLAG_PGERR_BANK2 (FLASH_SR2_PGERR << 16U)
525  #define FLASH_FLAG_WRPERR_BANK2 (FLASH_SR2_WRPRTERR << 16U)
526  #define FLASH_FLAG_EOP_BANK2 (FLASH_SR2_EOP << 16U)
528 #else
529 
530  #define FLASH_FLAG_BSY FLASH_SR_BSY
531  #define FLASH_FLAG_PGERR FLASH_SR_PGERR
532  #define FLASH_FLAG_WRPERR FLASH_SR_WRPRTERR
533  #define FLASH_FLAG_EOP FLASH_SR_EOP
535 #endif
536  #define FLASH_FLAG_OPTVERR ((OBR_REG_INDEX << 8U | FLASH_OBR_OPTERR))
545 #if defined(FLASH_BANK2_END)
546  #define FLASH_IT_EOP FLASH_IT_EOP_BANK1
547  #define FLASH_IT_ERR FLASH_IT_ERR_BANK1
549  #define FLASH_IT_EOP_BANK1 FLASH_CR_EOPIE
550  #define FLASH_IT_ERR_BANK1 FLASH_CR_ERRIE
552  #define FLASH_IT_EOP_BANK2 (FLASH_CR2_EOPIE << 16U)
553  #define FLASH_IT_ERR_BANK2 (FLASH_CR2_ERRIE << 16U)
555 #else
556 
557  #define FLASH_IT_EOP FLASH_CR_EOPIE
558  #define FLASH_IT_ERR FLASH_CR_ERRIE
560 #endif
561 
574 /* Exported macro ------------------------------------------------------------*/
584 #if defined(FLASH_BANK2_END)
585 
595 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { \
596  /* Enable Bank1 IT */ \
597  SET_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
598  /* Enable Bank2 IT */ \
599  SET_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
600  } while(0U)
601 
612 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { \
613  /* Disable Bank1 IT */ \
614  CLEAR_BIT(FLASH->CR, ((__INTERRUPT__) & 0x0000FFFFU)); \
615  /* Disable Bank2 IT */ \
616  CLEAR_BIT(FLASH->CR2, ((__INTERRUPT__) >> 16U)); \
617  } while(0U)
618 
634 #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
635  (FLASH->OBR & FLASH_OBR_OPTERR) : \
636  ((((__FLAG__) & SR_FLAG_MASK) != RESET)? \
637  (FLASH->SR & ((__FLAG__) & SR_FLAG_MASK)) : \
638  (FLASH->SR2 & ((__FLAG__) >> 16U))))
639 
655 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \
656  /* Clear FLASH_FLAG_OPTVERR flag */ \
657  if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
658  { \
659  CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
660  } \
661  else { \
662  /* Clear Flag in Bank1 */ \
663  if (((__FLAG__) & SR_FLAG_MASK) != RESET) \
664  { \
665  FLASH->SR = ((__FLAG__) & SR_FLAG_MASK); \
666  } \
667  /* Clear Flag in Bank2 */ \
668  if (((__FLAG__) >> 16U) != RESET) \
669  { \
670  FLASH->SR2 = ((__FLAG__) >> 16U); \
671  } \
672  } \
673  } while(0U)
674 #else
675 
683 #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) (FLASH->CR |= (__INTERRUPT__))
684 
693 #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->CR &= ~(__INTERRUPT__))
694 
706 #define __HAL_FLASH_GET_FLAG(__FLAG__) (((__FLAG__) == FLASH_FLAG_OPTVERR) ? \
707  (FLASH->OBR & FLASH_OBR_OPTERR) : \
708  (FLASH->SR & (__FLAG__)))
709 
719 #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { \
720  /* Clear FLASH_FLAG_OPTVERR flag */ \
721  if ((__FLAG__) == FLASH_FLAG_OPTVERR) \
722  { \
723  CLEAR_BIT(FLASH->OBR, FLASH_OBR_OPTERR); \
724  } \
725  else { \
726  /* Clear Flag in Bank1 */ \
727  FLASH->SR = (__FLAG__); \
728  } \
729  } while(0U)
730 
731 #endif
732 
741 /* Exported functions --------------------------------------------------------*/
749 /* IO operation functions *****************************************************/
750 HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
751 HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
752 
760 /* Peripheral Control functions ***********************************************/
761 HAL_StatusTypeDef HAL_FLASHEx_OBErase(void);
762 HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
763 void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
764 uint32_t HAL_FLASHEx_OBGetUserData(uint32_t DATAAdress);
780 #ifdef __cplusplus
781 }
782 #endif
783 
784 #endif /* __STM32F1xx_HAL_FLASH_EX_H */
785 
786 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
stm32f1xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
FLASH_OBProgramInitTypeDef::USERConfig
uint8_t USERConfig
Definition: stm32f1xx_hal_flash_ex.h:213
FLASH_EraseInitTypeDef
FLASH Erase structure definition.
Definition: stm32f1xx_hal_flash_ex.h:170
FLASH_OBProgramInitTypeDef::OptionType
uint32_t OptionType
Definition: stm32f1xx_hal_flash_ex.h:192
FLASH_OBProgramInitTypeDef::RDPLevel
uint8_t RDPLevel
Definition: stm32f1xx_hal_flash_ex.h:204
FLASH_OBProgramInitTypeDef::DATAData
uint8_t DATAData
Definition: stm32f1xx_hal_flash_ex.h:222
FLASH_EraseInitTypeDef::TypeErase
uint32_t TypeErase
Definition: stm32f1xx_hal_flash_ex.h:172
FLASH_OBProgramInitTypeDef::DATAAddress
uint32_t DATAAddress
Definition: stm32f1xx_hal_flash_ex.h:219
FLASH_EraseInitTypeDef::NbPages
uint32_t NbPages
Definition: stm32f1xx_hal_flash_ex.h:182
FLASH_OBProgramInitTypeDef::WRPPage
uint32_t WRPPage
Definition: stm32f1xx_hal_flash_ex.h:198
FLASH_OBProgramInitTypeDef::Banks
uint32_t Banks
Definition: stm32f1xx_hal_flash_ex.h:201
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f1xx_hal_def.h:39
FLASH_EraseInitTypeDef::Banks
uint32_t Banks
Definition: stm32f1xx_hal_flash_ex.h:175
FLASH_EraseInitTypeDef::PageAddress
uint32_t PageAddress
Definition: stm32f1xx_hal_flash_ex.h:178
FLASH_OBProgramInitTypeDef::WRPState
uint32_t WRPState
Definition: stm32f1xx_hal_flash_ex.h:195
FLASH_OBProgramInitTypeDef
FLASH Options bytes program structure definition.
Definition: stm32f1xx_hal_flash_ex.h:190
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