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stm32f1xx_hal_tim.h
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1 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32F1xx_HAL_TIM_H
22 #define STM32F1xx_HAL_TIM_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f1xx_hal_def.h"
30 
39 /* Exported types ------------------------------------------------------------*/
47 typedef struct
48 {
49  uint32_t Prescaler;
52  uint32_t CounterMode;
55  uint32_t Period;
59  uint32_t ClockDivision;
62  uint32_t RepetitionCounter;
71  uint32_t AutoReloadPreload;
73 } TIM_Base_InitTypeDef;
74 
78 typedef struct
79 {
80  uint32_t OCMode;
83  uint32_t Pulse;
86  uint32_t OCPolarity;
89  uint32_t OCNPolarity;
93  uint32_t OCFastMode;
98  uint32_t OCIdleState;
102  uint32_t OCNIdleState;
105 } TIM_OC_InitTypeDef;
106 
110 typedef struct
111 {
112  uint32_t OCMode;
115  uint32_t Pulse;
118  uint32_t OCPolarity;
121  uint32_t OCNPolarity;
125  uint32_t OCIdleState;
129  uint32_t OCNIdleState;
133  uint32_t ICPolarity;
136  uint32_t ICSelection;
139  uint32_t ICFilter;
141 } TIM_OnePulse_InitTypeDef;
142 
146 typedef struct
147 {
148  uint32_t ICPolarity;
151  uint32_t ICSelection;
154  uint32_t ICPrescaler;
157  uint32_t ICFilter;
159 } TIM_IC_InitTypeDef;
160 
164 typedef struct
165 {
166  uint32_t EncoderMode;
169  uint32_t IC1Polarity;
172  uint32_t IC1Selection;
175  uint32_t IC1Prescaler;
178  uint32_t IC1Filter;
181  uint32_t IC2Polarity;
184  uint32_t IC2Selection;
187  uint32_t IC2Prescaler;
190  uint32_t IC2Filter;
192 } TIM_Encoder_InitTypeDef;
193 
197 typedef struct
198 {
199  uint32_t ClockSource;
201  uint32_t ClockPolarity;
203  uint32_t ClockPrescaler;
205  uint32_t ClockFilter;
207 } TIM_ClockConfigTypeDef;
208 
212 typedef struct
213 {
214  uint32_t ClearInputState;
216  uint32_t ClearInputSource;
218  uint32_t ClearInputPolarity;
220  uint32_t ClearInputPrescaler;
222  uint32_t ClearInputFilter;
224 } TIM_ClearInputConfigTypeDef;
225 
229 typedef struct
230 {
231  uint32_t MasterOutputTrigger;
233  uint32_t MasterSlaveMode;
240 } TIM_MasterConfigTypeDef;
241 
245 typedef struct
246 {
247  uint32_t SlaveMode;
249  uint32_t InputTrigger;
251  uint32_t TriggerPolarity;
253  uint32_t TriggerPrescaler;
255  uint32_t TriggerFilter;
258 } TIM_SlaveConfigTypeDef;
259 
265 typedef struct
266 {
267  uint32_t OffStateRunMode;
269  uint32_t OffStateIDLEMode;
271  uint32_t LockLevel;
273  uint32_t DeadTime;
275  uint32_t BreakState;
277  uint32_t BreakPolarity;
279  uint32_t BreakFilter;
281  uint32_t AutomaticOutput;
283 } TIM_BreakDeadTimeConfigTypeDef;
284 
288 typedef enum
289 {
290  HAL_TIM_STATE_RESET = 0x00U,
291  HAL_TIM_STATE_READY = 0x01U,
292  HAL_TIM_STATE_BUSY = 0x02U,
293  HAL_TIM_STATE_TIMEOUT = 0x03U,
294  HAL_TIM_STATE_ERROR = 0x04U
295 } HAL_TIM_StateTypeDef;
296 
300 typedef enum
301 {
302  HAL_TIM_CHANNEL_STATE_RESET = 0x00U,
303  HAL_TIM_CHANNEL_STATE_READY = 0x01U,
304  HAL_TIM_CHANNEL_STATE_BUSY = 0x02U,
305 } HAL_TIM_ChannelStateTypeDef;
306 
310 typedef enum
311 {
312  HAL_DMA_BURST_STATE_RESET = 0x00U,
313  HAL_DMA_BURST_STATE_READY = 0x01U,
314  HAL_DMA_BURST_STATE_BUSY = 0x02U,
315 } HAL_TIM_DMABurstStateTypeDef;
316 
320 typedef enum
321 {
322  HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U,
323  HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U,
324  HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U,
325  HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U,
326  HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U
327 } HAL_TIM_ActiveChannel;
328 
332 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
333 typedef struct __TIM_HandleTypeDef
334 #else
335 typedef struct
336 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
337 {
338  TIM_TypeDef *Instance;
339  TIM_Base_InitTypeDef Init;
340  HAL_TIM_ActiveChannel Channel;
341  DMA_HandleTypeDef *hdma[7];
343  HAL_LockTypeDef Lock;
344  __IO HAL_TIM_StateTypeDef State;
345  __IO HAL_TIM_ChannelStateTypeDef ChannelState[4];
346  __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4];
347  __IO HAL_TIM_DMABurstStateTypeDef DMABurstState;
349 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
350  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
351  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
352  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
353  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
354  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
355  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
356  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
357  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
358  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
359  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
360  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
361  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
362  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);
363  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);
364  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);
365  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
366  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);
367  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
368  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);
369  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
370  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);
371  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);
372  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
373  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);
374  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);
375  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);
376  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);
377 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
378 } TIM_HandleTypeDef;
379 
380 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
381 
384 typedef enum
385 {
386  HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U
387  , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U
388  , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U
389  , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U
390  , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U
391  , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U
392  , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U
393  , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U
394  , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U
395  , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U
396  , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU
397  , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU
398  , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU
399  , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU
400  , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU
401  , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU
402  , HAL_TIM_TRIGGER_CB_ID = 0x10U
403  , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U
405  , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U
406  , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U
407  , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U
408  , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U
409  , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U
410  , HAL_TIM_ERROR_CB_ID = 0x17U
411  , HAL_TIM_COMMUTATION_CB_ID = 0x18U
412  , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U
413  , HAL_TIM_BREAK_CB_ID = 0x1AU
414 } HAL_TIM_CallbackIDTypeDef;
415 
419 typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);
421 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
422 
426 /* End of exported types -----------------------------------------------------*/
427 
428 /* Exported constants --------------------------------------------------------*/
436 #define TIM_CLEARINPUTSOURCE_NONE 0x00000000U
437 #define TIM_CLEARINPUTSOURCE_ETR 0x00000001U
445 #define TIM_DMABASE_CR1 0x00000000U
446 #define TIM_DMABASE_CR2 0x00000001U
447 #define TIM_DMABASE_SMCR 0x00000002U
448 #define TIM_DMABASE_DIER 0x00000003U
449 #define TIM_DMABASE_SR 0x00000004U
450 #define TIM_DMABASE_EGR 0x00000005U
451 #define TIM_DMABASE_CCMR1 0x00000006U
452 #define TIM_DMABASE_CCMR2 0x00000007U
453 #define TIM_DMABASE_CCER 0x00000008U
454 #define TIM_DMABASE_CNT 0x00000009U
455 #define TIM_DMABASE_PSC 0x0000000AU
456 #define TIM_DMABASE_ARR 0x0000000BU
457 #define TIM_DMABASE_RCR 0x0000000CU
458 #define TIM_DMABASE_CCR1 0x0000000DU
459 #define TIM_DMABASE_CCR2 0x0000000EU
460 #define TIM_DMABASE_CCR3 0x0000000FU
461 #define TIM_DMABASE_CCR4 0x00000010U
462 #define TIM_DMABASE_BDTR 0x00000011U
463 #define TIM_DMABASE_DCR 0x00000012U
464 #define TIM_DMABASE_DMAR 0x00000013U
465 
472 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
473 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
474 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
475 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
476 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
477 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
478 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
479 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
487 #define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U
488 #define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P
489 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP)
497 #define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP
498 #define TIM_ETRPOLARITY_NONINVERTED 0x00000000U
506 #define TIM_ETRPRESCALER_DIV1 0x00000000U
507 #define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0
508 #define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1
509 #define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS
517 #define TIM_COUNTERMODE_UP 0x00000000U
518 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
519 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
520 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
521 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
529 #define TIM_CLOCKDIVISION_DIV1 0x00000000U
530 #define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0
531 #define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1
539 #define TIM_OUTPUTSTATE_DISABLE 0x00000000U
540 #define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E
548 #define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U
549 #define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE
558 #define TIM_OCFAST_DISABLE 0x00000000U
559 #define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE
567 #define TIM_OUTPUTNSTATE_DISABLE 0x00000000U
568 #define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE
576 #define TIM_OCPOLARITY_HIGH 0x00000000U
577 #define TIM_OCPOLARITY_LOW TIM_CCER_CC1P
585 #define TIM_OCNPOLARITY_HIGH 0x00000000U
586 #define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP
594 #define TIM_OCIDLESTATE_SET TIM_CR2_OIS1
595 #define TIM_OCIDLESTATE_RESET 0x00000000U
603 #define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N
604 #define TIM_OCNIDLESTATE_RESET 0x00000000U
612 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
613 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
614 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
622 #define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
623 #define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
631 #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0
633 #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1
635 #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S
643 #define TIM_ICPSC_DIV1 0x00000000U
644 #define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0
645 #define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1
646 #define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC
654 #define TIM_OPMODE_SINGLE TIM_CR1_OPM
655 #define TIM_OPMODE_REPETITIVE 0x00000000U
663 #define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0
664 #define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1
665 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
673 #define TIM_IT_UPDATE TIM_DIER_UIE
674 #define TIM_IT_CC1 TIM_DIER_CC1IE
675 #define TIM_IT_CC2 TIM_DIER_CC2IE
676 #define TIM_IT_CC3 TIM_DIER_CC3IE
677 #define TIM_IT_CC4 TIM_DIER_CC4IE
678 #define TIM_IT_COM TIM_DIER_COMIE
679 #define TIM_IT_TRIGGER TIM_DIER_TIE
680 #define TIM_IT_BREAK TIM_DIER_BIE
688 #define TIM_COMMUTATION_TRGI TIM_CR2_CCUS
689 #define TIM_COMMUTATION_SOFTWARE 0x00000000U
697 #define TIM_DMA_UPDATE TIM_DIER_UDE
698 #define TIM_DMA_CC1 TIM_DIER_CC1DE
699 #define TIM_DMA_CC2 TIM_DIER_CC2DE
700 #define TIM_DMA_CC3 TIM_DIER_CC3DE
701 #define TIM_DMA_CC4 TIM_DIER_CC4DE
702 #define TIM_DMA_COM TIM_DIER_COMDE
703 #define TIM_DMA_TRIGGER TIM_DIER_TDE
711 #define TIM_FLAG_UPDATE TIM_SR_UIF
712 #define TIM_FLAG_CC1 TIM_SR_CC1IF
713 #define TIM_FLAG_CC2 TIM_SR_CC2IF
714 #define TIM_FLAG_CC3 TIM_SR_CC3IF
715 #define TIM_FLAG_CC4 TIM_SR_CC4IF
716 #define TIM_FLAG_COM TIM_SR_COMIF
717 #define TIM_FLAG_TRIGGER TIM_SR_TIF
718 #define TIM_FLAG_BREAK TIM_SR_BIF
719 #define TIM_FLAG_CC1OF TIM_SR_CC1OF
720 #define TIM_FLAG_CC2OF TIM_SR_CC2OF
721 #define TIM_FLAG_CC3OF TIM_SR_CC3OF
722 #define TIM_FLAG_CC4OF TIM_SR_CC4OF
730 #define TIM_CHANNEL_1 0x00000000U
731 #define TIM_CHANNEL_2 0x00000004U
732 #define TIM_CHANNEL_3 0x00000008U
733 #define TIM_CHANNEL_4 0x0000000CU
734 #define TIM_CHANNEL_ALL 0x0000003CU
742 #define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1
743 #define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0
744 #define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0
745 #define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1
746 #define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2
747 #define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3
748 #define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED
749 #define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1
750 #define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2
751 #define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF
759 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
760 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
761 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
762 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
763 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
771 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
772 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
773 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
774 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
782 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
783 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
791 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
792 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
793 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
794 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
802 #define TIM_OSSR_ENABLE TIM_BDTR_OSSR
803 #define TIM_OSSR_DISABLE 0x00000000U
811 #define TIM_OSSI_ENABLE TIM_BDTR_OSSI
812 #define TIM_OSSI_DISABLE 0x00000000U
819 #define TIM_LOCKLEVEL_OFF 0x00000000U
820 #define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0
821 #define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1
822 #define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK
830 #define TIM_BREAK_ENABLE TIM_BDTR_BKE
831 #define TIM_BREAK_DISABLE 0x00000000U
839 #define TIM_BREAKPOLARITY_LOW 0x00000000U
840 #define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP
848 #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U
849 #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE
858 #define TIM_TRGO_RESET 0x00000000U
859 #define TIM_TRGO_ENABLE TIM_CR2_MMS_0
860 #define TIM_TRGO_UPDATE TIM_CR2_MMS_1
861 #define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
862 #define TIM_TRGO_OC1REF TIM_CR2_MMS_2
863 #define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)
864 #define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)
865 #define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)
873 #define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM
874 #define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U
882 #define TIM_SLAVEMODE_DISABLE 0x00000000U
883 #define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2
884 #define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)
885 #define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)
886 #define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
894 #define TIM_OCMODE_TIMING 0x00000000U
895 #define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0
896 #define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1
897 #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
898 #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)
899 #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)
900 #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)
901 #define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2
909 #define TIM_TS_ITR0 0x00000000U
910 #define TIM_TS_ITR1 TIM_SMCR_TS_0
911 #define TIM_TS_ITR2 TIM_SMCR_TS_1
912 #define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
913 #define TIM_TS_TI1F_ED TIM_SMCR_TS_2
914 #define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
915 #define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
916 #define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
917 #define TIM_TS_NONE 0x0000FFFFU
925 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED
926 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED
927 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
928 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
929 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
937 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1
938 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2
939 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4
940 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8
948 #define TIM_TI1SELECTION_CH1 0x00000000U
949 #define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S
957 #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U
958 #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U
959 #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U
960 #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U
961 #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U
962 #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U
963 #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U
964 #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U
965 #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U
966 #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U
967 #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U
968 #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U
969 #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U
970 #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U
971 #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U
972 #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U
973 #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U
974 #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U
982 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000)
983 #define TIM_DMA_ID_CC1 ((uint16_t) 0x0001)
984 #define TIM_DMA_ID_CC2 ((uint16_t) 0x0002)
985 #define TIM_DMA_ID_CC3 ((uint16_t) 0x0003)
986 #define TIM_DMA_ID_CC4 ((uint16_t) 0x0004)
987 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005)
988 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006)
996 #define TIM_CCx_ENABLE 0x00000001U
997 #define TIM_CCx_DISABLE 0x00000000U
998 #define TIM_CCxN_ENABLE 0x00000004U
999 #define TIM_CCxN_DISABLE 0x00000000U
1007 /* End of exported constants -------------------------------------------------*/
1008 
1009 /* Exported macros -----------------------------------------------------------*/
1018 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1019 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
1020  (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
1021  (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1022  (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1023  (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1024  (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1025  (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1026  (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1027  (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1028  (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1029  (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
1030  (__HANDLE__)->Base_MspInitCallback = NULL; \
1031  (__HANDLE__)->Base_MspDeInitCallback = NULL; \
1032  (__HANDLE__)->IC_MspInitCallback = NULL; \
1033  (__HANDLE__)->IC_MspDeInitCallback = NULL; \
1034  (__HANDLE__)->OC_MspInitCallback = NULL; \
1035  (__HANDLE__)->OC_MspDeInitCallback = NULL; \
1036  (__HANDLE__)->PWM_MspInitCallback = NULL; \
1037  (__HANDLE__)->PWM_MspDeInitCallback = NULL; \
1038  (__HANDLE__)->OnePulse_MspInitCallback = NULL; \
1039  (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \
1040  (__HANDLE__)->Encoder_MspInitCallback = NULL; \
1041  (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \
1042  (__HANDLE__)->HallSensor_MspInitCallback = NULL; \
1043  (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \
1044  } while(0)
1045 #else
1046 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \
1047  (__HANDLE__)->State = HAL_TIM_STATE_RESET; \
1048  (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1049  (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1050  (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1051  (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1052  (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \
1053  (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \
1054  (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \
1055  (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \
1056  (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \
1057  } while(0)
1058 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1059 
1065 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
1066 
1072 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
1073 
1079 #define __HAL_TIM_DISABLE(__HANDLE__) \
1080  do { \
1081  if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1082  { \
1083  if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1084  { \
1085  (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
1086  } \
1087  } \
1088  } while(0)
1089 
1096 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
1097  do { \
1098  if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
1099  { \
1100  if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
1101  { \
1102  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
1103  } \
1104  } \
1105  } while(0)
1106 
1113 #define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
1114 
1129 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
1130 
1145 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
1146 
1160 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
1161 
1175 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
1176 
1195 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
1196 
1215 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
1216 
1232 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
1233  == (__INTERRUPT__)) ? SET : RESET)
1234 
1249 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
1250 
1258 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
1259 
1266 #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
1267 
1274 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
1275 
1281 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
1282 
1289 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
1290  do{ \
1291  (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
1292  (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
1293  } while(0)
1294 
1300 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
1301 
1312 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
1313  do{ \
1314  (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
1315  (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1316  (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1317  } while(0)
1318 
1327 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1328 
1346 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1347  do{ \
1348  TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1349  TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1350  } while(0)
1351 
1367 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1368  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1369  ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\
1370  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1371  (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)
1372 
1385 #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
1386  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
1387  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
1388  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
1389  ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)))
1390 
1402 #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
1403  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
1404  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
1405  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
1406  ((__HANDLE__)->Instance->CCR4))
1407 
1419 #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1420  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
1421  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
1422  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
1423  ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE))
1424 
1436 #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
1437  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
1438  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
1439  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
1440  ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE))
1441 
1457 #define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
1458  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
1459  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
1460  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
1461  ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE))
1462 
1478 #define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
1479  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
1480  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
1481  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
1482  ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE))
1483 
1492 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
1493 
1505 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
1506 
1522 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1523  do{ \
1524  TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1525  TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1526  }while(0)
1527 
1531 /* End of exported macros ----------------------------------------------------*/
1532 
1533 /* Private constants ---------------------------------------------------------*/
1537 /* The counter of a timer instance is disabled only if all the CCx and CCxN
1538  channels have been disabled */
1539 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
1540 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
1541 
1544 /* End of private constants --------------------------------------------------*/
1545 
1546 /* Private macros ------------------------------------------------------------*/
1550 #define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
1551  ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
1552 
1553 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
1554  ((__BASE__) == TIM_DMABASE_CR2) || \
1555  ((__BASE__) == TIM_DMABASE_SMCR) || \
1556  ((__BASE__) == TIM_DMABASE_DIER) || \
1557  ((__BASE__) == TIM_DMABASE_SR) || \
1558  ((__BASE__) == TIM_DMABASE_EGR) || \
1559  ((__BASE__) == TIM_DMABASE_CCMR1) || \
1560  ((__BASE__) == TIM_DMABASE_CCMR2) || \
1561  ((__BASE__) == TIM_DMABASE_CCER) || \
1562  ((__BASE__) == TIM_DMABASE_CNT) || \
1563  ((__BASE__) == TIM_DMABASE_PSC) || \
1564  ((__BASE__) == TIM_DMABASE_ARR) || \
1565  ((__BASE__) == TIM_DMABASE_RCR) || \
1566  ((__BASE__) == TIM_DMABASE_CCR1) || \
1567  ((__BASE__) == TIM_DMABASE_CCR2) || \
1568  ((__BASE__) == TIM_DMABASE_CCR3) || \
1569  ((__BASE__) == TIM_DMABASE_CCR4) || \
1570  ((__BASE__) == TIM_DMABASE_BDTR))
1571 
1572 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFF00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1573 
1574 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
1575  ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
1576  ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
1577  ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
1578  ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
1579 
1580 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
1581  ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
1582  ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
1583 
1584 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
1585  ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
1586 
1587 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
1588  ((__STATE__) == TIM_OCFAST_ENABLE))
1589 
1590 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
1591  ((__POLARITY__) == TIM_OCPOLARITY_LOW))
1592 
1593 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
1594  ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
1595 
1596 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
1597  ((__STATE__) == TIM_OCIDLESTATE_RESET))
1598 
1599 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
1600  ((__STATE__) == TIM_OCNIDLESTATE_RESET))
1601 
1602 #define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
1603  ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
1604 
1605 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
1606  ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
1607  ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
1608 
1609 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
1610  ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
1611  ((__SELECTION__) == TIM_ICSELECTION_TRC))
1612 
1613 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
1614  ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
1615  ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
1616  ((__PRESCALER__) == TIM_ICPSC_DIV8))
1617 
1618 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
1619  ((__MODE__) == TIM_OPMODE_REPETITIVE))
1620 
1621 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
1622  ((__MODE__) == TIM_ENCODERMODE_TI2) || \
1623  ((__MODE__) == TIM_ENCODERMODE_TI12))
1624 
1625 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1626 
1627 #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1628  ((__CHANNEL__) == TIM_CHANNEL_2) || \
1629  ((__CHANNEL__) == TIM_CHANNEL_3) || \
1630  ((__CHANNEL__) == TIM_CHANNEL_4) || \
1631  ((__CHANNEL__) == TIM_CHANNEL_ALL))
1632 
1633 #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1634  ((__CHANNEL__) == TIM_CHANNEL_2))
1635 
1636 #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
1637  ((__CHANNEL__) == TIM_CHANNEL_2) || \
1638  ((__CHANNEL__) == TIM_CHANNEL_3))
1639 
1640 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1641  ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1642  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
1643  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
1644  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
1645  ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
1646  ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
1647  ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
1648  ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
1649  ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
1650 
1651 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
1652  ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1653  ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
1654  ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
1655  ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
1656 
1657 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
1658  ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
1659  ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
1660  ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
1661 
1662 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1663 
1664 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1665  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1666 
1667 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1668  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1669  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1670  ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
1671 
1672 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1673 
1674 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
1675  ((__STATE__) == TIM_OSSR_DISABLE))
1676 
1677 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
1678  ((__STATE__) == TIM_OSSI_DISABLE))
1679 
1680 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
1681  ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
1682  ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
1683  ((__LEVEL__) == TIM_LOCKLEVEL_3))
1684 
1685 #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
1686 
1687 
1688 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
1689  ((__STATE__) == TIM_BREAK_DISABLE))
1690 
1691 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
1692  ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
1693 
1694 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1695  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
1696 
1697 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
1698  ((__SOURCE__) == TIM_TRGO_ENABLE) || \
1699  ((__SOURCE__) == TIM_TRGO_UPDATE) || \
1700  ((__SOURCE__) == TIM_TRGO_OC1) || \
1701  ((__SOURCE__) == TIM_TRGO_OC1REF) || \
1702  ((__SOURCE__) == TIM_TRGO_OC2REF) || \
1703  ((__SOURCE__) == TIM_TRGO_OC3REF) || \
1704  ((__SOURCE__) == TIM_TRGO_OC4REF))
1705 
1706 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
1707  ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
1708 
1709 #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
1710  ((__MODE__) == TIM_SLAVEMODE_RESET) || \
1711  ((__MODE__) == TIM_SLAVEMODE_GATED) || \
1712  ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
1713  ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1))
1714 
1715 #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \
1716  ((__MODE__) == TIM_OCMODE_PWM2))
1717 
1718 #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
1719  ((__MODE__) == TIM_OCMODE_ACTIVE) || \
1720  ((__MODE__) == TIM_OCMODE_INACTIVE) || \
1721  ((__MODE__) == TIM_OCMODE_TOGGLE) || \
1722  ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
1723  ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE))
1724 
1725 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1726  ((__SELECTION__) == TIM_TS_ITR1) || \
1727  ((__SELECTION__) == TIM_TS_ITR2) || \
1728  ((__SELECTION__) == TIM_TS_ITR3) || \
1729  ((__SELECTION__) == TIM_TS_TI1F_ED) || \
1730  ((__SELECTION__) == TIM_TS_TI1FP1) || \
1731  ((__SELECTION__) == TIM_TS_TI2FP2) || \
1732  ((__SELECTION__) == TIM_TS_ETRF))
1733 
1734 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1735  ((__SELECTION__) == TIM_TS_ITR1) || \
1736  ((__SELECTION__) == TIM_TS_ITR2) || \
1737  ((__SELECTION__) == TIM_TS_ITR3) || \
1738  ((__SELECTION__) == TIM_TS_NONE))
1739 
1740 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
1741  ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
1742  ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
1743  ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
1744  ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
1745 
1746 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
1747  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
1748  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
1749  ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
1750 
1751 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1752 
1753 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
1754  ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
1755 
1756 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
1757  ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
1758  ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
1759  ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
1760  ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
1761  ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
1762  ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
1763  ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
1764  ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
1765  ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
1766  ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
1767  ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
1768  ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
1769  ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
1770  ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
1771  ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
1772  ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
1773  ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
1774 
1775 #define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
1776 
1777 #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)
1778 
1779 #define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU)
1780 
1781 #define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) ((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER)
1782 
1783 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
1784  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
1785  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
1786  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
1787  ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
1788 
1789 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
1790  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
1791  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
1792  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
1793  ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
1794 
1795 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1796  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
1797  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
1798  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
1799  ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
1800 
1801 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
1802  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
1803  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
1804  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P)) :\
1805  ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P)))
1806 
1807 #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\
1808  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
1809  ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
1810  ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
1811  (__HANDLE__)->ChannelState[3])
1812 
1813 #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
1814  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
1815  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
1816  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
1817  ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)))
1818 
1819 #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
1820  (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \
1821  (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \
1822  (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \
1823  (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \
1824  } while(0)
1825 
1826 #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\
1827  (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
1828  ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
1829  ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
1830  (__HANDLE__)->ChannelNState[3])
1831 
1832 #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \
1833  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
1834  ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
1835  ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
1836  ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))
1837 
1838 #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \
1839  (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \
1840  (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \
1841  (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \
1842  (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \
1843  } while(0)
1844 
1848 /* End of private macros -----------------------------------------------------*/
1849 
1850 /* Include TIM HAL Extended module */
1851 #include "stm32f1xx_hal_tim_ex.h"
1852 
1853 /* Exported functions --------------------------------------------------------*/
1862 /* Time Base functions ********************************************************/
1863 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1864 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1865 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1866 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1867 /* Blocking mode: Polling */
1868 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1869 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1870 /* Non-Blocking mode: Interrupt */
1871 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1872 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1873 /* Non-Blocking mode: DMA */
1874 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1875 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1884 /* Timer Output Compare functions *********************************************/
1885 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1886 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1887 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1888 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1889 /* Blocking mode: Polling */
1890 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1891 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1892 /* Non-Blocking mode: Interrupt */
1893 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1894 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1895 /* Non-Blocking mode: DMA */
1896 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1897 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1906 /* Timer PWM functions ********************************************************/
1907 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1908 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1909 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1910 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1911 /* Blocking mode: Polling */
1912 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1913 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1914 /* Non-Blocking mode: Interrupt */
1915 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1916 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1917 /* Non-Blocking mode: DMA */
1918 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1919 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1928 /* Timer Input Capture functions **********************************************/
1929 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1930 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1931 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1932 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1933 /* Blocking mode: Polling */
1934 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1935 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1936 /* Non-Blocking mode: Interrupt */
1937 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1938 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1939 /* Non-Blocking mode: DMA */
1940 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1941 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1950 /* Timer One Pulse functions **************************************************/
1951 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1952 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1953 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1954 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1955 /* Blocking mode: Polling */
1956 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1957 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1958 /* Non-Blocking mode: Interrupt */
1959 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1960 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1969 /* Timer Encoder functions ****************************************************/
1970 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
1971 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
1972 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
1973 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
1974 /* Blocking mode: Polling */
1975 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1976 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1977 /* Non-Blocking mode: Interrupt */
1978 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1979 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1980 /* Non-Blocking mode: DMA */
1981 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
1982  uint32_t *pData2, uint16_t Length);
1983 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1992 /* Interrupt Handler functions ***********************************************/
1993 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
2002 /* Control functions *********************************************************/
2003 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
2004 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
2005 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
2006 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
2007  uint32_t OutputChannel, uint32_t InputChannel);
2008 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
2009  uint32_t Channel);
2010 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
2011 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
2012 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
2013 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
2014 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2015  uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2016 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2017  uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
2018  uint32_t DataLength);
2019 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2020 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2021  uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
2022 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
2023  uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,
2024  uint32_t DataLength);
2025 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
2026 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
2027 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
2036 /* Callback in non blocking modes (Interrupt and DMA) *************************/
2037 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
2038 void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);
2039 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
2040 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
2041 void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);
2042 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
2043 void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);
2044 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
2045 void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);
2046 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
2047 
2048 /* Callbacks Register/UnRegister functions ***********************************/
2049 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2050 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
2051  pTIM_CallbackTypeDef pCallback);
2052 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
2053 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2054 
2063 /* Peripheral State functions ************************************************/
2064 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
2065 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
2066 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
2067 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
2068 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
2069 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
2070 
2071 /* Peripheral Channel state functions ************************************************/
2072 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim);
2073 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel);
2074 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim);
2082 /* End of exported functions -------------------------------------------------*/
2083 
2084 /* Private functions----------------------------------------------------------*/
2088 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
2089 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
2090 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
2091 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
2092  uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
2093 
2094 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);
2095 void TIM_DMAError(DMA_HandleTypeDef *hdma);
2096 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
2097 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);
2098 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);
2099 
2100 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2101 void TIM_ResetCallback(TIM_HandleTypeDef *htim);
2102 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2103 
2107 /* End of private functions --------------------------------------------------*/
2108 
2117 #ifdef __cplusplus
2118 }
2119 #endif
2120 
2121 #endif /* STM32F1xx_HAL_TIM_H */
2122 
2123 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
stm32f1xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
TIM_HandleTypeDef::DMABurstState
__IO HAL_TIM_DMABurstStateTypeDef DMABurstState
Definition: stm32f1xx_hal_tim.h:347
TIM_HandleTypeDef::Channel
HAL_TIM_ActiveChannel Channel
Definition: stm32f1xx_hal_tim.h:340
TIM_IC_InitTypeDef::ICPrescaler
uint32_t ICPrescaler
Definition: stm32f1xx_hal_tim.h:154
TIM_IC_InitTypeDef::ICFilter
uint32_t ICFilter
Definition: stm32f1xx_hal_tim.h:157
HAL_TIM_ActiveChannel
HAL_TIM_ActiveChannel
HAL Active channel structures definition.
Definition: stm32f1xx_hal_tim.h:320
TIM_MasterConfigTypeDef::MasterOutputTrigger
uint32_t MasterOutputTrigger
Definition: stm32f1xx_hal_tim.h:231
TIM_Encoder_InitTypeDef
TIM Encoder Configuration Structure definition.
Definition: stm32f1xx_hal_tim.h:164
TIM_BreakDeadTimeConfigTypeDef::OffStateIDLEMode
uint32_t OffStateIDLEMode
Definition: stm32f1xx_hal_tim.h:269
TIM_ClockConfigTypeDef::ClockSource
uint32_t ClockSource
Definition: stm32f1xx_hal_tim.h:199
TIM_OnePulse_InitTypeDef::OCNPolarity
uint32_t OCNPolarity
Definition: stm32f1xx_hal_tim.h:121
__DMA_HandleTypeDef
DMA handle Structure definition.
Definition: stm32f1xx_hal_dma.h:111
TIM_OnePulse_InitTypeDef::ICSelection
uint32_t ICSelection
Definition: stm32f1xx_hal_tim.h:136
TIM_IC_InitTypeDef::ICSelection
uint32_t ICSelection
Definition: stm32f1xx_hal_tim.h:151
HAL_TIM_STATE_TIMEOUT
Definition: stm32f1xx_hal_tim.h:293
TIM_ClearInputConfigTypeDef::ClearInputPrescaler
uint32_t ClearInputPrescaler
Definition: stm32f1xx_hal_tim.h:220
HAL_TIM_DMABurstStateTypeDef
HAL_TIM_DMABurstStateTypeDef
DMA Burst States definition.
Definition: stm32f1xx_hal_tim.h:310
TIM_Base_InitTypeDef
TIM Time base Configuration Structure definition.
Definition: stm32f1xx_hal_tim.h:47
TIM_MasterConfigTypeDef::MasterSlaveMode
uint32_t MasterSlaveMode
Definition: stm32f1xx_hal_tim.h:233
TIM_BreakDeadTimeConfigTypeDef::OffStateRunMode
uint32_t OffStateRunMode
Definition: stm32f1xx_hal_tim.h:267
TIM_Base_InitTypeDef::CounterMode
uint32_t CounterMode
Definition: stm32f1xx_hal_tim.h:52
TIM_Encoder_InitTypeDef::IC2Filter
uint32_t IC2Filter
Definition: stm32f1xx_hal_tim.h:190
TIM_Encoder_InitTypeDef::IC1Filter
uint32_t IC1Filter
Definition: stm32f1xx_hal_tim.h:178
TIM_ClearInputConfigTypeDef::ClearInputPolarity
uint32_t ClearInputPolarity
Definition: stm32f1xx_hal_tim.h:218
TIM_HandleTypeDef::Init
TIM_Base_InitTypeDef Init
Definition: stm32f1xx_hal_tim.h:339
TIM_BreakDeadTimeConfigTypeDef::DeadTime
uint32_t DeadTime
Definition: stm32f1xx_hal_tim.h:273
TIM_OC_InitTypeDef
TIM Output Compare Configuration Structure definition.
Definition: stm32f1xx_hal_tim.h:78
TIM_SlaveConfigTypeDef::TriggerPrescaler
uint32_t TriggerPrescaler
Definition: stm32f1xx_hal_tim.h:253
TIM_OC_InitTypeDef::OCPolarity
uint32_t OCPolarity
Definition: stm32f1xx_hal_tim.h:86
TIM_Encoder_InitTypeDef::IC1Polarity
uint32_t IC1Polarity
Definition: stm32f1xx_hal_tim.h:169
TIM_IC_InitTypeDef
TIM Input Capture Configuration Structure definition.
Definition: stm32f1xx_hal_tim.h:146
TIM_OnePulse_InitTypeDef::OCNIdleState
uint32_t OCNIdleState
Definition: stm32f1xx_hal_tim.h:129
TIM_OnePulse_InitTypeDef
TIM One Pulse Mode Configuration Structure definition.
Definition: stm32f1xx_hal_tim.h:110
TIM_Base_InitTypeDef::ClockDivision
uint32_t ClockDivision
Definition: stm32f1xx_hal_tim.h:59
TIM_Base_InitTypeDef::Period
uint32_t Period
Definition: stm32f1xx_hal_tim.h:55
HAL_TIM_ACTIVE_CHANNEL_4
Definition: stm32f1xx_hal_tim.h:325
HAL_TIM_STATE_READY
Definition: stm32f1xx_hal_tim.h:291
TIM_ClockConfigTypeDef::ClockFilter
uint32_t ClockFilter
Definition: stm32f1xx_hal_tim.h:205
TIM_OnePulse_InitTypeDef::OCPolarity
uint32_t OCPolarity
Definition: stm32f1xx_hal_tim.h:118
HAL_DMA_BURST_STATE_BUSY
Definition: stm32f1xx_hal_tim.h:314
HAL_TIM_ACTIVE_CHANNEL_2
Definition: stm32f1xx_hal_tim.h:323
HAL_TIM_ACTIVE_CHANNEL_CLEARED
Definition: stm32f1xx_hal_tim.h:326
TIM_IC_InitTypeDef::ICPolarity
uint32_t ICPolarity
Definition: stm32f1xx_hal_tim.h:148
TIM_Base_InitTypeDef::AutoReloadPreload
uint32_t AutoReloadPreload
Definition: stm32f1xx_hal_tim.h:71
HAL_TIM_ACTIVE_CHANNEL_3
Definition: stm32f1xx_hal_tim.h:324
TIM_ClockConfigTypeDef::ClockPolarity
uint32_t ClockPolarity
Definition: stm32f1xx_hal_tim.h:201
TIM_OC_InitTypeDef::OCNPolarity
uint32_t OCNPolarity
Definition: stm32f1xx_hal_tim.h:89
TIM_Encoder_InitTypeDef::IC2Prescaler
uint32_t IC2Prescaler
Definition: stm32f1xx_hal_tim.h:187
TIM_Encoder_InitTypeDef::IC1Prescaler
uint32_t IC1Prescaler
Definition: stm32f1xx_hal_tim.h:175
__IO
#define __IO
Definition: core_armv8mbl.h:196
TIM_ClockConfigTypeDef
Clock Configuration Handle Structure definition.
Definition: stm32f1xx_hal_tim.h:197
TIM_BreakDeadTimeConfigTypeDef::LockLevel
uint32_t LockLevel
Definition: stm32f1xx_hal_tim.h:271
TIM_OnePulse_InitTypeDef::Pulse
uint32_t Pulse
Definition: stm32f1xx_hal_tim.h:115
TIM_BreakDeadTimeConfigTypeDef::BreakPolarity
uint32_t BreakPolarity
Definition: stm32f1xx_hal_tim.h:277
TIM_ClearInputConfigTypeDef::ClearInputSource
uint32_t ClearInputSource
Definition: stm32f1xx_hal_tim.h:216
TIM_SlaveConfigTypeDef::SlaveMode
uint32_t SlaveMode
Definition: stm32f1xx_hal_tim.h:247
TIM_ClearInputConfigTypeDef::ClearInputState
uint32_t ClearInputState
Definition: stm32f1xx_hal_tim.h:214
TIM_BreakDeadTimeConfigTypeDef::BreakFilter
uint32_t BreakFilter
Definition: stm32f1xx_hal_tim.h:279
HAL_TIM_STATE_BUSY
Definition: stm32f1xx_hal_tim.h:292
HAL_DMA_BURST_STATE_RESET
Definition: stm32f1xx_hal_tim.h:312
TIM_BreakDeadTimeConfigTypeDef::AutomaticOutput
uint32_t AutomaticOutput
Definition: stm32f1xx_hal_tim.h:281
HAL_TIM_PeriodElapsedCallback
void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
Period elapsed callback in non blocking mode.
Definition: main.c:165
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32f1xx_hal_def.h:50
HAL_TIM_StateTypeDef
HAL_TIM_StateTypeDef
HAL State structures definition.
Definition: stm32f1xx_hal_tim.h:288
TIM_BreakDeadTimeConfigTypeDef::BreakState
uint32_t BreakState
Definition: stm32f1xx_hal_tim.h:275
HAL_TIM_CHANNEL_STATE_RESET
Definition: stm32f1xx_hal_tim.h:302
TIM_Encoder_InitTypeDef::IC1Selection
uint32_t IC1Selection
Definition: stm32f1xx_hal_tim.h:172
TIM_SlaveConfigTypeDef::InputTrigger
uint32_t InputTrigger
Definition: stm32f1xx_hal_tim.h:249
TIM_OC_InitTypeDef::OCNIdleState
uint32_t OCNIdleState
Definition: stm32f1xx_hal_tim.h:102
HAL_TIM_STATE_RESET
Definition: stm32f1xx_hal_tim.h:290
TIM_SlaveConfigTypeDef
TIM Slave configuration Structure definition.
Definition: stm32f1xx_hal_tim.h:245
stm32f1xx_hal_tim_ex.h
Header file of TIM HAL Extended module.
TIM_OC_InitTypeDef::Pulse
uint32_t Pulse
Definition: stm32f1xx_hal_tim.h:83
TIM_OnePulse_InitTypeDef::ICFilter
uint32_t ICFilter
Definition: stm32f1xx_hal_tim.h:139
TIM_Encoder_InitTypeDef::EncoderMode
uint32_t EncoderMode
Definition: stm32f1xx_hal_tim.h:166
TIM_Encoder_InitTypeDef::IC2Selection
uint32_t IC2Selection
Definition: stm32f1xx_hal_tim.h:184
TIM_OC_InitTypeDef::OCMode
uint32_t OCMode
Definition: stm32f1xx_hal_tim.h:80
TIM_Base_InitTypeDef::Prescaler
uint32_t Prescaler
Definition: stm32f1xx_hal_tim.h:49
TIM_TypeDef
TIM Timers.
Definition: stm32f103xb.h:477
TIM_Encoder_InitTypeDef::IC2Polarity
uint32_t IC2Polarity
Definition: stm32f1xx_hal_tim.h:181
TIM_OnePulse_InitTypeDef::OCIdleState
uint32_t OCIdleState
Definition: stm32f1xx_hal_tim.h:125
TIM_HandleTypeDef
TIM Time Base Handle Structure definition.
Definition: stm32f1xx_hal_tim.h:335
TIM_MasterConfigTypeDef
TIM Master configuration Structure definition.
Definition: stm32f1xx_hal_tim.h:229
TIM_ClearInputConfigTypeDef::ClearInputFilter
uint32_t ClearInputFilter
Definition: stm32f1xx_hal_tim.h:222
TIM_ClearInputConfigTypeDef
TIM Clear Input Configuration Handle Structure definition.
Definition: stm32f1xx_hal_tim.h:212
HAL_TIM_ChannelStateTypeDef
HAL_TIM_ChannelStateTypeDef
TIM Channel States definition.
Definition: stm32f1xx_hal_tim.h:300
TIM_SlaveConfigTypeDef::TriggerPolarity
uint32_t TriggerPolarity
Definition: stm32f1xx_hal_tim.h:251
TIM_OnePulse_InitTypeDef::ICPolarity
uint32_t ICPolarity
Definition: stm32f1xx_hal_tim.h:133
HAL_TIM_CHANNEL_STATE_READY
Definition: stm32f1xx_hal_tim.h:303
TIM_OnePulse_InitTypeDef::OCMode
uint32_t OCMode
Definition: stm32f1xx_hal_tim.h:112
TIM_ClockConfigTypeDef::ClockPrescaler
uint32_t ClockPrescaler
Definition: stm32f1xx_hal_tim.h:203
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32f1xx_hal_def.h:39
HAL_TIM_ACTIVE_CHANNEL_1
Definition: stm32f1xx_hal_tim.h:322
TIM_HandleTypeDef::State
__IO HAL_TIM_StateTypeDef State
Definition: stm32f1xx_hal_tim.h:344
TIM_SlaveConfigTypeDef::TriggerFilter
uint32_t TriggerFilter
Definition: stm32f1xx_hal_tim.h:255
TIM_OC_InitTypeDef::OCIdleState
uint32_t OCIdleState
Definition: stm32f1xx_hal_tim.h:98
HAL_TIM_CHANNEL_STATE_BUSY
Definition: stm32f1xx_hal_tim.h:304
HAL_TIM_STATE_ERROR
Definition: stm32f1xx_hal_tim.h:294
TIM_BreakDeadTimeConfigTypeDef
TIM Break input(s) and Dead time configuration Structure definition.
Definition: stm32f1xx_hal_tim.h:265
TIM_HandleTypeDef::Instance
TIM_TypeDef * Instance
Definition: stm32f1xx_hal_tim.h:338
TIM_Base_InitTypeDef::RepetitionCounter
uint32_t RepetitionCounter
Definition: stm32f1xx_hal_tim.h:62
TIM_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32f1xx_hal_tim.h:343
TIM_OC_InitTypeDef::OCFastMode
uint32_t OCFastMode
Definition: stm32f1xx_hal_tim.h:93
HAL_DMA_BURST_STATE_READY
Definition: stm32f1xx_hal_tim.h:313
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