rtl Architecture Reference

Architecture rtl of level_filter entity. More...

Processes
pr_shift	( clk_in , rst_in )
	Shift process.

Constants
c_high	std_logic_vector ( count - 2 DOWNTO 0 ) := ( others = > ' 1 ' )
	Constant for all-high.
c_low	std_logic_vector ( count - 2 DOWNTO 0 ) := ( others = > ' 0 ' )
	Constant for all-low.

Signals
history	std_logic_vector ( count - 2 DOWNTO 0 )
	Input history shift register.
state	std_logic
	Current state.

Detailed Description

Architecture rtl of level_filter entity.

Definition at line 29 of file level_filter.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/utility/source/level_filter.vhd