tb Architecture Reference

Architecture tb of sdm_device_tb entity. More...

Functions
string	to_string ( vector: in std_logic_vector )
	Function to create string from std_logic_vector.

Processes
pr_clock	( )
	Clock generator process.
pr_stimulus	( )
	Stimulus process to drive SDM unit under test.

Use Clauses
rst
	Reset input to sdm_device.

Constants
c_clk_period	time := 10 ns
	Test bench clock period.
c_stimulus	t_stimulus_array := ( ( name = > " Reset " , rst = > ' 1 ' , data_wr = > X " FFFFFFFF " , data_rd = > X " 00000000 " , percent = > ( 0 , 0 , 0 , 0 ) ) , ( name = > " Set 0 , 0 , 0 , 0 " , rst = > ' 0 ' , data_wr = > X " 00000000 " , data_rd = > X " 00000000 " , percent = > ( 0 , 0 , 0 , 0 ) ) , ( name = > " Set 255 , 255 , 255 , 255 " , rst = > ' 0 ' , data_wr = > X " FFFFFFFF " , data_rd = > X " FFFFFFFF " , percent = > ( 100 , 100 , 100 , 100 ) ) , ( name = > " Set 127 , 127 , 127 , 127 " , rst = > ' 0 ' , data_wr = > X " 7F7F7F7F " , data_rd = > X " 7F7F7F7F " , percent = > ( 50 , 50 , 50 , 50 ) ) , ( name = > " Set 0 , 85 , 170 , 255 " , rst = > ' 0 ' , data_wr = > X " FFAA5500 " , data_rd = > X " FFAA5500 " , percent = > ( 0 , 33 , 67 , 100 ) ) , ( name = > " Set 0 , 0 , 0 , 0 " , rst = > ' 0 ' , data_wr = > X " 00000000 " , data_rd = > X " 00000000 " , percent = > ( 0 , 0 , 0 , 0 ) ) )
	Test stimulus.

Types
t_percent_array	( 0 TO 3 ) integer
	Type for percentage array.
t_stimulus_array	array ( natural range <> ) of t_stimulus
	Stimulus array type.

Signals
clk	std_logic
	Clock input to uut.
dat_wr_done	std_logic
	Data write done input to uut.
dat_wr_reg	std_logic_vector ( 31 DOWNTO 0 )
	Data write register input to uut.
dat_rd_reg	std_logic_vector ( 31 DOWNTO 0 )
	Data read register output from uut.
sdm_out	std_logic_vector ( 3 DOWNTO 0 )
	PWM outputs from uut.
on_rst	std_logic
	Reset input to on_percent.
on_percent	t_percent_array
	Percent output from on_percent.

Records
t_stimulus
	Stimulus record type.
name	string ( 1 TO 30 )
	Stimulus name.
data_wr	std_logic_vector ( 31 DOWNTO 0 )
	Write data to sdm_device.
data_rd	std_logic_vector ( 31 DOWNTO 0 )
	Expected read data from sdm_device.
percent	t_percent_array
	Expected sdm percents.

Instantiations
i_uut	sdm_device <Entity sdm_device>
	Instantiate SDM device as uut.
i_on_percent	sim_on_percent <Entity sim_on_percent>
	Generate on_percent measuring entities.

Detailed Description

Architecture tb of sdm_device_tb entity.

Definition at line 20 of file sdm_device_tb.vhd.

Member Function Documentation

pr_clock()

pr_clock

(

)

Clock generator process.

This generates the clk signal and the adv signal

Definition at line 146 of file sdm_device_tb.vhd.

    pr_clock : PROCESS IS
    BEGIN
    
        clk <= '0';
        WAIT FOR c_clk_period / 2;

        clk <= '1';
        WAIT FOR c_clk_period / 2;
        
    END PROCESS pr_clock;

Member Data Documentation

i_on_percent

i_on_percent sim_on_percent

Instantiation

Generate on_percent measuring entities.

Instantiate on_percent

Definition at line 141 of file sdm_device_tb.vhd.

rst

rst

Package

Reset input to sdm_device.

Reset input to uut.

Definition at line 31 of file sdm_device_tb.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/devices/sim/sdm_device_tb.vhd