sim_drv8711 Entity Reference

Simulated drv8711 entity. More...

Inheritance diagram for sim_drv8711:

Entities
sim	architecture
	Architectur sim of entity sim_drv8711. More...

Libraries
ieee
	Using IEEE library.

Use Clauses
std_logic_1164
	Using IEEE standard logic components.
numeric_std
	Using IEE standard numeric components.

Ports
rst_in	in std_logic
	Asynchronous reset.
spi_scs_in	in std_logic
	SPI scs line.
spi_sclk_in	in std_logic
	SPI sclk line.
spi_mosi_in	in std_logic
	SPI mosi line.
spi_miso_out	out std_logic
	SPI miso line.
dat_miso_in	in std_logic_vector ( 15 DOWNTO 0 )
	SPI data to send.
dat_mosi_out	out std_logic_vector ( 15 DOWNTO 0 )
	SPI data received.
step_in	in std_logic
	Step input.
dir_in	in std_logic
	Direction input.
steps_out	out integer
	Steps count.

Detailed Description

Simulated drv8711 entity.

Definition at line 16 of file sim_drv8711.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/devices/sim/sim_drv8711.vhd