sim Architecture Reference

Architecture sim of entity sim_edge_count. More...

Processes
pr_count	( clk_in , rst_in )
	Counting process.

Signals
prev_signal	std_logic
	Previous signal.
prev_ok	std_logic
	Previous signal ok flag.
rise	integer
	Count of rising edges.
fall	integer
	Count of falling edges.

Detailed Description

Architecture sim of entity sim_edge_count.

Definition at line 27 of file sim_edge_count.vhd.

Member Function Documentation

pr_count()

pr_count (   clk_in ,   rst_in   )

Process

Counting process.

This process counts the rising and falling edges

Definition at line 39 of file sim_edge_count.vhd.

    BEGIN
    
        IF (rst_in = '1') THEN
            -- Reset counts
            prev_signal <= '0';
            prev_ok     <= '0';
            rise        <= 0;
            fall        <= 0;
        ELSIF (rising_edge(clk_in)) THEN
            -- Detect edges
            IF (prev_ok = '1') THEN
                -- Count rising edges
                IF (prev_signal = '0' AND signal_in = '1') THEN
                    rise <= rise + 1;
                END IF;
                
                -- Count falling edges
                IF (prev_signal = '1' AND signal_in = '0') THEN
                    fall <= fall + 1;
                END IF;
            END IF;
            
            -- Update previous signal
            prev_signal <= signal_in;
            prev_ok     <= '1';
        END IF;
    
    END PROCESS pr_count;

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The documentation for this class was generated from the following file:

• fpga/common/utility/sim/sim_edge_count.vhd