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| #define | FLASH_BASE 0x08000000UL |
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| #define | FLASH_BANK1_END 0x0801FFFFUL |
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| #define | SRAM_BASE 0x20000000UL |
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| #define | PERIPH_BASE 0x40000000UL |
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| #define | SRAM_BB_BASE 0x22000000UL |
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| #define | PERIPH_BB_BASE 0x42000000UL |
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#define | APB1PERIPH_BASE PERIPH_BASE |
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#define | APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) |
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#define | AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
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#define | TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) |
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#define | TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) |
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#define | TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) |
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#define | RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) |
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#define | WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) |
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#define | IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) |
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#define | SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) |
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#define | USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) |
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#define | USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) |
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#define | I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) |
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#define | I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) |
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#define | CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL) |
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#define | BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL) |
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#define | PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) |
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#define | AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL) |
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#define | EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) |
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#define | GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL) |
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#define | GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL) |
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#define | GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL) |
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#define | GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL) |
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#define | GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL) |
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#define | ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) |
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#define | ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL) |
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#define | TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) |
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#define | SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) |
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#define | USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) |
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#define | DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) |
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#define | DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL) |
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#define | DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL) |
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#define | DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL) |
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#define | DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL) |
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#define | DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL) |
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#define | DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL) |
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#define | DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL) |
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#define | RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) |
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#define | CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) |
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| #define | FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) |
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| #define | FLASHSIZE_BASE 0x1FFFF7E0UL |
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| #define | UID_BASE 0x1FFFF7E8UL |
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| #define | OB_BASE 0x1FFFF800UL |
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| #define | DBGMCU_BASE 0xE0042000UL |
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| #define | USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) |
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| #define | USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) |
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