PLL Clock Source

Collaboration diagram for PLL Clock Source:

Macros
#define	RCC_PLLSOURCE_HSI_DIV2   0x00000000U
#define	RCC_PLLSOURCE_HSE   RCC_CFGR_PLLSRC

Detailed Description

Macro Definition Documentation

RCC_PLLSOURCE_HSE

#define RCC_PLLSOURCE_HSE   RCC_CFGR_PLLSRC

HSE clock selected as PLL entry clock source

RCC_PLLSOURCE_HSI_DIV2

#define RCC_PLLSOURCE_HSI_DIV2   0x00000000U

HSI clock divided by 2 selected as PLL entry clock source