Motion FPGA
Motion FPGA for the MachX02-7000HE Breakout Board
Signals | Processes
rtl Architecture Reference

Architecture rtl of clk_div_n entity. More...

Processes

pr_count  ( clk_in , rst_in )
 Clock divider count process.

Signals

count  integer range 0 TO clk_div - 1
 Clock counter.

Detailed Description

Architecture rtl of clk_div_n entity.

Definition at line 34 of file clk_div_n.vhd.

Member Function Documentation

§ pr_count()

pr_count (   clk_in ,
  rst_in  
)
Process

Clock divider count process.

This process handles counting and reset.

Definition at line 44 of file clk_div_n.vhd.

pr_count : PROCESS (clk_in, rst_in) IS
44  BEGIN
45 
46  IF (rst_in = '1') THEN
47  -- Asynchronous aeset
48  count <= 0;
49  div_end_out <= '0';
50  div_pls_out <= '0';
51  ELSIF (rising_edge(clk_in)) THEN
52  -- Default pulse to low
53  div_pls_out <= '0';
54 
55  -- Handle conditional advance
56  IF (div_clr_in = '1') THEN
57  -- Synchronous clear
58  count <= 0;
59  div_end_out <= '0';
60  ELSIF (div_adv_in = '1') THEN
61  IF (count = clk_div - 1) THEN
62  -- Handle roll-over
63  count <= 0;
64  div_end_out <= '1';
65  div_pls_out <= '1';
66  ELSE
67  -- Handle normal advance
68  count <= count + 1;
69  div_end_out <= '0';
70  END IF;
71  END IF;
72  END IF;
73 
74  END PROCESS pr_count;
75 
clk_div_n.div_pls_out
out div_pls_outstd_logic
Divider pulse flag.
Definition: clk_div_n.vhd:30
clk_div_n.div_end_out
out div_end_outstd_logic
Divider end flag.
Definition: clk_div_n.vhd:28
clk_div_n.clk_in
in clk_instd_logic
Clock.
Definition: clk_div_n.vhd:24
clk_div_n.div_adv_in
in div_adv_instd_logic
Divider advance flag.
Definition: clk_div_n.vhd:27
clk_div_n.rtl.count
integer range 0 TO clk_div- 1 count
Clock counter.
Definition: clk_div_n.vhd:37
clk_div_n.clk_div
clk_divinteger range 2 TO integer'high:= 4
Divider amount.
Definition: clk_div_n.vhd:22
clk_div_n.div_clr_in
in div_clr_instd_logic
Divider clear flag.
Definition: clk_div_n.vhd:26
clk_div_n.rst_in
in rst_instd_logic
Asynchronous reset.
Definition: clk_div_n.vhd:25
The documentation for this class was generated from the following file: