tb Architecture Reference

Architecture tb of clk_div_n_tb entity. More...

Processes
pr_clock	( )
	Clock generation process.
pr_stimulus	( )
	Stimulus process to drive PWM unit under test.

Constants
c_clk_period	time := 10 ns
	Test bench clock period.
c_stimulus	t_stimulus_array := ( ( name = > " Hold in reset " , rst = > " 11111111 " , div_clr = > " 00000000 " , div_adv = > " 00000000 " , div_end = > " 00000000 " , div_pls = > " 00000000 " ) , ( name = > " Not enabled " , rst = > " 00000000 " , div_clr = > " 00000000 " , div_adv = > " 00000000 " , div_end = > " 00000000 " , div_pls = > " 00000000 " ) , ( name = > " Clear " , rst = > " 00000000 " , div_clr = > " 11111111 " , div_adv = > " 00000000 " , div_end = > " 00000000 " , div_pls = > " 00000000 " ) , ( name = > " Normal counting 1 " , rst = > " 00000000 " , div_clr = > " 00000000 " , div_adv = > " 11111111 " , div_end = > " 00010001 " , div_pls = > " 00010001 " ) , ( name = > " Normal counting 2 " , rst = > " 00000000 " , div_clr = > " 00000000 " , div_adv = > " 11111111 " , div_end = > " 00010001 " , div_pls = > " 00010001 " ) , ( name = > " Freezing count " , rst = > " 00000000 " , div_clr = > " 00000000 " , div_adv = > " 00001111 " , div_end = > " 11110001 " , div_pls = > " 00000001 " ) , ( name = > " Count and clear " , rst = > " 00000000 " , div_clr = > " 00110000 " , div_adv = > " 11111111 " , div_end = > " 00000001 " , div_pls = > " 00000001 " ) )
	Test stimulus.

Types
t_stimulus_array	array ( natural range <> ) of t_stimulus
	Stimulus array type.

Signals
clk	std_logic
	Clock.
rst	std_logic
	Reset.
div_clr	std_logic
	Divider clear to uut.
div_adv	std_logic
	Divider advance to uut.
div_end	std_logic
	Divider end from uut.
div_pls	std_logic
	Divider pulse from uut.

Records
t_stimulus
	Stimulus record type.
name	string ( 1 TO 20 )
	Stimulus name.
rst	std_logic_vector ( 0 TO 7 )
	rst input to uut
div_clr	std_logic_vector ( 0 TO 7 )
	div_clr input to uut
div_adv	std_logic_vector ( 0 TO 7 )
	div_adv input to uut
div_end	std_logic_vector ( 0 TO 7 )
	div_end expected from uut
div_pls	std_logic_vector ( 0 TO 7 )
	div_pls expected from uut

Instantiations
i_uut	clk_div_n <Entity clk_div_n>
	Instantiate clk_div_n as unit under test.

Detailed Description

Architecture tb of clk_div_n_tb entity.

Definition at line 20 of file clk_div_n_tb.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/utility/sim/clk_div_n_tb.vhd