delay_line Entity Reference

Delay-line entity. More...

Inheritance diagram for delay_line:

Entities
rtl	architecture
	Architecture rtl of delay_line entity. More...

Libraries
ieee
	Using IEEE library.

Use Clauses
std_logic_1164
	Using IEEE standard logic components.

Generics
count	natural range 1 TO natural ' high := 2
	Delay length.

Ports
clk_in	in std_logic
	Clock.
rst_in	in std_logic
	Asynchronous reset.
sig_in	in std_logic
	Input signal.
sig_out	out std_logic
	Output signal.

Detailed Description

Delay-line entity.

This entity acts as a delay-line for signals

Definition at line 15 of file delay_line.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/utility/source/delay_line.vhd