rtl Architecture Reference

Architecture rtl of delay_line entity. More...

Processes
pr_shift	( clk_in , rst_in )
	Shift process.

Signals
history	std_logic_vector ( count - 1 DOWNTO 0 )
	Input history shift register.
state	std_logic
	Current state.

Detailed Description

Architecture rtl of delay_line entity.

Definition at line 28 of file delay_line.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/utility/source/delay_line.vhd