tb Architecture Reference

Architecture tb of delay_line_tb entity. More...

Processes
pr_clock	( )
	Clock generation process.
pr_stimulus	( )
	Stimulus process to drive PWM unit under test.

Constants
c_clk_period	time := 10 ns
	Test bench clock period.
c_stimulus	t_stimulus_array := ( ( name = > " Hold in reset " , rst = > " 11111111 " , sig_in = > " 01010101 " , sig_out = > " 00000000 " ) , ( name = > " Active " , rst = > " 00000000 " , sig_in = > " 01111000 " , sig_out = > " 00011110 " ) )
	Test stimulus.

Types
t_stimulus_array	array ( natural range <> ) of t_stimulus
	Stimulus array type.

Signals
clk	std_logic
	Clock.
rst	std_logic
	Reset.
sig_in	std_logic
	Signal in to uut.
sig_out	std_logic
	Signal out from uut.

Records
t_stimulus
	Stimulus record type.
name	string ( 1 TO 20 )
	Stimulus name.
rst	std_logic_vector ( 0 TO 7 )
	rst input to uut
sig_in	std_logic_vector ( 0 TO 7 )
	signal input
sig_out	std_logic_vector ( 0 TO 7 )
	Expected signal output.

Instantiations
i_uut	delay_line <Entity delay_line>
	Instantiate delay_line as unit under test.

Detailed Description

Architecture tb of delay_line_tb entity.

Definition at line 17 of file delay_line_tb.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/utility/sim/delay_line_tb.vhd