drv8711_spi Entity Reference
DRV8711 spi entity. More...
Inheritance diagram for drv8711_spi:
Entities | |
| rtl | architecture |
| Architecture rtl of drv8711_spi entity. More... | |
Libraries | |
| ieee | |
| Using IEEE library. | |
Use Clauses | |
| std_logic_1164 | |
| Using IEEE standard logic components. | |
Ports | |
| clk_in | in std_logic |
| Clock. | |
| rst_in | in std_logic |
| Asynchronous reset. | |
| data_send_in | in std_logic_vector ( 15 DOWNTO 0 ) |
| Data to send. | |
| data_recv_out | out std_logic_vector ( 15 DOWNTO 0 ) |
| Data received. | |
| xfer_adv_in | in std_logic |
| Transfer advance flag. | |
| xfer_start_in | in std_logic |
| Transfer start flag. | |
| xfer_done_out | out std_logic |
| Transfer done flag. | |
| spi_scs_out | out std_logic |
| SPI chip-select. | |
| spi_sclk_out | out std_logic |
| SPI clock. | |
| spi_mosi_out | out std_logic |
| SPI mosi. | |
| spi_miso_in | in std_logic |
| SPI miso. | |
Detailed Description
DRV8711 spi entity.
Definition at line 13 of file drv8711_spi.vhd.
The documentation for this class was generated from the following file:
- fpga/common/devices/source/drv8711_spi.vhd
