rtl Architecture Reference

Architecture rtl of drv8711_spi entity. More...

Processes
pr_transfer	( clk_in , rst_in )

Types
t_xfer_state	( xfer_idle , xfer_start_delay , xfer_data , xfer_end_delay , xfer_finish )

Signals
xfer_state	t_xfer_state
xfer_start	std_logic
data_send	std_logic_vector ( 15 DOWNTO 0 )
data_recv	std_logic_vector ( 15 DOWNTO 0 )
spi_count	integer range 0 TO 15
spi_sclk	std_logic

Detailed Description

Architecture rtl of drv8711_spi entity.

Definition at line 30 of file drv8711_spi.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/devices/source/drv8711_spi.vhd