rtl Architecture Reference

Architecture rtl of edge_detect entity. More...

Processes
pr_detect	( clk_in , rst_in )
	Edge detection process.

Signals
prev_ok	std_logic
	Previous input valid signal.
prev	std_logic
	Previous input signal.

Detailed Description

Architecture rtl of edge_detect entity.

Definition at line 27 of file edge_detect.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/utility/source/edge_detect.vhd