tb Architecture Reference

Architecture tb of edge_detect_tb entity. More...

Processes
pr_clock	( )
	Clock generation process.
pr_stimulus	( )
	Stimulus process to drive PWM unit under test.

Constants
c_clk_period	time := 10 ns
	Test bench clock period.
c_stimulus	t_stimulus_array := ( ( name = > " Hold in reset " , rst = > " 11111111 " , sig = > " 00000000 " , rise = > " 00000000 " , fall = > " 00000000 " ) , ( name = > " Wake low then edges " , rst = > " 10000000 " , sig = > " 00011100 " , rise = > " 00010000 " , fall = > " 00000010 " ) , ( name = > " Wake high then edges " , rst = > " 10000000 " , sig = > " 11100011 " , rise = > " 00000010 " , fall = > " 00010000 " ) )
	Test stimulus.

Types
t_stimulus_array	array ( natural range <> ) of t_stimulus
	Stimulus array type.

Signals
clk	std_logic
	Signal 'clk' to uut.
rst	std_logic
	Signal 'rst' to uut.
sig	std_logic
	Signal 'sig' to uut.
rise	std_logic
	Signal 'rise' from uut.
fall	std_logic
	Signal 'fall' from uut.

Records
t_stimulus
	Stimulus record type.
name	string ( 1 TO 20 )
	Stimulus name.
rst	std_logic_vector ( 0 TO 7 )
	rst input to uut
sig	std_logic_vector ( 0 TO 7 )
	sig input to uut
rise	std_logic_vector ( 0 TO 7 )
	rise expected from uut
fall	std_logic_vector ( 0 TO 7 )
	fall expected from uut

Instantiations
i_uut	edge_detect <Entity edge_detect>
	Instantiate edge_detect as unit under test.

Detailed Description

Architecture tb of edge_detect_tb entity.

Definition at line 17 of file edge_detect_tb.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/utility/sim/edge_detect_tb.vhd