pwm Entity Reference
PWM entity. More...
Inheritance diagram for pwm:
Entities | |
| rtl | architecture |
| Architecture rtl of pwm entity. More... | |
Libraries | |
| ieee | |
| Using IEEE library. | |
Use Clauses | |
| std_logic_1164 | |
| Using IEEE standard logic components. | |
| numeric_std | |
| Using IEE standard numeric components. | |
Generics | |
| bit_width | natural range 2 TO 32 := 8 |
| PWM width. | |
Ports | |
| clk_in | in std_logic |
| Clock. | |
| rst_in | in std_logic |
| Asynchronous reset. | |
| pwm_adv_in | in std_logic |
| PWM Advance flag. | |
| pwm_duty_in | in std_logic_vector ( bit_width - 1 DOWNTO 0 ) |
| PWM duty cycle. | |
| pwm_out | out std_logic |
| PWM output. | |
Detailed Description
PWM entity.
PWM Entity
This entity is a configurable PWM generator. The 'count_max' determines how high the PWM will count to before rolling over. The 'pwm_duty' input determines when the PWM will turn off in the cycle.
A pwm_duty of '0' causes the pwm to stay low all the time; where-as a pwm_duty of 'count_max + 1' causes the pwm to stay high all the time.
The documentation for this class was generated from the following file:
- fpga/common/utility/source/pwm.vhd
