rtl Architecture Reference

Architecture rtl of pwm entity. More...

Processes
pr_pwm	( clk_in , rst_in )
	Process for PWM generation.

Constants
c_count_max	natural := ( 2 ** bit_width ) - 2
	Maximum PWM count.

Signals
count	unsigned ( pwm_duty_in ' range )
	PWM count.
state	std_logic
	PWM state.

Detailed Description

Architecture rtl of pwm entity.

Definition at line 39 of file pwm.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/utility/source/pwm.vhd