sdm Entity Reference

Using IEE standard numeric components Sigma-Delta modulator entityThis entity is a configurable first-order sigma-delta modulator with a configurable bit-width. More...

Inheritance diagram for sdm:

Entities
rtl	architecture
	Architecture rtl of sdm entity. More...

Libraries
ieee
	Drive quadrature output.

Use Clauses
std_logic_1164
	Using IEEE library.
numeric_std
	Using IEEE standard logic components.

Generics
bit_width	integer range 1 TO 32 := 8
	Bit width.

Ports
clk_in	in std_logic
	Clock.
rst_in	in std_logic
	Asynchronous reset.
sdm_level_in	in std_logic_vector ( bit_width - 1 DOWNTO 0 )
	Modulator level.
sdm_out	out std_logic
	Modulator output.

Detailed Description

Using IEE standard numeric components Sigma-Delta modulator entity

This entity is a configurable first-order sigma-delta modulator with a configurable bit-width.

Definition at line 19 of file sdm.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/utility/source/sdm.vhd