rtl Architecture Reference

Architecture rtl of sdm_device entity. More...

Processes
pr_write	( clk_in , rst_in )
	Process to handle writes and resets.
pr_read	( clk_in )
	Process to handle reads.

Types
sdm_level_set	( 3 DOWNTO 0 ) std_logic_vector ( 7 DOWNTO 0 )
	Array type of four levels.

Signals
sdm_level	sdm_level_set
	Levels array.

Instantiations
i_sdm	sdm <Entity sdm>
	Generate four Sigma-Delta modulators.

Detailed Description

Architecture rtl of sdm_device entity.

Definition at line 32 of file sdm_device.vhd.

Member Data Documentation

i_sdm

i_sdm sdm

Instantiation

Generate four Sigma-Delta modulators.

Generate Sigma-Delta modulator instance

Definition at line 57 of file sdm_device.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/devices/source/sdm_device.vhd