tb Architecture Reference

Architecture tb of sdm_tb entity. More...

Processes
pr_clock	( )
	Clock generation process.
pr_stimulus	( )
	Stimulus process to drive PWM unit under test.

Use Clauses
rst
	rst input to uut
sdm_level
	sdm_level input to uut

Constants
c_clk_period	time := 10 ns
	Test bench clock period.
c_stimulus	t_stimulus_array := ( ( name = > " Hold in reset " , rst = > ' 1 ' , sdm_level = > B " 11 " , percent = > 0 ) , ( name = > " Running value 0 " , rst = > ' 0 ' , sdm_level = > B " 00 " , percent = > 0 ) , ( name = > " Running value 1 " , rst = > ' 0 ' , sdm_level = > B " 01 " , percent = > 25 ) , ( name = > " Running value 2 " , rst = > ' 0 ' , sdm_level = > B " 10 " , percent = > 50 ) , ( name = > " Running value 3 " , rst = > ' 0 ' , sdm_level = > B " 11 " , percent = > 75 ) )
	Test stimulus.

Types
t_stimulus_array	array ( natural range <> ) of t_stimulus
	Stimulus array type.

Signals
clk	std_logic
	Clock input to sdm uut.
sdm_out	std_logic
	Modulator output from sdm uut.
on_rst	std_logic
	Reset input to on_percent.
on_percent	integer
	Percent output from on_percent.

Records
t_stimulus
	Stimulus record type.
name	string ( 1 TO 20 )
	Stimulus name.
percent	integer
	Expected on-percent from uut.

Instantiations
i_uut	sdm <Entity sdm>
	Instantiate sigma-delta modulator as unit under test.
i_on_percent	sim_on_percent <Entity sim_on_percent>
	Instantiate on_percent.

Detailed Description

Architecture tb of sdm_tb entity.

Definition at line 20 of file sdm_tb.vhd.

Member Data Documentation

rst

rst

Package

rst input to uut

Reset input to sdm uut.

Definition at line 28 of file sdm_tb.vhd.

sdm_level

sdm_level

Package

sdm_level input to uut

Level input to sdm uut.

Definition at line 29 of file sdm_tb.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/utility/sim/sdm_tb.vhd