sim_spi_master Entity Reference

SPI Master simulation entity. More...

Entities
sim	architecture
	Architecture sim of entity sim_spi_master. More...

Libraries
ieee
	Using IEEE library.

Use Clauses
std_logic_1164
	Using IEEE standard logic components.

Generics
spi_width	natural := 32
	SPI transfer width.
spi_cs_delay	time := 500 ns
	SPI chip-select rise/fall delay.
spi_sclk_period	time := 400 ns
	SPI clock period.

Ports
rst_in	in std_logic
	Asynchronous reset.
spi_cs_out	out std_logic
	SPI chip-select line.
spi_sclk_out	out std_logic
	SPI sclk line.
spi_mosi_out	out std_logic
	SPI mosi line.
spi_miso_in	in std_logic
	SPI miso line.
data_mosi_in	in std_logic_vector ( spi_width - 1 DOWNTO 0 )
	Data to send.
data_miso_out	out std_logic_vector ( spi_width - 1 DOWNTO 0 )
	Data received.
xfer_start_in	in std_logic
	Start transfer flag.
xfer_done_out	out std_logic
	Transfer done flag.

Detailed Description

SPI Master simulation entity.

Definition at line 13 of file sim_spi_master.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/communications/sim/sim_spi_master.vhd