Motion FPGA
Motion FPGA for the MachX02-7000HE Breakout Board
Processes
sim Architecture Reference

Architecture sim of entity sim_spi_master. More...

Processes

pr_xfer  ( )
 SPI transfer process.

Detailed Description

Architecture sim of entity sim_spi_master.

Definition at line 33 of file sim_spi_master.vhd.

Member Function Documentation

§ pr_xfer()

pr_xfer ( )
Process

SPI transfer process.

This process performs SPI transfers when requested by xfer_start.

Definition at line 40 of file sim_spi_master.vhd.

pr_xfer : PROCESS IS
40 
41  VARIABLE v_data_miso : std_logic_vector(spi_width - 1 DOWNTO 0);
42 
43  BEGIN
44 
45  IF (rst_in = '1') THEN
46  -- Reset
47  spi_cs_out <= '1';
48  spi_sclk_out <= '0';
49  spi_mosi_out <= '0';
50  data_miso_out <= (OTHERS => '0');
51  xfer_done_out <= '0';
52 
53  -- Wait for reset to clear
54  WAIT UNTIL rst_in = '0';
55  ELSIF (xfer_start_in = '1') THEN
56  -- Drop chip-select
57  WAIT FOR spi_cs_delay;
58  spi_cs_out <= '0';
59  WAIT FOR spi_cs_delay;
60 
61  -- Transfer all bits
62  FOR b in spi_width - 1 DOWNTO 0 LOOP
63 
64  -- First half of clock
65  spi_mosi_out <= data_mosi_in(b);
66  spi_sclk_out <= '1';
67  WAIT FOR spi_sclk_period / 2;
68 
69  -- Second half of clock
70  v_data_miso(b) := spi_miso_in;
71  spi_sclk_out <= '0';
72  WAIT FOR spi_sclk_period / 2;
73 
74  END LOOP;
75 
76  -- Raise chip-select
77  WAIT FOR spi_cs_delay;
78  spi_cs_out <= '1';
79  WAIT FOR spi_cs_delay;
80 
81  -- Hand-shake transfer complete
82  data_miso_out <= v_data_miso;
83  xfer_done_out <= '1';
84  WAIT UNTIL xfer_start_in = '0';
85  xfer_done_out <= '0';
86  ELSE
87  -- Wait for work
88  WAIT ON rst_in, xfer_start_in;
89  END IF;
90 
91  END PROCESS pr_xfer;
92 
sim_spi_master.spi_mosi_out
out spi_mosi_outstd_logic
SPI mosi line.
Definition: sim_spi_master.vhd:23
sim_spi_master.xfer_start_in
in xfer_start_instd_logic
Start transfer flag.
Definition: sim_spi_master.vhd:27
sim_spi_master.spi_sclk_out
out spi_sclk_outstd_logic
SPI sclk line.
Definition: sim_spi_master.vhd:22
sim_spi_master.data_miso_out
out data_miso_outstd_logic_vector( spi_width- 1 DOWNTO 0)
Data received.
Definition: sim_spi_master.vhd:26
sim_spi_master.spi_sclk_period
spi_sclk_periodtime := 400 ns
SPI clock period.
Definition: sim_spi_master.vhd:18
sim_spi_master.rst_in
in rst_instd_logic
Asynchronous reset.
Definition: sim_spi_master.vhd:20
sim_spi_master.spi_width
spi_widthnatural := 32
SPI transfer width.
Definition: sim_spi_master.vhd:15
sim_spi_master.spi_cs_delay
spi_cs_delaytime := 500 ns
SPI chip-select rise/fall delay.
Definition: sim_spi_master.vhd:16
sim_spi_master.spi_cs_out
out spi_cs_outstd_logic
SPI chip-select line.
Definition: sim_spi_master.vhd:21
sim_spi_master.xfer_done_out
out xfer_done_outstd_logic
Transfer done flag.
Definition: sim_spi_master.vhd:29
sim_spi_master.data_mosi_in
in data_mosi_instd_logic_vector( spi_width- 1 DOWNTO 0)
Data to send.
Definition: sim_spi_master.vhd:25
sim_spi_master.spi_miso_in
in spi_miso_instd_logic
SPI miso line.
Definition: sim_spi_master.vhd:24
The documentation for this class was generated from the following file: