spi_slave Entity Reference

SPI Slave module. More...

Inheritance diagram for spi_slave:

Entities
rtl	architecture
	Architecture rtl of spi_slave entity. More...

Libraries
ieee
	Using IEEE library.

Use Clauses
std_logic_1164
	Using IEEE standard logic components.

Generics
size	natural range 1 TO natural ' high
	Size of the SPI data.

Ports
clk_in	in std_logic
	Clock.
rst_in	in std_logic
	Asynchronous reset.
spi_cs_in	in std_logic
	SPI Chip-select.
spi_sclk_in	in std_logic
	SPI Clock.
spi_mosi_in	in std_logic
	SPI MOSI.
spi_miso_out	out std_logic
	SPI MISO.
dat_rd_reg_in	in std_logic_vector ( size - 1 DOWNTO 0 )
	Data Read Register value.
dat_wr_reg_out	out std_logic_vector ( size - 1 DOWNTO 0 )
	Data Write Register value.
dat_wr_done_out	out std_logic
	Data Write Done flag.

Detailed Description

SPI Slave module.

This SPI slave works with SPI signals using the following format:

• CPOL = 0: sclk low when idle.
• CPHA = 1: data written on first edge and read on second.

This SPI slave provides a simple SPI shift register for reading/writing data. At the start of a transfer when the CS goes low the 'dat_rd_reg_in' is latched for transmitting.

At the end of transfer when the CS goes high the module loads the received data into 'dat_wr_reg_out' then drives the 'dat_wr_done_out' signal for one clock indicating new data has been written to the SPI block.

Definition at line 25 of file spi_slave.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/communications/source/spi_slave.vhd