rtl Architecture Reference

Architecture rtl of spi_slave entity. More...

Processes
pr_shift	( clk_in , rst_in )
	SPI shift process.

Signals
in_xfer	std_logic
	Flag indicating a transfer is in progress.
shift	std_logic_vector ( size - 1 DOWNTO 0 )
	SPI shift register.
sclk_rise	std_logic
	Signal indicating rise of sclk.
sclk_fall	std_logic
	Signal indicating fall fo sclk.

Instantiations
i_sclk_edge	edge_detect <Entity edge_detect>
	Edge detector for SCLK signal.

Detailed Description

Architecture rtl of spi_slave entity.

Definition at line 43 of file spi_slave.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/communications/source/spi_slave.vhd