tb Architecture Reference

Architecture tb of spi_slave_tb entity. More...

Processes
pr_clock	( )
	Clock generation process.
pr_stimulus	( )
	Stimulus process.

Constants
c_clk_period	time := 100 ns
	Clock period.

Signals
clk	std_logic
	Clock.
rst	std_logic
	Asynchronous reset.
spi_cs	std_logic
	SPI chip select input to uut.
spi_sclk	std_logic
	SPI clock input to uut.
spi_mosi	std_logic
	SPI MOSI input to uut.
spi_miso	std_logic
	SPI MISO output from uut.
dat_rd_reg	std_logic_vector ( 31 DOWNTO 0 )
	Data read register input to uut.
dat_wr_reg	std_logic_vector ( 31 DOWNTO 0 )
	Data write register output from uut.
dat_wr_done	std_logic
	Data write done output from uut.
mosi_wr	std_logic_vector ( 31 DOWNTO 0 )
	SPI MOSI test pattern to drive into uut.
miso_rd	std_logic_vector ( 31 DOWNTO 0 )
	SPI MISO output pattern driven from uut.

Instantiations
i_uut	spi_slave <Entity spi_slave>
	Instantiate spi_slave as unit under test.

Detailed Description

Architecture tb of spi_slave_tb entity.

Definition at line 17 of file spi_slave_tb.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/communications/sim/spi_slave_tb.vhd