Step Generator entity. More...

Inheritance diagram for step_generator:

Entities
rtl	architecture
	Architecture rtl of step_generator entity. More...

Use Clauses
std_logic_1164
	Using IEEE standard logic components.
numeric_std
	Using IEE standard numeric components.

Generics
count_wid	integer range 1 TO integer ' high := 4
	Width of count.
delay_wid	integer range 1 TO integer ' high := 6
	Width of delay.

Ports
clk_in	in std_logic
	Clock.
rst_in	in std_logic
	Asynchronous reset.
enable_in	in std_logic
	Generator enable flag.
advance_in	in std_logic
	Advance flag.
count_in	in std_logic_vector ( count_wid - 1 DOWNTO 0 )
	Count of steps.
delay_in	in std_logic_vector ( delay_wid - 1 DOWNTO 0 )
	Delay between steps.
step_out	out std_logic
	Step output.

Detailed Description

Step Generator entity.

This step-generator entity produces a number of step-pulses. This is commonly used for devices such as stepper motor driver chips.

When the user asserts the enable_in signal the step-generation begins. The user can de-assert enable_in to cancel step-generation.

The advance_in flag should be pulsed at the basic step-generation rate. This rate is divided down by the delay_in count to produce the stepping rate.

Definition at line 26 of file step_generator.vhd.

The documentation for this class was generated from the following file:

Entities