rtl Architecture Reference

Architecture rtl of step_generator entity. More...

Processes
pr_step	( clk_in , rst_in )
	Process to generate steps.

Signals
count	unsigned ( count_wid - 1 DOWNTO 0 )
	Current step counter.
delay	unsigned ( delay_wid - 1 DOWNTO 0 )
	Current delay counter.
step	std_logic
	Step state.

Detailed Description

Architecture rtl of step_generator entity.

Definition at line 43 of file step_generator.vhd.

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The documentation for this class was generated from the following file:

• fpga/common/utility/source/step_generator.vhd