Motion FPGA
Motion FPGA for the MachX02-7000HE Breakout Board
quad_decoder.vhd
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1 -------------------------------------------------------------------------------
2 --! @file
3 --! @brief Quadrature decoder module
4 -------------------------------------------------------------------------------
5 
6 --! Using IEEE library
7 LIBRARY ieee;
8 
9 --! Using IEEE standard logic components
10 USE ieee.std_logic_1164.ALL;
11 
12 --! Using IEE standard numeric components
13 USE ieee.numeric_std.ALL;
14 
15 --! @brief Quadrature decoder entity
16 ENTITY quad_decoder IS
17  GENERIC (
18  bit_width : natural := 8 --! Width of the quadrature decoder
19  );
20  PORT (
21  clk_in : IN std_logic; --! Clock
22  rst_in : IN std_logic; --! Asynchronous reset
23  quad_a_in : IN std_logic; --! Quadrature a input
24  quad_b_in : IN std_logic; --! Quadrature b input
25  quad_count_out : OUT unsigned(bit_width - 1 DOWNTO 0) --! Quadrature count output
26  );
27 END ENTITY quad_decoder;
28 
29 --! Architecture rtl of quad_encoder entity
30 ARCHITECTURE rtl OF quad_decoder IS
31 
32  -- Delayed inputs
33  SIGNAL quad_a_old : std_logic; --! Old copy of quad_a
34  SIGNAL quad_b_old : std_logic; --! Old copy of quad_b
35 
36  --! Quadrature count
37  SIGNAL quad_count : unsigned(bit_width - 1 DOWNTO 0);
38 
39 BEGIN
40 
41  --! @brief Process to perform quadrature counting
42  pr_count : PROCESS (clk_in, rst_in) IS
43 
44  VARIABLE v_count_en : std_logic; --! Flag to perform count
45  VARIABLE v_count_dir : std_logic; --! Flag for count direction
46 
47  BEGIN
48 
49  IF (rst_in = '1') THEN
50  -- Reset counter
51  quad_a_old <= '0';
52  quad_b_old <= '0';
53  quad_count <= (OTHERS => '0');
54  ELSIF (rising_edge(clk_in)) THEN
55  -- Evaluate whether to count and in which direction
56  v_count_en := quad_a_in XOR quad_a_old XOR quad_b_in XOR quad_b_old;
57  v_count_dir := quad_a_in XOR quad_b_old;
58 
59  -- Perform counting
60  IF (v_count_en = '1') THEN
61  IF (v_count_dir = '1') THEN
62  quad_count <= quad_count + 1;
63  ELSE
64  quad_count <= quad_count - 1;
65  END IF;
66  END IF;
67 
68  -- Update delayed inputs
71  END IF;
72 
73  END PROCESS pr_count;
74 
75  --! Drive quadrature output
77 
78 END ARCHITECTURE rtl;
_library_ ieeeieee
Using IEEE library.
Definition: pwm.vhd:7
Quadrature decoder entity.
in clk_instd_logic
Clock.
out quad_count_outunsigned( bit_width- 1 DOWNTO 0)
Quadrature count output.
in quad_a_instd_logic
Quadrature a input.
unsigned( bit_width- 1 DOWNTO 0) quad_count
Quadrature count.
bit_widthnatural := 8
Width of the quadrature decoder.
std_logic quad_a_old
Old copy of quad_a.
in rst_instd_logic
Asynchronous reset.
std_logic quad_b_old
Old copy of quad_b.
in quad_b_instd_logic
Quadrature b input.