orcasim::models::orca::DmaNetif Class Reference

#include <DmaNetif.hpp>

Inheritance diagram for orcasim::models::orca::DmaNetif:

Public Member Functions
DmaNetifRecvState	GetRecvState ()
DmaNetifSendState	GetSendState ()
Signal< uint8_t > *	GetSignalStall ()
Signal< uint8_t > *	GetSignalIntr ()
Signal< uint8_t > *	GetSignalProgSend ()
Signal< uint8_t > *	GetSignalProgRecv ()
Signal< uint8_t > *	GetSignalRecvReload ()
Signal< uint8_t > *	GetSignalSendStatus ()
Signal< uint32_t > *	GetSignalRecvStatus ()
Signal< uint32_t > *	GetSignalProgAddr ()
Signal< uint32_t > *	GetSignalProgSize ()
Signal< uint16_t > *	GetSignalProgDest ()
void	SetSignalStall (Signal< uint8_t > *)
void	SetSignalIntr (Signal< uint8_t > *)
void	SetSignalSendStatus (Signal< uint8_t > *)
void	SetSignalProgSend (Signal< uint8_t > *)
void	SetSignalProgRecv (Signal< uint8_t > *)
void	SetSignalRecvReload (Signal< uint8_t > *)
void	SetSignalRecvStatus (Signal< uint32_t > *)
void	SetSignalProgAddr (Signal< uint32_t > *)
void	SetSignalProgSize (Signal< uint32_t > *)
void	SetSignalProgDest (Signal< uint16_t > *)
void	sendProcess ()
void	recvProcess ()
SimulationTime	Run ()
	Method which is called by the simulator when during the execution of the TimedModel. More...
void	Reset ()
	Resets the instance to its starting state. More...
void	SetMem0 (Memory *)
void	SetMem1 (Memory *)
void	SetMem2 (Memory *)
void	SetOutputBuffer (Buffer< FlitType > *ob)
Buffer< FlitType > *	GetInputBuffer ()
	DmaNetif (std::string name)
	~DmaNetif ()
a name that identifies the model, advisably not empty.
Default ctor.
std::string	GetName ()
	Getter method for the <_name> field. More...
void	SetName (std::string s)
	Setter method for the <_name> field. More...

Private Attributes
Memory *	_mem0
Memory *	_mem1
Memory *	_mem2
DmaNetifRecvState	_recv_state
DmaNetifSendState	_send_state
FlitType	_recv_reg
FlitType	_send_reg
Signal< uint8_t > *	_sig_stall
Signal< uint8_t > *	_sig_intr
Signal< uint8_t > *	_sig_recv_reload
Signal< uint8_t > *	_sig_prog_send
Signal< uint8_t > *	_sig_prog_recv
Signal< uint8_t > *	_sig_send_status
Signal< uint32_t > *	_sig_recv_status
Signal< uint32_t > *	_sig_prog_addr
Signal< uint32_t > *	_sig_prog_size
Signal< uint16_t > *	_sig_prog_dest
uint32_t	_recv_payload_size
uint32_t	_recv_payload_remaining
uint32_t	_recv_address
uint32_t	_send_payload_size
uint32_t	_send_payload_remaining
uint32_t	_send_address
Buffer< FlitType > *	_ib
Buffer< FlitType > *	_ob

Detailed Description

Author

Anderson Domingues

Date

10/03/18

Definition at line 98 of file DmaNetif.hpp.

Constructor & Destructor Documentation

DmaNetif()

DmaNetif::DmaNetif ( std::string  name )

explicit

Definition at line 43 of file DmaNetif.cpp.

                                 : TimedModel(name) {
    _sig_stall = nullptr;
    _sig_intr  = nullptr;

    _sig_send_status = nullptr;
    _sig_recv_status = nullptr;

    _sig_recv_reload = nullptr;

    _sig_prog_addr = nullptr;
    _sig_prog_size = nullptr;
    _sig_prog_send = nullptr;
    _sig_prog_recv = nullptr;
    _sig_prog_dest = nullptr;

    _ib = new Buffer<FlitType>(name + ".IN", NI_BUFFER_LEN);

    this->Reset();
}

~DmaNetif()

DmaNetif::~DmaNetif

(

)

Definition at line 63 of file DmaNetif.cpp.

                    {
    delete _ib;
}

Member Function Documentation

GetInputBuffer()

Buffer< FlitType > * DmaNetif::GetInputBuffer

(

)

Definition at line 76 of file DmaNetif.cpp.

                                           {
    return _ib;
}

GetName()

std::string Model::GetName ( )

inherited

Getter method for the <_name> field.

Definition at line 34 of file Model.cpp.

                         {
    return _name;
}

GetRecvState()

DmaNetifRecvState DmaNetif::GetRecvState

(

)

Definition at line 81 of file DmaNetif.cpp.

{ return _recv_state; }

GetSendState()

DmaNetifSendState DmaNetif::GetSendState

(

)

Definition at line 82 of file DmaNetif.cpp.

{ return _send_state; }

GetSignalIntr()

Signal< uint8_t > * DmaNetif::GetSignalIntr

(

)

Definition at line 90 of file DmaNetif.cpp.

{ return _sig_intr; }

GetSignalProgAddr()

Signal< uint32_t > * DmaNetif::GetSignalProgAddr

(

)

Definition at line 97 of file DmaNetif.cpp.

{ return _sig_prog_addr; }

GetSignalProgDest()

Signal< uint16_t > * DmaNetif::GetSignalProgDest

(

)

Definition at line 100 of file DmaNetif.cpp.

{ return _sig_prog_dest; }

GetSignalProgRecv()

Signal< uint8_t > * DmaNetif::GetSignalProgRecv

(

)

Definition at line 93 of file DmaNetif.cpp.

{ return _sig_prog_recv; }

GetSignalProgSend()

Signal< uint8_t > * DmaNetif::GetSignalProgSend

(

)

Definition at line 92 of file DmaNetif.cpp.

{ return _sig_prog_send; }

GetSignalProgSize()

Signal< uint32_t > * DmaNetif::GetSignalProgSize

(

)

Definition at line 98 of file DmaNetif.cpp.

{ return _sig_prog_size; }

GetSignalRecvReload()

Signal< uint8_t > * DmaNetif::GetSignalRecvReload

(

)

Definition at line 94 of file DmaNetif.cpp.

{ return _sig_recv_reload; }

GetSignalRecvStatus()

Signal< uint32_t > * DmaNetif::GetSignalRecvStatus

(

)

Definition at line 96 of file DmaNetif.cpp.

{ return _sig_recv_status; }

GetSignalSendStatus()

Signal< uint8_t > * DmaNetif::GetSignalSendStatus

(

)

Definition at line 91 of file DmaNetif.cpp.

{ return _sig_send_status; }

GetSignalStall()

Signal< uint8_t > * DmaNetif::GetSignalStall

(

)

Definition at line 89 of file DmaNetif.cpp.

{ return _sig_stall; }

recvProcess()

void DmaNetif::recvProcess

(

)

Definition at line 124 of file DmaNetif.cpp.

                           {
    // recv state machine
    switch (_recv_state) {

        // wait for the leading flit do start the loading process
        case DmaNetifRecvState::RELOAD_WAIT: {
            if (_ib->size() > 0) {
                _ib->pop(); // discard first flit 
                _recv_state = DmaNetifRecvState::RELOAD_SIZE;
                _recv_address = _mem0->GetBase(); //write to 1st position
            }
        } break;
        
        // collect the size of data to be loaded into memory
        case DmaNetifRecvState::RELOAD_SIZE: {
            if (_ib->size() > 0) {
                _recv_reg = _ib->top();
                _recv_payload_size = _recv_reg;
                _recv_payload_remaining = _recv_reg;
                _ib->pop();
                _recv_state = DmaNetifRecvState::RELOAD_SIZE;
            }
        } break;

        case DmaNetifRecvState::RELOAD_COPY:
            if (_ib->size() > 0) {
                _recv_reg = _ib->top();
                _ib->pop();
                _mem1->Write(_recv_address,
                    reinterpret_cast<int8_t*>(&_recv_reg), sizeof(FlitType));
                _recv_payload_remaining--;
                _recv_address += sizeof(FlitType);

                if(_recv_payload_remaining == 0)
                    _recv_state = DmaNetifRecvState::RELOAD_FLUSH;
            }
            break;

        case DmaNetifRecvState::RELOAD_FLUSH:

            break;

        // wait some flit to arrive at the local port
        case DmaNetifRecvState::WAIT_ADDR_FLIT: {
            // If buffer has any flit, copy that flit to internal
            // memory and proceed to next flit. Please note that
            // it is expected the first flit to containg address
            // data. Whatever comes first we treat as the addr flit.
            if (_ib->size() > 0) {
                // copy the first flit into an auxiliar register and pop buffer
                _recv_reg = _ib->top();
                _ib->pop();

                // reset memory pointer and write copied flit to first position
                _recv_address = 0;

                #ifdef NETIF_WRITE_ADDRESS_CHECKING
                if (_recv_address < _mem1->GetBase() || _
                    recv_address > _mem1->GetLastAddr()) {
                    stringstream ss;
                    ss << this->GetName()
                        << ", recv::WAIT_ADDR_FLIT, unable to write to _mem1 "
                        << std::hex << "0x" << _recv_address << std::endl;
                    throw std::runtime_error(ss.str());
                }
                #endif

                // write first flit to recv mem
                _mem1->Write(_recv_address,
                    reinterpret_cast<int8_t*>(&_recv_reg), sizeof(FlitType));
                _recv_address += sizeof(FlitType);

                // change states
                _recv_state = DmaNetifRecvState::WAIT_SIZE_FLIT;
            }
        } break;

        // read size flit to determine how many flits will come next. please
        // note that we treat whatever flit comes next as the size flit
        case DmaNetifRecvState::WAIT_SIZE_FLIT: {
            if (_ib->size() > 0) {
                // copy size flit to an auxiliar register and pop buffer
                _recv_reg = _ib->top();
                _ib->pop();

                // report current size (in flits) to the cpu
                // we sum 2 due to the size flit does not take the first two
                // flits into account.
                _sig_recv_status->Write((_recv_reg + 2));

                #ifdef NETIF_WRITE_ADDRESS_CHECKING
                if (_recv_address < _mem1->GetBase() ||
                    recv_address > _mem1->GetLastAddr()) {
                    stringstream ss;
                    ss << this->GetName()
                        << ", recv::WAIT_SIZE_FLIT, unable to write to _mem1 "
                        << std::hex << "0x" << _recv_address << std::endl;
                    throw std::runtime_error(ss.str());
                }
                #endif

                // write to the second position and increment memory pointer
                _mem1->Write(_recv_address,
                    reinterpret_cast<int8_t*>(&_recv_reg), sizeof(FlitType));
                _recv_address += sizeof(FlitType);

                // set current payload size and the number of remaining flits
                _recv_payload_size = _recv_reg;
                _recv_payload_remaining = _recv_reg;

                // change states
                _recv_state = DmaNetifRecvState::WAIT_PAYLOAD;
            }
        } break;

        // wait for remaining flits to arrive, and interrupt
        case DmaNetifRecvState::WAIT_PAYLOAD: {
            // check whether there are more flits to receive
            if (_recv_payload_remaining > 0) {
                // check whether there is any data in the buffer
                if (_ib->size() > 0) {
                    // copy one flit into the auxiliary register and pop buffer
                    _recv_reg = _ib->top();
                    _ib->pop();

                    #ifdef NETIF_WRITE_ADDRESS_CHECKING
                    if (_recv_address < _mem1->GetBase() ||
                        _recv_address > _mem1->GetLastAddr()) {
                        stringstream ss;
                        ss << this->GetName()
                            << ", recv::WAIT_PAYLOAD, unable to write to _mem1 "
                            << std::hex << "0x" << _recv_address << std::endl;
                        throw std::runtime_error(ss.str());
                    }
                    #endif

                    // write the flit to memory and increment memory counter
                    _mem1->Write(_recv_address,
                        reinterpret_cast<int8_t*>(&_recv_reg),
                        sizeof(FlitType));

                    _recv_address += sizeof(FlitType);

                    // one less flit to be received
                    _recv_payload_remaining--;
                }

            // whether the ni received all the payload,
            // and interrupt the cpu and change states
            } else {
                _sig_intr->Write(0x1);
                _recv_state = DmaNetifRecvState::WAIT_CONFIG_STALL;
            }
        } break;

        // wait for the cpu to configure the dma
        case DmaNetifRecvState::WAIT_CONFIG_STALL: {
            if (_sig_prog_recv->Read() == 0x1) {
                // configured via cpu. accounts the +2, so no sum is necessary
                _recv_payload_remaining = _sig_prog_size->Read();
                _sig_recv_status->Write(0x0);

                _recv_state = DmaNetifRecvState::COPY_RELEASE;
                _recv_address = 0;  // reset memory pointer
                _sig_stall->Write(0x1);  // stall cpu
            }
        } break;

        // copy data, and release
        case DmaNetifRecvState::COPY_RELEASE: {
            // for each flit, copy from the auxiliary _mem1 memory
            // to the _mem0 main memory
            if (_recv_payload_remaining > 0) {
                #ifdef NETIF_READ_ADDRESS_CHECKING
                if (_recv_address < _mem1->GetBase() ||
                    _recv_address > _mem1->GetLastAddr()) {
                    stringstream ss;
                    ss << this->GetName()
                        << ", recv::COPY_RELEASE, unable to read to _mem1 "
                        << std::hex << "0x" << _recv_address << std::endl;
                    throw std::runtime_error(ss.str());
                }
                #endif

                // read data to the auxiliary register
                _mem1->Read(_recv_address,
                    reinterpret_cast<int8_t*>(&_recv_reg), sizeof(FlitType));

                #ifdef NETIF_WRITE_ADDRESS_CHECKING
                uint32_t addr = _recv_address + _sig_prog_addr->Read();
                if (addr < _mem0->GetBase() || addr > _mem0->GetLastAddr()) {
                    stringstream ss;
                    ss << this->GetName()
                        << ", recv::COPY_RELEASE, unable to write to _mem0 "
                        << std::hex << "0x" << addr << std::endl;
                    throw std::runtime_error(ss.str());
                }
                #endif

                // write auxiliary flit to main memory
                _mem0->Write(_recv_address + _sig_prog_addr->Read(),
                    reinterpret_cast<int8_t*>(&_recv_reg), sizeof(FlitType));

                _recv_address += sizeof(FlitType);  // read next address
                _recv_payload_remaining--;  // one less flit to write

            // if there is no more flits to receive, lower the interruption,
            // restore the cpu (release stall), then change states
            } else {
                _sig_stall->Write(0x0);
                _sig_intr->Write(0x0);

                _recv_state = DmaNetifRecvState::FLUSH;
            }
        } break;

        case DmaNetifRecvState::FLUSH: {
            if (_sig_prog_recv->Read() == 0x0) {
                _recv_state = DmaNetifRecvState::WAIT_ADDR_FLIT;
            }
        } break;
    }
}

Reset()

void DmaNetif::Reset ( )

virtual

Resets the instance to its starting state.

Must be implemented by subclasses

Implements orcasim::base::TimedModel.

Definition at line 67 of file DmaNetif.cpp.

                     {
    _recv_state = DmaNetifRecvState::WAIT_ADDR_FLIT;
    _send_state = DmaNetifSendState::WAIT_CONFIG_STALL;
}

Run()

SimulationTime DmaNetif::Run ( )

virtual

Method which is called by the simulator when during the execution of the TimedModel.

Must be implemented by subclasses.

Implements orcasim::base::TimedModel.

Definition at line 116 of file DmaNetif.cpp.

                             {
    // independent processes, can run parallel
    this->recvProcess();
    this->sendProcess();

    return 1;  // takes only 1 cycle to change both states
}

sendProcess()

void DmaNetif::sendProcess

(

)

Definition at line 348 of file DmaNetif.cpp.

                           {
    // send state machine
    switch (_send_state) {
        // wait the cpu to configure the ni
        case DmaNetifSendState::WAIT_CONFIG_STALL: {
            if (_sig_prog_send->Read() == 0x1) {
                _sig_stall->Write(0x1);        // raise stall
                _sig_send_status->Write(0x1);  // raise status

                _send_address = 0;
                _send_payload_size = _sig_prog_size->Read();
                _send_payload_remaining = _send_payload_size;

                // change states
                _send_state = DmaNetifSendState::COPY_AND_RELEASE;
            }
        } break;

        // copy data from the main memory to the auxiliary memory
        // and releases cpu, lower status and stall
        case DmaNetifSendState::COPY_AND_RELEASE: {
            if (_send_payload_remaining > 0) {
                #ifdef NETIF_READ_ADDRESS_CHECKING
                uint32_t addr = _send_address + _sig_prog_addr->Read();
                if (addr < _mem0->GetBase() || addr > _mem0->GetLastAddr()) {
                    stringstream ss;
                    ss << this->GetName()
                        << ", send::COPY_RELEASE, unable to read from _mem0 "
                        << std::hex << "0x" << addr << std::endl;
                    throw std::runtime_error(ss.str());
                }
                #endif

                // read from main memory
                _mem0->Read(_send_address + _sig_prog_addr->Read(),
                    reinterpret_cast<int8_t*>(&_send_reg), sizeof(FlitType));

                #ifdef NETIF_WRITE_ADDRESS_CHECKING
                if (_send_address < _mem2->GetBase() ||
                    _send_address > _mem2->GetLastAddr()) {
                    stringstream ss;
                    ss << this->GetName()
                        << ", send::COPY_RELEASE, unable to write to _mem2 "
                        << std::hex << "0x" << _send_address << std::endl;
                    throw std::runtime_error(ss.str());
                }
                #endif

                // write auxiliary flit to auxiliary memory
                _mem2->Write(_send_address,
                    reinterpret_cast<int8_t*>(&_send_reg), sizeof(FlitType));

                _send_address += sizeof(FlitType);  // write next address
                _send_payload_remaining--;  // one less packet to send

            // all flits copied to the aux memory, switch to noc-mode
            } else {
                _sig_stall->Write(0x0);  // lowers stall
                _send_payload_remaining = _send_payload_size;  // flits to push
                _send_address = 0;  // reset memory pointer
                _send_state = DmaNetifSendState::SEND_DATA_TO_NOC;
            }
        } break;

        case DmaNetifSendState::SEND_DATA_TO_NOC: {
            // make sure the buffer has room to receive another packet
            if (_send_payload_remaining > 0) {
                if (_ob->size() < _ob->capacity()) {
                    _mem2->Read(_send_address,
                        reinterpret_cast<int8_t*>(&_send_reg),
                        sizeof(FlitType));
                    _ob->push(_send_reg);
                    _send_payload_remaining--;

                    _send_address += sizeof(FlitType);
                }

            // make sure the cpu have lowered the start signal at least once
            // before getting back to the waiting state (prevent duplicates)
            } else {
                _send_state = DmaNetifSendState::FLUSH;
            }
        } break;

        case DmaNetifSendState::FLUSH: {
            if (_sig_prog_send->Read() == 0x0) {
                _sig_send_status->Write(0x0);  // notify free
                _send_state = DmaNetifSendState::WAIT_CONFIG_STALL;
            }
        } break;
    }
}

SetMem0()

void DmaNetif::SetMem0

(

Memory *

m0

)

Definition at line 84 of file DmaNetif.cpp.

{ _mem0 = m0; }  // main mem

SetMem1()

void DmaNetif::SetMem1

(

Memory *

m1

)

Definition at line 85 of file DmaNetif.cpp.

{ _mem1 = m1; }  // recv mem

SetMem2()

void DmaNetif::SetMem2

(

Memory *

m2

)

Definition at line 86 of file DmaNetif.cpp.

{ _mem2 = m2; }  // send mem

SetName()

void Model::SetName ( std::string  s )

inherited

Setter method for the <_name> field.

Parameters

s	Value to be set

Definition at line 38 of file Model.cpp.

                                        {
    _name = name;
}

SetOutputBuffer()

void DmaNetif::SetOutputBuffer

(

Buffer< FlitType > *

ob

)

Definition at line 72 of file DmaNetif.cpp.

                                                   {
    _ob = ob;
}

SetSignalIntr()

void DmaNetif::SetSignalIntr

(

Signal< uint8_t > *

c

)

Definition at line 104 of file DmaNetif.cpp.

{ _sig_intr = c; }

SetSignalProgAddr()

void DmaNetif::SetSignalProgAddr

(

Signal< uint32_t > *

c

)

Definition at line 111 of file DmaNetif.cpp.

{ _sig_prog_addr = c; }

SetSignalProgDest()

void DmaNetif::SetSignalProgDest

(

Signal< uint16_t > *

c

)

Definition at line 114 of file DmaNetif.cpp.

{ _sig_prog_dest = c; }

SetSignalProgRecv()

void DmaNetif::SetSignalProgRecv

(

Signal< uint8_t > *

c

)

Definition at line 107 of file DmaNetif.cpp.

{ _sig_prog_recv = c; }

SetSignalProgSend()

void DmaNetif::SetSignalProgSend

(

Signal< uint8_t > *

c

)

Definition at line 106 of file DmaNetif.cpp.

{ _sig_prog_send = c; }

SetSignalProgSize()

void DmaNetif::SetSignalProgSize

(

Signal< uint32_t > *

c

)

Definition at line 112 of file DmaNetif.cpp.

{ _sig_prog_size = c; }

SetSignalRecvReload()

void DmaNetif::SetSignalRecvReload

(

Signal< uint8_t > *

c

)

Definition at line 108 of file DmaNetif.cpp.

{ _sig_recv_reload = c; }

SetSignalRecvStatus()

void DmaNetif::SetSignalRecvStatus

(

Signal< uint32_t > *

c

)

Definition at line 110 of file DmaNetif.cpp.

{ _sig_recv_status = c; }

SetSignalSendStatus()

void DmaNetif::SetSignalSendStatus

(

Signal< uint8_t > *

c

)

Definition at line 105 of file DmaNetif.cpp.

{ _sig_send_status = c; }

SetSignalStall()

void DmaNetif::SetSignalStall

(

Signal< uint8_t > *

c

)

Definition at line 103 of file DmaNetif.cpp.

{ _sig_stall = c; }

Member Data Documentation

_ib

Buffer<FlitType>* orcasim::models::orca::DmaNetif::_ib

private

Definition at line 138 of file DmaNetif.hpp.

_mem0

Memory* orcasim::models::orca::DmaNetif::_mem0

private

Definition at line 101 of file DmaNetif.hpp.

_mem1

Memory* orcasim::models::orca::DmaNetif::_mem1

private

Definition at line 102 of file DmaNetif.hpp.

_mem2

Memory* orcasim::models::orca::DmaNetif::_mem2

private

Definition at line 103 of file DmaNetif.hpp.

_ob

Buffer<FlitType>* orcasim::models::orca::DmaNetif::_ob

private

Definition at line 139 of file DmaNetif.hpp.

_recv_address

uint32_t orcasim::models::orca::DmaNetif::_recv_address

private

Definition at line 130 of file DmaNetif.hpp.

_recv_payload_remaining

uint32_t orcasim::models::orca::DmaNetif::_recv_payload_remaining

private

Definition at line 129 of file DmaNetif.hpp.

_recv_payload_size

uint32_t orcasim::models::orca::DmaNetif::_recv_payload_size

private

Definition at line 128 of file DmaNetif.hpp.

_recv_reg

FlitType orcasim::models::orca::DmaNetif::_recv_reg

private

Definition at line 110 of file DmaNetif.hpp.

_recv_state

DmaNetifRecvState orcasim::models::orca::DmaNetif::_recv_state

private

Definition at line 106 of file DmaNetif.hpp.

_send_address

uint32_t orcasim::models::orca::DmaNetif::_send_address

private

Definition at line 135 of file DmaNetif.hpp.

_send_payload_remaining

uint32_t orcasim::models::orca::DmaNetif::_send_payload_remaining

private

Definition at line 134 of file DmaNetif.hpp.

_send_payload_size

uint32_t orcasim::models::orca::DmaNetif::_send_payload_size

private

Definition at line 133 of file DmaNetif.hpp.

_send_reg

FlitType orcasim::models::orca::DmaNetif::_send_reg

private

Definition at line 111 of file DmaNetif.hpp.

_send_state

DmaNetifSendState orcasim::models::orca::DmaNetif::_send_state

private

Definition at line 107 of file DmaNetif.hpp.

_sig_intr

Signal<uint8_t>* orcasim::models::orca::DmaNetif::_sig_intr

private

Definition at line 115 of file DmaNetif.hpp.

_sig_prog_addr

Signal<uint32_t>* orcasim::models::orca::DmaNetif::_sig_prog_addr

private

Definition at line 122 of file DmaNetif.hpp.

_sig_prog_dest

Signal<uint16_t>* orcasim::models::orca::DmaNetif::_sig_prog_dest

private

Definition at line 125 of file DmaNetif.hpp.

_sig_prog_recv

Signal<uint8_t>* orcasim::models::orca::DmaNetif::_sig_prog_recv

private

Definition at line 118 of file DmaNetif.hpp.

_sig_prog_send

Signal<uint8_t>* orcasim::models::orca::DmaNetif::_sig_prog_send

private

Definition at line 117 of file DmaNetif.hpp.

_sig_prog_size

Signal<uint32_t>* orcasim::models::orca::DmaNetif::_sig_prog_size

private

Definition at line 123 of file DmaNetif.hpp.

_sig_recv_reload

Signal<uint8_t>* orcasim::models::orca::DmaNetif::_sig_recv_reload

private

Definition at line 116 of file DmaNetif.hpp.

_sig_recv_status

Signal<uint32_t>* orcasim::models::orca::DmaNetif::_sig_recv_status

private

Definition at line 121 of file DmaNetif.hpp.

_sig_send_status

Signal<uint8_t>* orcasim::models::orca::DmaNetif::_sig_send_status

private

Definition at line 119 of file DmaNetif.hpp.

_sig_stall

Signal<uint8_t>* orcasim::models::orca::DmaNetif::_sig_stall

private

Definition at line 114 of file DmaNetif.hpp.

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The documentation for this class was generated from the following files:

• models/orca-network-interface/include/DmaNetif.hpp
• models/orca-network-interface/src/DmaNetif.cpp