40 #include "UMemory.hpp" 43 #include "THFRiscV.hpp" 62 std::cout << std::endl <<
63 "Simulation interrupted. Wait for the current epoch to finish " <<
64 "or press CTRL+C again to force quit." << std::endl;
70 std::cout << std::endl <<
"Hold your horses!" << std::endl;
76 #ifndef ORCA_EPOCH_LENGTH 78 "ORCA_EPOCH_LENGTH must be defined in Configuration.mk\n");
83 #ifndef ORCA_EPOCHS_TO_SIM 84 std::cout <<
"ORCA_EPOCHS_TO_SIM set to INFINITE" << std::endl;
86 std::cout <<
"ORCA_EPOCHS_TO_SIM set to " 91 #ifndef URSA_ZERO_TIME_CHECKING 92 std::cout <<
"URSA_ZERO_TIME_CHECKING disabled" << std::endl;
94 std::cout <<
"URSA_ZERO_TIME_CHECKING set to " 95 << URSA_ZERO_TIME_CHECKING << std::endl;
98 #ifndef URSA_QUEUE_SIZE_CHECKING 99 std::cout <<
"URSA_QUEUE_SIZE_CHECKING disabled" << std::endl;
101 std::cout <<
"URSA_QUEUE_SIZE_CHECKING set to " 102 << URSA_QUEUE_SIZE_CHECKING << std::endl;
106 #ifndef MEMORY_WRITE_ADDRESS_CHECKING 107 std::cout <<
"MEMORY_WRITE_ADDRESS_CHECKING disabled" << std::endl;
109 std::cout <<
"MEMORY_WRITE_ADDRESS_CHECKING enabled" << std::endl;
112 #ifndef MEMORY_READ_ADDRESS_CHECKING 113 std::cout <<
"MEMORY_READ_ADDRESS_CHECKING disabled" << std::endl;
115 std::cout <<
"MEMORY_READ_ADDRESS_CHECKING enabled" << std::endl;
118 #ifndef MEMORY_WIPE_ADDRESS_CHECKING 119 std::cout <<
"MEMORY_WIPE_ADDRESS_CHECKING disabled" << std::endl;
121 std::cout <<
"MEMORY_WIPE_ADDRESS_CHECKING enabled" << std::endl;
124 #ifndef MEMORY_ENABLE_COUNTERS 125 std::cout <<
"MEMORY_ENABLE_COUNTERS disabled" << std::endl;
127 std::cout <<
"MEMORY_ENABLE_COUNTERS enabled" << std::endl;
131 #ifndef HFRISCV_WRITE_ADDRESS_CHECKING 132 std::cout <<
"HFRISCV_WRITE_ADDRESS_CHECKING disabled" << std::endl;
134 std::cout <<
"HFRISCV_WRITE_ADDRESS_CHECKING enabled" << std::endl;
137 #ifndef HFRISCV_READ_ADDRESS_CHECKING 138 std::cout <<
"HFRISCV_READ_ADDRESS_CHECKING disabled" << std::endl;
140 std::cout <<
"HFRISCV_READ_ADDRESS_CHECKING enabled" << std::endl;
143 #ifndef HFRISCV_ENABLE_COUNTERS 144 std::cout <<
"HFRISCV_ENABLE_COUNTERS disabled" << std::endl;
146 std::cout <<
"HFRISCV_ENABLE_COUNTERS enabled" << std::endl;
150 int main(
int __attribute__((unused)) argc,
char** argv) {
156 std::cout <<
"URSA/ORCA Platform " << std::endl;
158 std::cout <<
"==============[ PARAMETERS ]" << std::endl;
161 }
catch (std::runtime_error& e) {
162 std::cout << e.what() << std::endl;
166 std::cout <<
"==============[ TILE COMPOSITION ]" << std::endl;
174 std::cout <<
"==============[ SIMULATION ]" << std::endl;
177 Simulator* s =
new Simulator();
179 std::cout <<
"Scheduling..." << std::endl;
182 s->Schedule(Event(3, tile->
GetCpu()));
185 s->Schedule(Event(2, tile->
GetDma()));
188 <<
" cycles." << std::endl;
189 std::cout <<
"Please wait..." << std::endl;
192 std::chrono::high_resolution_clock::time_point t1, t2;
194 t1 = std::chrono::high_resolution_clock::now();
196 t2 = std::chrono::high_resolution_clock::now();
199 std::chrono::duration_cast<std::chrono::milliseconds>(t2 - t1)
205 (static_cast<double>(duration) / 1000.0);
208 std::cout <<
"notice: epoch #" << s->GetEpochs() <<
" took ~" 209 << duration <<
"ms (running @ " << (hertz / 1000000.0)
210 <<
" MHz)" << std::endl;
212 #ifdef ORCA_EPOCHS_TO_SIM 218 }
catch(std::runtime_error& e) {
219 std::cout << e.what() << std::endl;
234 std::cout <<
"Simulation failed!" << std::endl;
236 std::cout <<
"Simulation ended without errors." << std::endl;
Signal< uint8_t > * GetSignalIntr()
#define MEM0_SIZE
This file is part of project URSA.
static volatile sig_atomic_t interruption
#define ORCA_EPOCHS_TO_SIM
#define ORCA_EPOCH_LENGTH
Signal< uint8_t > * GetSignalStall()
T Read()
Get the last value writen to the bus.
int main(int __attribute__((unused)) argc, char **argv)
static void sig_handler(int _)