Verilog Parser
AST Construction Functions

This page describes all of the functions used to construct the AST representation of the input code, along with the corresponding data structures. More...

Modules

 Meta Data
 Objects used to represent meta data about a particular construct.
 
 Numbers
 Objects used to represent individual numbers.
 
 Attributes
 Describes attributes passed to modules, functions and expression assignments.
 
 Concatenations
 Concatenations of expressions, l-values, variables, nets and module paths.
 
 L-Values
 Represents the class of values which represent the left hand term of an assignment.
 
 Function Calls
 Represents a call to a system or user function. Note this is destinct from a function declaration.
 
 Expressions
 Super-group for data-structures representing the kinds of expressions that Verilog has.
 
 Path Declarations
 Describes construction of path declarations and delay specifiers.
 
 Timing Control Statements
 
 User Defined Primitives
 User defined primitive types.
 
 Primitives
 Digital design primitive representation. Transistors, transmission gates, etc.
 
 Delays
 Signal propagation delays.
 
 Drive Strengths
 Describes signal drive strengths.
 
 Nets and Variables
 Net and variable types, declarations and assignments.
 
 Type Declaration
 Custom type declarations.
 
 Module Declaration
 Details declaration of module ports and parameters.
 
 Identifiers
 Functions and data structures representing identifiers for all Verilog Constructs.
 
 Configuration Source
 Describes configuration constructs.
 
 Library Source
 Library, config and include statements / constructs.
 
 Compiler Directives
 TODO.
 
 Top Level
 Represents nodes at the very top of the source tree.
 

Detailed Description

This page describes all of the functions used to construct the AST representation of the input code, along with the corresponding data structures.

All functions and data structures are grouped depending on which syntactic feature of the language you are trying to represent.