| ▼Abstract Syntax Tree | Functions and data structures which build and represent the AST |
| ▼AST Construction Functions | This page describes all of the functions used to construct the AST representation of the input code, along with the corresponding data structures |
| Meta Data | Objects used to represent meta data about a particular construct |
| Numbers | Objects used to represent individual numbers |
| Attributes | Describes attributes passed to modules, functions and expression assignments |
| Concatenations | Concatenations of expressions, l-values, variables, nets and module paths |
| L-Values | Represents the class of values which represent the left hand term of an assignment |
| Function Calls | Represents a call to a system or user function. Note this is destinct from a function declaration |
| ▼Expressions | Super-group for data-structures representing the kinds of expressions that Verilog has |
| Expression Primaries | Expresses primary terms of expressions. These can be sub-expressions, numbers, identifiers etc |
| Path Declarations | Describes construction of path declarations and delay specifiers |
| Timing Control Statements | |
| User Defined Primitives | User defined primitive types |
| Primitives | Digital design primitive representation. Transistors, transmission gates, etc |
| Delays | Signal propagation delays |
| Drive Strengths | Describes signal drive strengths |
| Nets and Variables | Net and variable types, declarations and assignments |
| Type Declaration | Custom type declarations |
| ▼Module Declaration | Details declaration of module ports and parameters |
| Module Port Declaration | |
| Module Parameters | |
| ▼Module Items | Contains things like continuous assignments, procedural blocks and module instantiations |
| Fork Join and Sequential Blocks | Fork join and sequential stamement blocks |
| ▼Procedural Blocks and Assignments | Describes items found inside procedural blocks |
| Task Enable Statements | Describes task enable statements |
| Loop Statements | Describes for and while loop representation |
| Case Statements | |
| If Else Statements | |
| Generate Statements | Represents generate loops |
| Module Instantiation | Describes the instantiation of a module, as opposed to it's declaration |
| ▼Declarations | Blocks of definitions |
| Function Declaration | Describes a declaration of a user function |
| Task Declaration | User task (procedure) definition |
| Identifiers | Functions and data structures representing identifiers for all Verilog Constructs |
| Configuration Source | Describes configuration constructs |
| Library Source | Library, config and include statements / constructs |
| Compiler Directives | TODO |
| Top Level | Represents nodes at the very top of the source tree |
| AST Nodes | Notes and todo list for the AST nodes |
| ▼AST Utility Functions | Contains utility data structures and functions which are used to help represent portions of the AST, but which are not specific to a particular node |
| Linked List | |
| Stack | |
| Hash Table | A very simple hash table implemented (for now) over a linked list |
| Memory Management | Helps to manage memory allocated during AST construction |
| Module Resoloution & Searching | Functions for resolving module names |
| Verilog Parser API | Describes the top level, programmer facing parser API |
| Preprocessor | This module contains all code and information on the preprocessor and how it works / is implemented |
1.8.11 
