Verilog Parser

Details declaration of module ports and parameters. More...

Modules

 Module Port Declaration
 
 Module Parameters
 
 Module Items
 Contains things like continuous assignments, procedural blocks and module instantiations.
 

Data Structures

struct  ast_module_declaration
 Fully describes a single module declaration in terms of parameters ports and internal constructs. More...
 

Functions

ast_module_declaration * ast_new_module_declaration (ast_node_attributes *attributes, ast_identifier identifier, ast_list *parameters, ast_list *ports, ast_list *constructs)
 Creates a new module instantiation. More...
 

Detailed Description

Details declaration of module ports and parameters.

Function Documentation

ast_module_declaration* ast_new_module_declaration ( ast_node_attributes *  attributes,
ast_identifier  identifier,
ast_list parameters,
ast_list ports,
ast_list constructs 
)

Creates a new module instantiation.

Parameters
[in]attributes- Tool specific attributes.
[in]identifier- The full module name
[in]parameters- List of parameters to the module
[in]ports- List of module ports.
[in]constructs- The internal constructs such as tasks, procedures and internal instantiations.
[in]ports- This should be a list of ast_port_declaration if we are using the new style of port declaration, or NULL if the port declarations are contained within the module items list.