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Verilog Parser
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Contains utility data structures and functions which are used to help represent portions of the AST, but which are not specific to a particular node. More...
Modules | |
| Linked List | |
| Stack | |
| Hash Table | |
| A very simple hash table implemented (for now) over a linked list. | |
| Memory Management | |
| Helps to manage memory allocated during AST construction. | |
| Module Resoloution & Searching | |
| Functions for resolving module names. | |
Contains utility data structures and functions which are used to help represent portions of the AST, but which are not specific to a particular node.