Functions for resolving module names. More...

Functions
ast_module_declaration *	verilog_find_module_declaration (verilog_source_tree *source, ast_identifier module_name)
	Searches the list of modules in the parsed source tree, returning the one that matches the passed identifer. More...

ast_list *	verilog_module_get_children (ast_module_declaration *module)
	Returns a list of module declarations, representing the different types of module which this parent instantiates. More...

ast_hashtable *	verilog_modules_get_children (verilog_source_tree *source)
	Finds the child modules for all modules in a source tree. More...

void	verilog_resolve_modules (verilog_source_tree *source)
	searches across an entire verilog source tree, resolving module identifiers to their declarations.

Detailed Description

Functions for resolving module names.

Function Documentation

ast_module_declaration* verilog_find_module_declaration	(	verilog_source_tree *	source,
		ast_identifier	module_name
	)

Searches the list of modules in the parsed source tree, returning the one that matches the passed identifer.

Returns: The matching module declaration, or NULL if no such declaration exists.

ast_list* verilog_module_get_children ( ast_module_declaration * module )

Returns a list of module declarations, representing the different types of module which this parent instantiates.

Each child module will appear once in the returned list. That is, if a register instantiates eight flip flop modules, then the flip flop module will appear only once in the returned list.

Returns: a list of elements of type ast_module_declaration.

Precondition: The verilog_resolve_modules function has been called on the source tree to which the passed module belongs.

See also: verilog_modules_get_children

Returns a list of module declarations, representing the different types of module which this parent instantiates.

ast_hashtable* verilog_modules_get_children ( verilog_source_tree * source )

Finds the child modules for all modules in a source tree.

Returns: A hash table, keyed by the module identifiers, of lists of module children.

Precondition: The verilog_resolve_modules function has been called on the source tree to which the passed module belongs.

See also: verilog_module_get_children