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core_cm33.h
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1 /**************************************************************************/
7 /*
8  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #endif
30 
31 #ifndef __CORE_CM33_H_GENERIC
32 #define __CORE_CM33_H_GENERIC
33 
34 #include <stdint.h>
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif
39 
55 /*******************************************************************************
56  * CMSIS definitions
57  ******************************************************************************/
63 #include "cmsis_version.h"
64 
65 /* CMSIS CM33 definitions */
66 #define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67 #define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68 #define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \
69  __CM33_CMSIS_VERSION_SUB )
71 #define __CORTEX_M (33U)
76 #if defined ( __CC_ARM )
77  #if defined (__TARGET_FPU_VFP)
78  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
79  #define __FPU_USED 1U
80  #else
81  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82  #define __FPU_USED 0U
83  #endif
84  #else
85  #define __FPU_USED 0U
86  #endif
87 
88  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
89  #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
90  #define __DSP_USED 1U
91  #else
92  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
93  #define __DSP_USED 0U
94  #endif
95  #else
96  #define __DSP_USED 0U
97  #endif
98 
99 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
100  #if defined (__ARM_PCS_VFP)
101  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
102  #define __FPU_USED 1U
103  #else
104  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
105  #define __FPU_USED 0U
106  #endif
107  #else
108  #define __FPU_USED 0U
109  #endif
110 
111  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
112  #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
113  #define __DSP_USED 1U
114  #else
115  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
116  #define __DSP_USED 0U
117  #endif
118  #else
119  #define __DSP_USED 0U
120  #endif
121 
122 #elif defined ( __GNUC__ )
123  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
124  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
125  #define __FPU_USED 1U
126  #else
127  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
128  #define __FPU_USED 0U
129  #endif
130  #else
131  #define __FPU_USED 0U
132  #endif
133 
134  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
135  #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
136  #define __DSP_USED 1U
137  #else
138  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
139  #define __DSP_USED 0U
140  #endif
141  #else
142  #define __DSP_USED 0U
143  #endif
144 
145 #elif defined ( __ICCARM__ )
146  #if defined (__ARMVFP__)
147  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
148  #define __FPU_USED 1U
149  #else
150  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
151  #define __FPU_USED 0U
152  #endif
153  #else
154  #define __FPU_USED 0U
155  #endif
156 
157  #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
158  #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
159  #define __DSP_USED 1U
160  #else
161  #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
162  #define __DSP_USED 0U
163  #endif
164  #else
165  #define __DSP_USED 0U
166  #endif
167 
168 #elif defined ( __TI_ARM__ )
169  #if defined (__TI_VFP_SUPPORT__)
170  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
171  #define __FPU_USED 1U
172  #else
173  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
174  #define __FPU_USED 0U
175  #endif
176  #else
177  #define __FPU_USED 0U
178  #endif
179 
180 #elif defined ( __TASKING__ )
181  #if defined (__FPU_VFP__)
182  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
183  #define __FPU_USED 1U
184  #else
185  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
186  #define __FPU_USED 0U
187  #endif
188  #else
189  #define __FPU_USED 0U
190  #endif
191 
192 #elif defined ( __CSMC__ )
193  #if ( __CSMC__ & 0x400U)
194  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
195  #define __FPU_USED 1U
196  #else
197  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
198  #define __FPU_USED 0U
199  #endif
200  #else
201  #define __FPU_USED 0U
202  #endif
203 
204 #endif
205 
206 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
207 
208 
209 #ifdef __cplusplus
210 }
211 #endif
212 
213 #endif /* __CORE_CM33_H_GENERIC */
214 
215 #ifndef __CMSIS_GENERIC
216 
217 #ifndef __CORE_CM33_H_DEPENDANT
218 #define __CORE_CM33_H_DEPENDANT
219 
220 #ifdef __cplusplus
221  extern "C" {
222 #endif
223 
224 /* check device defines and use defaults */
225 #if defined __CHECK_DEVICE_DEFINES
226  #ifndef __CM33_REV
227  #define __CM33_REV 0x0000U
228  #warning "__CM33_REV not defined in device header file; using default!"
229  #endif
230 
231  #ifndef __FPU_PRESENT
232  #define __FPU_PRESENT 0U
233  #warning "__FPU_PRESENT not defined in device header file; using default!"
234  #endif
235 
236  #ifndef __MPU_PRESENT
237  #define __MPU_PRESENT 0U
238  #warning "__MPU_PRESENT not defined in device header file; using default!"
239  #endif
240 
241  #ifndef __SAUREGION_PRESENT
242  #define __SAUREGION_PRESENT 0U
243  #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
244  #endif
245 
246  #ifndef __DSP_PRESENT
247  #define __DSP_PRESENT 0U
248  #warning "__DSP_PRESENT not defined in device header file; using default!"
249  #endif
250 
251  #ifndef __NVIC_PRIO_BITS
252  #define __NVIC_PRIO_BITS 3U
253  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
254  #endif
255 
256  #ifndef __Vendor_SysTickConfig
257  #define __Vendor_SysTickConfig 0U
258  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
259  #endif
260 #endif
261 
262 /* IO definitions (access restrictions to peripheral registers) */
270 #ifdef __cplusplus
271  #define __I volatile
272 #else
273  #define __I volatile const
274 #endif
275 #define __O volatile
276 #define __IO volatile
278 /* following defines should be used for structure members */
279 #define __IM volatile const
280 #define __OM volatile
281 #define __IOM volatile
283 
287 /*******************************************************************************
288  * Register Abstraction
289  Core Register contain:
290  - Core Register
291  - Core NVIC Register
292  - Core SCB Register
293  - Core SysTick Register
294  - Core Debug Register
295  - Core MPU Register
296  - Core SAU Register
297  - Core FPU Register
298  ******************************************************************************/
299 
314 typedef union
315 {
316  struct
317  {
318  uint32_t _reserved0:16;
319  uint32_t GE:4;
320  uint32_t _reserved1:7;
321  uint32_t Q:1;
322  uint32_t V:1;
323  uint32_t C:1;
324  uint32_t Z:1;
325  uint32_t N:1;
326  } b;
327  uint32_t w;
328 } APSR_Type;
329 
330 /* APSR Register Definitions */
331 #define APSR_N_Pos 31U
332 #define APSR_N_Msk (1UL << APSR_N_Pos)
334 #define APSR_Z_Pos 30U
335 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
337 #define APSR_C_Pos 29U
338 #define APSR_C_Msk (1UL << APSR_C_Pos)
340 #define APSR_V_Pos 28U
341 #define APSR_V_Msk (1UL << APSR_V_Pos)
343 #define APSR_Q_Pos 27U
344 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
346 #define APSR_GE_Pos 16U
347 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
353 typedef union
354 {
355  struct
356  {
357  uint32_t ISR:9;
358  uint32_t _reserved0:23;
359  } b;
360  uint32_t w;
361 } IPSR_Type;
362 
363 /* IPSR Register Definitions */
364 #define IPSR_ISR_Pos 0U
365 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
371 typedef union
372 {
373  struct
374  {
375  uint32_t ISR:9;
376  uint32_t _reserved0:7;
377  uint32_t GE:4;
378  uint32_t _reserved1:4;
379  uint32_t T:1;
380  uint32_t IT:2;
381  uint32_t Q:1;
382  uint32_t V:1;
383  uint32_t C:1;
384  uint32_t Z:1;
385  uint32_t N:1;
386  } b;
387  uint32_t w;
388 } xPSR_Type;
389 
390 /* xPSR Register Definitions */
391 #define xPSR_N_Pos 31U
392 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
394 #define xPSR_Z_Pos 30U
395 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
397 #define xPSR_C_Pos 29U
398 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
400 #define xPSR_V_Pos 28U
401 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
403 #define xPSR_Q_Pos 27U
404 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
406 #define xPSR_IT_Pos 25U
407 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos)
409 #define xPSR_T_Pos 24U
410 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
412 #define xPSR_GE_Pos 16U
413 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
415 #define xPSR_ISR_Pos 0U
416 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
422 typedef union
423 {
424  struct
425  {
426  uint32_t nPRIV:1;
427  uint32_t SPSEL:1;
428  uint32_t FPCA:1;
429  uint32_t SFPA:1;
430  uint32_t _reserved1:28;
431  } b;
432  uint32_t w;
433 } CONTROL_Type;
434 
435 /* CONTROL Register Definitions */
436 #define CONTROL_SFPA_Pos 3U
437 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos)
439 #define CONTROL_FPCA_Pos 2U
440 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
442 #define CONTROL_SPSEL_Pos 1U
443 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
445 #define CONTROL_nPRIV_Pos 0U
446 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
448 
461 typedef struct
462 {
463  __IOM uint32_t ISER[16U];
464  uint32_t RESERVED0[16U];
465  __IOM uint32_t ICER[16U];
466  uint32_t RSERVED1[16U];
467  __IOM uint32_t ISPR[16U];
468  uint32_t RESERVED2[16U];
469  __IOM uint32_t ICPR[16U];
470  uint32_t RESERVED3[16U];
471  __IOM uint32_t IABR[16U];
472  uint32_t RESERVED4[16U];
473  __IOM uint32_t ITNS[16U];
474  uint32_t RESERVED5[16U];
475  __IOM uint8_t IPR[496U];
476  uint32_t RESERVED6[580U];
477  __OM uint32_t STIR;
478 } NVIC_Type;
479 
480 /* Software Triggered Interrupt Register Definitions */
481 #define NVIC_STIR_INTID_Pos 0U
482 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
484 
497 typedef struct
498 {
499  __IM uint32_t CPUID;
500  __IOM uint32_t ICSR;
501  __IOM uint32_t VTOR;
502  __IOM uint32_t AIRCR;
503  __IOM uint32_t SCR;
504  __IOM uint32_t CCR;
505  __IOM uint8_t SHPR[12U];
506  __IOM uint32_t SHCSR;
507  __IOM uint32_t CFSR;
508  __IOM uint32_t HFSR;
509  __IOM uint32_t DFSR;
510  __IOM uint32_t MMFAR;
511  __IOM uint32_t BFAR;
512  __IOM uint32_t AFSR;
513  __IM uint32_t ID_PFR[2U];
514  __IM uint32_t ID_DFR;
515  __IM uint32_t ID_ADR;
516  __IM uint32_t ID_MMFR[4U];
517  __IM uint32_t ID_ISAR[6U];
518  __IM uint32_t CLIDR;
519  __IM uint32_t CTR;
520  __IM uint32_t CCSIDR;
521  __IOM uint32_t CSSELR;
522  __IOM uint32_t CPACR;
523  __IOM uint32_t NSACR;
524  uint32_t RESERVED3[92U];
525  __OM uint32_t STIR;
526  uint32_t RESERVED4[15U];
527  __IM uint32_t MVFR0;
528  __IM uint32_t MVFR1;
529  __IM uint32_t MVFR2;
530  uint32_t RESERVED5[1U];
531  __OM uint32_t ICIALLU;
532  uint32_t RESERVED6[1U];
533  __OM uint32_t ICIMVAU;
534  __OM uint32_t DCIMVAC;
535  __OM uint32_t DCISW;
536  __OM uint32_t DCCMVAU;
537  __OM uint32_t DCCMVAC;
538  __OM uint32_t DCCSW;
539  __OM uint32_t DCCIMVAC;
540  __OM uint32_t DCCISW;
541  uint32_t RESERVED7[6U];
542  __IOM uint32_t ITCMCR;
543  __IOM uint32_t DTCMCR;
544  __IOM uint32_t AHBPCR;
545  __IOM uint32_t CACR;
546  __IOM uint32_t AHBSCR;
547  uint32_t RESERVED8[1U];
548  __IOM uint32_t ABFSR;
549 } SCB_Type;
550 
551 /* SCB CPUID Register Definitions */
552 #define SCB_CPUID_IMPLEMENTER_Pos 24U
553 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
555 #define SCB_CPUID_VARIANT_Pos 20U
556 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
558 #define SCB_CPUID_ARCHITECTURE_Pos 16U
559 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
561 #define SCB_CPUID_PARTNO_Pos 4U
562 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
564 #define SCB_CPUID_REVISION_Pos 0U
565 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
567 /* SCB Interrupt Control State Register Definitions */
568 #define SCB_ICSR_PENDNMISET_Pos 31U
569 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos)
571 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos
572 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk
574 #define SCB_ICSR_PENDNMICLR_Pos 30U
575 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos)
577 #define SCB_ICSR_PENDSVSET_Pos 28U
578 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
580 #define SCB_ICSR_PENDSVCLR_Pos 27U
581 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
583 #define SCB_ICSR_PENDSTSET_Pos 26U
584 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
586 #define SCB_ICSR_PENDSTCLR_Pos 25U
587 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
589 #define SCB_ICSR_STTNS_Pos 24U
590 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos)
592 #define SCB_ICSR_ISRPREEMPT_Pos 23U
593 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
595 #define SCB_ICSR_ISRPENDING_Pos 22U
596 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
598 #define SCB_ICSR_VECTPENDING_Pos 12U
599 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
601 #define SCB_ICSR_RETTOBASE_Pos 11U
602 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
604 #define SCB_ICSR_VECTACTIVE_Pos 0U
605 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
607 /* SCB Vector Table Offset Register Definitions */
608 #define SCB_VTOR_TBLOFF_Pos 7U
609 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
611 /* SCB Application Interrupt and Reset Control Register Definitions */
612 #define SCB_AIRCR_VECTKEY_Pos 16U
613 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
615 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
616 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
618 #define SCB_AIRCR_ENDIANESS_Pos 15U
619 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
621 #define SCB_AIRCR_PRIS_Pos 14U
622 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos)
624 #define SCB_AIRCR_BFHFNMINS_Pos 13U
625 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos)
627 #define SCB_AIRCR_PRIGROUP_Pos 8U
628 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
630 #define SCB_AIRCR_SYSRESETREQS_Pos 3U
631 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos)
633 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
634 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
636 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
637 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
639 /* SCB System Control Register Definitions */
640 #define SCB_SCR_SEVONPEND_Pos 4U
641 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
643 #define SCB_SCR_SLEEPDEEPS_Pos 3U
644 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos)
646 #define SCB_SCR_SLEEPDEEP_Pos 2U
647 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
649 #define SCB_SCR_SLEEPONEXIT_Pos 1U
650 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
652 /* SCB Configuration Control Register Definitions */
653 #define SCB_CCR_BP_Pos 18U
654 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos)
656 #define SCB_CCR_IC_Pos 17U
657 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos)
659 #define SCB_CCR_DC_Pos 16U
660 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos)
662 #define SCB_CCR_STKOFHFNMIGN_Pos 10U
663 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos)
665 #define SCB_CCR_BFHFNMIGN_Pos 8U
666 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
668 #define SCB_CCR_DIV_0_TRP_Pos 4U
669 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
671 #define SCB_CCR_UNALIGN_TRP_Pos 3U
672 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
674 #define SCB_CCR_USERSETMPEND_Pos 1U
675 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
677 /* SCB System Handler Control and State Register Definitions */
678 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U
679 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos)
681 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U
682 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos)
684 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U
685 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos)
687 #define SCB_SHCSR_USGFAULTENA_Pos 18U
688 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
690 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
691 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
693 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
694 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
696 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
697 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
699 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
700 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
702 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
703 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
705 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
706 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
708 #define SCB_SHCSR_SYSTICKACT_Pos 11U
709 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
711 #define SCB_SHCSR_PENDSVACT_Pos 10U
712 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
714 #define SCB_SHCSR_MONITORACT_Pos 8U
715 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
717 #define SCB_SHCSR_SVCALLACT_Pos 7U
718 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
720 #define SCB_SHCSR_NMIACT_Pos 5U
721 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos)
723 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U
724 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos)
726 #define SCB_SHCSR_USGFAULTACT_Pos 3U
727 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
729 #define SCB_SHCSR_HARDFAULTACT_Pos 2U
730 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos)
732 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
733 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
735 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
736 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
738 /* SCB Configurable Fault Status Register Definitions */
739 #define SCB_CFSR_USGFAULTSR_Pos 16U
740 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
742 #define SCB_CFSR_BUSFAULTSR_Pos 8U
743 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
745 #define SCB_CFSR_MEMFAULTSR_Pos 0U
746 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
748 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
749 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
750 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
752 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
753 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
755 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
756 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
758 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
759 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
761 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
762 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
764 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
765 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
767 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
768 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
769 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
771 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
772 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
774 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
775 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
777 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
778 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
780 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
781 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
783 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
784 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
786 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
787 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
789 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
790 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
791 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
793 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
794 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
796 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U)
797 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos)
799 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
800 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
802 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
803 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
805 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
806 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
808 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
809 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
811 /* SCB Hard Fault Status Register Definitions */
812 #define SCB_HFSR_DEBUGEVT_Pos 31U
813 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
815 #define SCB_HFSR_FORCED_Pos 30U
816 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
818 #define SCB_HFSR_VECTTBL_Pos 1U
819 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
821 /* SCB Debug Fault Status Register Definitions */
822 #define SCB_DFSR_EXTERNAL_Pos 4U
823 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
825 #define SCB_DFSR_VCATCH_Pos 3U
826 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
828 #define SCB_DFSR_DWTTRAP_Pos 2U
829 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
831 #define SCB_DFSR_BKPT_Pos 1U
832 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
834 #define SCB_DFSR_HALTED_Pos 0U
835 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
837 /* SCB Non-Secure Access Control Register Definitions */
838 #define SCB_NSACR_CP11_Pos 11U
839 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos)
841 #define SCB_NSACR_CP10_Pos 10U
842 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos)
844 #define SCB_NSACR_CPn_Pos 0U
845 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/)
847 /* SCB Cache Level ID Register Definitions */
848 #define SCB_CLIDR_LOUU_Pos 27U
849 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos)
851 #define SCB_CLIDR_LOC_Pos 24U
852 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos)
854 /* SCB Cache Type Register Definitions */
855 #define SCB_CTR_FORMAT_Pos 29U
856 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos)
858 #define SCB_CTR_CWG_Pos 24U
859 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos)
861 #define SCB_CTR_ERG_Pos 20U
862 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos)
864 #define SCB_CTR_DMINLINE_Pos 16U
865 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos)
867 #define SCB_CTR_IMINLINE_Pos 0U
868 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/)
870 /* SCB Cache Size ID Register Definitions */
871 #define SCB_CCSIDR_WT_Pos 31U
872 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos)
874 #define SCB_CCSIDR_WB_Pos 30U
875 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos)
877 #define SCB_CCSIDR_RA_Pos 29U
878 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos)
880 #define SCB_CCSIDR_WA_Pos 28U
881 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos)
883 #define SCB_CCSIDR_NUMSETS_Pos 13U
884 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos)
886 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U
887 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos)
889 #define SCB_CCSIDR_LINESIZE_Pos 0U
890 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/)
892 /* SCB Cache Size Selection Register Definitions */
893 #define SCB_CSSELR_LEVEL_Pos 1U
894 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos)
896 #define SCB_CSSELR_IND_Pos 0U
897 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/)
899 /* SCB Software Triggered Interrupt Register Definitions */
900 #define SCB_STIR_INTID_Pos 0U
901 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/)
903 /* SCB D-Cache Invalidate by Set-way Register Definitions */
904 #define SCB_DCISW_WAY_Pos 30U
905 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos)
907 #define SCB_DCISW_SET_Pos 5U
908 #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos)
910 /* SCB D-Cache Clean by Set-way Register Definitions */
911 #define SCB_DCCSW_WAY_Pos 30U
912 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos)
914 #define SCB_DCCSW_SET_Pos 5U
915 #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos)
917 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
918 #define SCB_DCCISW_WAY_Pos 30U
919 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos)
921 #define SCB_DCCISW_SET_Pos 5U
922 #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos)
924 /* Instruction Tightly-Coupled Memory Control Register Definitions */
925 #define SCB_ITCMCR_SZ_Pos 3U
926 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos)
928 #define SCB_ITCMCR_RETEN_Pos 2U
929 #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos)
931 #define SCB_ITCMCR_RMW_Pos 1U
932 #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos)
934 #define SCB_ITCMCR_EN_Pos 0U
935 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/)
937 /* Data Tightly-Coupled Memory Control Register Definitions */
938 #define SCB_DTCMCR_SZ_Pos 3U
939 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos)
941 #define SCB_DTCMCR_RETEN_Pos 2U
942 #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos)
944 #define SCB_DTCMCR_RMW_Pos 1U
945 #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos)
947 #define SCB_DTCMCR_EN_Pos 0U
948 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/)
950 /* AHBP Control Register Definitions */
951 #define SCB_AHBPCR_SZ_Pos 1U
952 #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos)
954 #define SCB_AHBPCR_EN_Pos 0U
955 #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/)
957 /* L1 Cache Control Register Definitions */
958 #define SCB_CACR_FORCEWT_Pos 2U
959 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos)
961 #define SCB_CACR_ECCEN_Pos 1U
962 #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos)
964 #define SCB_CACR_SIWT_Pos 0U
965 #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/)
967 /* AHBS Control Register Definitions */
968 #define SCB_AHBSCR_INITCOUNT_Pos 11U
969 #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos)
971 #define SCB_AHBSCR_TPRI_Pos 2U
972 #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos)
974 #define SCB_AHBSCR_CTL_Pos 0U
975 #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/)
977 /* Auxiliary Bus Fault Status Register Definitions */
978 #define SCB_ABFSR_AXIMTYPE_Pos 8U
979 #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos)
981 #define SCB_ABFSR_EPPB_Pos 4U
982 #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos)
984 #define SCB_ABFSR_AXIM_Pos 3U
985 #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos)
987 #define SCB_ABFSR_AHBP_Pos 2U
988 #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos)
990 #define SCB_ABFSR_DTCM_Pos 1U
991 #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos)
993 #define SCB_ABFSR_ITCM_Pos 0U
994 #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/)
996 
1009 typedef struct
1010 {
1011  uint32_t RESERVED0[1U];
1012  __IM uint32_t ICTR;
1013  __IOM uint32_t ACTLR;
1014  __IOM uint32_t CPPWR;
1015 } SCnSCB_Type;
1016 
1017 /* Interrupt Controller Type Register Definitions */
1018 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
1019 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
1021 
1034 typedef struct
1035 {
1036  __IOM uint32_t CTRL;
1037  __IOM uint32_t LOAD;
1038  __IOM uint32_t VAL;
1039  __IM uint32_t CALIB;
1040 } SysTick_Type;
1041 
1042 /* SysTick Control / Status Register Definitions */
1043 #define SysTick_CTRL_COUNTFLAG_Pos 16U
1044 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
1046 #define SysTick_CTRL_CLKSOURCE_Pos 2U
1047 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
1049 #define SysTick_CTRL_TICKINT_Pos 1U
1050 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
1052 #define SysTick_CTRL_ENABLE_Pos 0U
1053 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
1055 /* SysTick Reload Register Definitions */
1056 #define SysTick_LOAD_RELOAD_Pos 0U
1057 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
1059 /* SysTick Current Register Definitions */
1060 #define SysTick_VAL_CURRENT_Pos 0U
1061 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
1063 /* SysTick Calibration Register Definitions */
1064 #define SysTick_CALIB_NOREF_Pos 31U
1065 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
1067 #define SysTick_CALIB_SKEW_Pos 30U
1068 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
1070 #define SysTick_CALIB_TENMS_Pos 0U
1071 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
1073 
1086 typedef struct
1087 {
1088  __OM union
1089  {
1090  __OM uint8_t u8;
1091  __OM uint16_t u16;
1092  __OM uint32_t u32;
1093  } PORT [32U];
1094  uint32_t RESERVED0[864U];
1095  __IOM uint32_t TER;
1096  uint32_t RESERVED1[15U];
1097  __IOM uint32_t TPR;
1098  uint32_t RESERVED2[15U];
1099  __IOM uint32_t TCR;
1100  uint32_t RESERVED3[29U];
1101  __OM uint32_t IWR;
1102  __IM uint32_t IRR;
1103  __IOM uint32_t IMCR;
1104  uint32_t RESERVED4[43U];
1105  __OM uint32_t LAR;
1106  __IM uint32_t LSR;
1107  uint32_t RESERVED5[1U];
1108  __IM uint32_t DEVARCH;
1109  uint32_t RESERVED6[4U];
1110  __IM uint32_t PID4;
1111  __IM uint32_t PID5;
1112  __IM uint32_t PID6;
1113  __IM uint32_t PID7;
1114  __IM uint32_t PID0;
1115  __IM uint32_t PID1;
1116  __IM uint32_t PID2;
1117  __IM uint32_t PID3;
1118  __IM uint32_t CID0;
1119  __IM uint32_t CID1;
1120  __IM uint32_t CID2;
1121  __IM uint32_t CID3;
1122 } ITM_Type;
1123 
1124 /* ITM Stimulus Port Register Definitions */
1125 #define ITM_STIM_DISABLED_Pos 1U
1126 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos)
1128 #define ITM_STIM_FIFOREADY_Pos 0U
1129 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/)
1131 /* ITM Trace Privilege Register Definitions */
1132 #define ITM_TPR_PRIVMASK_Pos 0U
1133 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
1135 /* ITM Trace Control Register Definitions */
1136 #define ITM_TCR_BUSY_Pos 23U
1137 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
1139 #define ITM_TCR_TRACEBUSID_Pos 16U
1140 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos)
1142 #define ITM_TCR_GTSFREQ_Pos 10U
1143 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
1145 #define ITM_TCR_TSPRESCALE_Pos 8U
1146 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos)
1148 #define ITM_TCR_STALLENA_Pos 5U
1149 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos)
1151 #define ITM_TCR_SWOENA_Pos 4U
1152 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
1154 #define ITM_TCR_DWTENA_Pos 3U
1155 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
1157 #define ITM_TCR_SYNCENA_Pos 2U
1158 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
1160 #define ITM_TCR_TSENA_Pos 1U
1161 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
1163 #define ITM_TCR_ITMENA_Pos 0U
1164 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
1166 /* ITM Integration Write Register Definitions */
1167 #define ITM_IWR_ATVALIDM_Pos 0U
1168 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
1170 /* ITM Integration Read Register Definitions */
1171 #define ITM_IRR_ATREADYM_Pos 0U
1172 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
1174 /* ITM Integration Mode Control Register Definitions */
1175 #define ITM_IMCR_INTEGRATION_Pos 0U
1176 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
1178 /* ITM Lock Status Register Definitions */
1179 #define ITM_LSR_ByteAcc_Pos 2U
1180 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
1182 #define ITM_LSR_Access_Pos 1U
1183 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
1185 #define ITM_LSR_Present_Pos 0U
1186 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
1188  /* end of group CMSIS_ITM */
1189 
1190 
1201 typedef struct
1202 {
1203  __IOM uint32_t CTRL;
1204  __IOM uint32_t CYCCNT;
1205  __IOM uint32_t CPICNT;
1206  __IOM uint32_t EXCCNT;
1207  __IOM uint32_t SLEEPCNT;
1208  __IOM uint32_t LSUCNT;
1209  __IOM uint32_t FOLDCNT;
1210  __IM uint32_t PCSR;
1211  __IOM uint32_t COMP0;
1212  uint32_t RESERVED1[1U];
1213  __IOM uint32_t FUNCTION0;
1214  uint32_t RESERVED2[1U];
1215  __IOM uint32_t COMP1;
1216  uint32_t RESERVED3[1U];
1217  __IOM uint32_t FUNCTION1;
1218  uint32_t RESERVED4[1U];
1219  __IOM uint32_t COMP2;
1220  uint32_t RESERVED5[1U];
1221  __IOM uint32_t FUNCTION2;
1222  uint32_t RESERVED6[1U];
1223  __IOM uint32_t COMP3;
1224  uint32_t RESERVED7[1U];
1225  __IOM uint32_t FUNCTION3;
1226  uint32_t RESERVED8[1U];
1227  __IOM uint32_t COMP4;
1228  uint32_t RESERVED9[1U];
1229  __IOM uint32_t FUNCTION4;
1230  uint32_t RESERVED10[1U];
1231  __IOM uint32_t COMP5;
1232  uint32_t RESERVED11[1U];
1233  __IOM uint32_t FUNCTION5;
1234  uint32_t RESERVED12[1U];
1235  __IOM uint32_t COMP6;
1236  uint32_t RESERVED13[1U];
1237  __IOM uint32_t FUNCTION6;
1238  uint32_t RESERVED14[1U];
1239  __IOM uint32_t COMP7;
1240  uint32_t RESERVED15[1U];
1241  __IOM uint32_t FUNCTION7;
1242  uint32_t RESERVED16[1U];
1243  __IOM uint32_t COMP8;
1244  uint32_t RESERVED17[1U];
1245  __IOM uint32_t FUNCTION8;
1246  uint32_t RESERVED18[1U];
1247  __IOM uint32_t COMP9;
1248  uint32_t RESERVED19[1U];
1249  __IOM uint32_t FUNCTION9;
1250  uint32_t RESERVED20[1U];
1251  __IOM uint32_t COMP10;
1252  uint32_t RESERVED21[1U];
1253  __IOM uint32_t FUNCTION10;
1254  uint32_t RESERVED22[1U];
1255  __IOM uint32_t COMP11;
1256  uint32_t RESERVED23[1U];
1257  __IOM uint32_t FUNCTION11;
1258  uint32_t RESERVED24[1U];
1259  __IOM uint32_t COMP12;
1260  uint32_t RESERVED25[1U];
1261  __IOM uint32_t FUNCTION12;
1262  uint32_t RESERVED26[1U];
1263  __IOM uint32_t COMP13;
1264  uint32_t RESERVED27[1U];
1265  __IOM uint32_t FUNCTION13;
1266  uint32_t RESERVED28[1U];
1267  __IOM uint32_t COMP14;
1268  uint32_t RESERVED29[1U];
1269  __IOM uint32_t FUNCTION14;
1270  uint32_t RESERVED30[1U];
1271  __IOM uint32_t COMP15;
1272  uint32_t RESERVED31[1U];
1273  __IOM uint32_t FUNCTION15;
1274  uint32_t RESERVED32[934U];
1275  __IM uint32_t LSR;
1276  uint32_t RESERVED33[1U];
1277  __IM uint32_t DEVARCH;
1278 } DWT_Type;
1279 
1280 /* DWT Control Register Definitions */
1281 #define DWT_CTRL_NUMCOMP_Pos 28U
1282 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
1284 #define DWT_CTRL_NOTRCPKT_Pos 27U
1285 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
1287 #define DWT_CTRL_NOEXTTRIG_Pos 26U
1288 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
1290 #define DWT_CTRL_NOCYCCNT_Pos 25U
1291 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
1293 #define DWT_CTRL_NOPRFCNT_Pos 24U
1294 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
1296 #define DWT_CTRL_CYCDISS_Pos 23U
1297 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos)
1299 #define DWT_CTRL_CYCEVTENA_Pos 22U
1300 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
1302 #define DWT_CTRL_FOLDEVTENA_Pos 21U
1303 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
1305 #define DWT_CTRL_LSUEVTENA_Pos 20U
1306 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
1308 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
1309 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
1311 #define DWT_CTRL_EXCEVTENA_Pos 18U
1312 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
1314 #define DWT_CTRL_CPIEVTENA_Pos 17U
1315 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
1317 #define DWT_CTRL_EXCTRCENA_Pos 16U
1318 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
1320 #define DWT_CTRL_PCSAMPLENA_Pos 12U
1321 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
1323 #define DWT_CTRL_SYNCTAP_Pos 10U
1324 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
1326 #define DWT_CTRL_CYCTAP_Pos 9U
1327 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
1329 #define DWT_CTRL_POSTINIT_Pos 5U
1330 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
1332 #define DWT_CTRL_POSTPRESET_Pos 1U
1333 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
1335 #define DWT_CTRL_CYCCNTENA_Pos 0U
1336 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
1338 /* DWT CPI Count Register Definitions */
1339 #define DWT_CPICNT_CPICNT_Pos 0U
1340 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1342 /* DWT Exception Overhead Count Register Definitions */
1343 #define DWT_EXCCNT_EXCCNT_Pos 0U
1344 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1346 /* DWT Sleep Count Register Definitions */
1347 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1348 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1350 /* DWT LSU Count Register Definitions */
1351 #define DWT_LSUCNT_LSUCNT_Pos 0U
1352 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1354 /* DWT Folded-instruction Count Register Definitions */
1355 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
1356 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1358 /* DWT Comparator Function Register Definitions */
1359 #define DWT_FUNCTION_ID_Pos 27U
1360 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos)
1362 #define DWT_FUNCTION_MATCHED_Pos 24U
1363 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1365 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
1366 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1368 #define DWT_FUNCTION_ACTION_Pos 4U
1369 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos)
1371 #define DWT_FUNCTION_MATCH_Pos 0U
1372 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/)
1374  /* end of group CMSIS_DWT */
1375 
1376 
1387 typedef struct
1388 {
1389  __IM uint32_t SSPSR;
1390  __IOM uint32_t CSPSR;
1391  uint32_t RESERVED0[2U];
1392  __IOM uint32_t ACPR;
1393  uint32_t RESERVED1[55U];
1394  __IOM uint32_t SPPR;
1395  uint32_t RESERVED2[131U];
1396  __IM uint32_t FFSR;
1397  __IOM uint32_t FFCR;
1398  __IOM uint32_t PSCR;
1399  uint32_t RESERVED3[759U];
1400  __IM uint32_t TRIGGER;
1401  __IM uint32_t ITFTTD0;
1402  __IOM uint32_t ITATBCTR2;
1403  uint32_t RESERVED4[1U];
1404  __IM uint32_t ITATBCTR0;
1405  __IM uint32_t ITFTTD1;
1406  __IOM uint32_t ITCTRL;
1407  uint32_t RESERVED5[39U];
1408  __IOM uint32_t CLAIMSET;
1409  __IOM uint32_t CLAIMCLR;
1410  uint32_t RESERVED7[8U];
1411  __IM uint32_t DEVID;
1412  __IM uint32_t DEVTYPE;
1413 } TPI_Type;
1414 
1415 /* TPI Asynchronous Clock Prescaler Register Definitions */
1416 #define TPI_ACPR_PRESCALER_Pos 0U
1417 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
1419 /* TPI Selected Pin Protocol Register Definitions */
1420 #define TPI_SPPR_TXMODE_Pos 0U
1421 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1423 /* TPI Formatter and Flush Status Register Definitions */
1424 #define TPI_FFSR_FtNonStop_Pos 3U
1425 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1427 #define TPI_FFSR_TCPresent_Pos 2U
1428 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1430 #define TPI_FFSR_FtStopped_Pos 1U
1431 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1433 #define TPI_FFSR_FlInProg_Pos 0U
1434 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1436 /* TPI Formatter and Flush Control Register Definitions */
1437 #define TPI_FFCR_TrigIn_Pos 8U
1438 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1440 #define TPI_FFCR_FOnMan_Pos 6U
1441 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)
1443 #define TPI_FFCR_EnFCont_Pos 1U
1444 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1446 /* TPI TRIGGER Register Definitions */
1447 #define TPI_TRIGGER_TRIGGER_Pos 0U
1448 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
1450 /* TPI Integration Test FIFO Test Data 0 Register Definitions */
1451 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U
1452 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)
1454 #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U
1455 #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)
1457 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U
1458 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)
1460 #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U
1461 #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)
1463 #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U
1464 #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
1466 #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U
1467 #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)
1469 #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U
1470 #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/)
1472 /* TPI Integration Test ATB Control Register 2 Register Definitions */
1473 #define TPI_ITATBCTR2_AFVALID2S_Pos 1U
1474 #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)
1476 #define TPI_ITATBCTR2_AFVALID1S_Pos 1U
1477 #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)
1479 #define TPI_ITATBCTR2_ATREADY2S_Pos 0U
1480 #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)
1482 #define TPI_ITATBCTR2_ATREADY1S_Pos 0U
1483 #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)
1485 /* TPI Integration Test FIFO Test Data 1 Register Definitions */
1486 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U
1487 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)
1489 #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U
1490 #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)
1492 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U
1493 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)
1495 #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U
1496 #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)
1498 #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U
1499 #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
1501 #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U
1502 #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)
1504 #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U
1505 #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/)
1507 /* TPI Integration Test ATB Control Register 0 Definitions */
1508 #define TPI_ITATBCTR0_AFVALID2S_Pos 1U
1509 #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)
1511 #define TPI_ITATBCTR0_AFVALID1S_Pos 1U
1512 #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)
1514 #define TPI_ITATBCTR0_ATREADY2S_Pos 0U
1515 #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)
1517 #define TPI_ITATBCTR0_ATREADY1S_Pos 0U
1518 #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)
1520 /* TPI Integration Mode Control Register Definitions */
1521 #define TPI_ITCTRL_Mode_Pos 0U
1522 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
1524 /* TPI DEVID Register Definitions */
1525 #define TPI_DEVID_NRZVALID_Pos 11U
1526 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1528 #define TPI_DEVID_MANCVALID_Pos 10U
1529 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1531 #define TPI_DEVID_PTINVALID_Pos 9U
1532 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1534 #define TPI_DEVID_FIFOSZ_Pos 6U
1535 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)
1537 #define TPI_DEVID_NrTraceInput_Pos 0U
1538 #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
1540 /* TPI DEVTYPE Register Definitions */
1541 #define TPI_DEVTYPE_SubType_Pos 4U
1542 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1544 #define TPI_DEVTYPE_MajorType_Pos 0U
1545 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1547  /* end of group CMSIS_TPI */
1548 
1549 
1550 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1551 
1561 typedef struct
1562 {
1563  __IM uint32_t TYPE;
1564  __IOM uint32_t CTRL;
1565  __IOM uint32_t RNR;
1566  __IOM uint32_t RBAR;
1567  __IOM uint32_t RLAR;
1568  __IOM uint32_t RBAR_A1;
1569  __IOM uint32_t RLAR_A1;
1570  __IOM uint32_t RBAR_A2;
1571  __IOM uint32_t RLAR_A2;
1572  __IOM uint32_t RBAR_A3;
1573  __IOM uint32_t RLAR_A3;
1574  uint32_t RESERVED0[1];
1575  union {
1576  __IOM uint32_t MAIR[2];
1577  struct {
1578  __IOM uint32_t MAIR0;
1579  __IOM uint32_t MAIR1;
1580  };
1581  };
1582 } MPU_Type;
1583 
1584 #define MPU_TYPE_RALIASES 4U
1585 
1586 /* MPU Type Register Definitions */
1587 #define MPU_TYPE_IREGION_Pos 16U
1588 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1590 #define MPU_TYPE_DREGION_Pos 8U
1591 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1593 #define MPU_TYPE_SEPARATE_Pos 0U
1594 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1596 /* MPU Control Register Definitions */
1597 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1598 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1600 #define MPU_CTRL_HFNMIENA_Pos 1U
1601 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1603 #define MPU_CTRL_ENABLE_Pos 0U
1604 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1606 /* MPU Region Number Register Definitions */
1607 #define MPU_RNR_REGION_Pos 0U
1608 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1610 /* MPU Region Base Address Register Definitions */
1611 #define MPU_RBAR_BASE_Pos 5U
1612 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos)
1614 #define MPU_RBAR_SH_Pos 3U
1615 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos)
1617 #define MPU_RBAR_AP_Pos 1U
1618 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos)
1620 #define MPU_RBAR_XN_Pos 0U
1621 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/)
1623 /* MPU Region Limit Address Register Definitions */
1624 #define MPU_RLAR_LIMIT_Pos 5U
1625 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos)
1627 #define MPU_RLAR_AttrIndx_Pos 1U
1628 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
1630 #define MPU_RLAR_EN_Pos 0U
1631 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/)
1633 /* MPU Memory Attribute Indirection Register 0 Definitions */
1634 #define MPU_MAIR0_Attr3_Pos 24U
1635 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos)
1637 #define MPU_MAIR0_Attr2_Pos 16U
1638 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos)
1640 #define MPU_MAIR0_Attr1_Pos 8U
1641 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos)
1643 #define MPU_MAIR0_Attr0_Pos 0U
1644 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/)
1646 /* MPU Memory Attribute Indirection Register 1 Definitions */
1647 #define MPU_MAIR1_Attr7_Pos 24U
1648 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos)
1650 #define MPU_MAIR1_Attr6_Pos 16U
1651 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos)
1653 #define MPU_MAIR1_Attr5_Pos 8U
1654 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos)
1656 #define MPU_MAIR1_Attr4_Pos 0U
1657 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/)
1659 
1660 #endif
1661 
1662 
1663 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1664 
1674 typedef struct
1675 {
1676  __IOM uint32_t CTRL;
1677  __IM uint32_t TYPE;
1678 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1679  __IOM uint32_t RNR;
1680  __IOM uint32_t RBAR;
1681  __IOM uint32_t RLAR;
1682 #else
1683  uint32_t RESERVED0[3];
1684 #endif
1685  __IOM uint32_t SFSR;
1686  __IOM uint32_t SFAR;
1687 } SAU_Type;
1688 
1689 /* SAU Control Register Definitions */
1690 #define SAU_CTRL_ALLNS_Pos 1U
1691 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos)
1693 #define SAU_CTRL_ENABLE_Pos 0U
1694 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/)
1696 /* SAU Type Register Definitions */
1697 #define SAU_TYPE_SREGION_Pos 0U
1698 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/)
1700 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1701 /* SAU Region Number Register Definitions */
1702 #define SAU_RNR_REGION_Pos 0U
1703 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/)
1705 /* SAU Region Base Address Register Definitions */
1706 #define SAU_RBAR_BADDR_Pos 5U
1707 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos)
1709 /* SAU Region Limit Address Register Definitions */
1710 #define SAU_RLAR_LADDR_Pos 5U
1711 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos)
1713 #define SAU_RLAR_NSC_Pos 1U
1714 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos)
1716 #define SAU_RLAR_ENABLE_Pos 0U
1717 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/)
1719 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1720 
1721 /* Secure Fault Status Register Definitions */
1722 #define SAU_SFSR_LSERR_Pos 7U
1723 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos)
1725 #define SAU_SFSR_SFARVALID_Pos 6U
1726 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos)
1728 #define SAU_SFSR_LSPERR_Pos 5U
1729 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos)
1731 #define SAU_SFSR_INVTRAN_Pos 4U
1732 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos)
1734 #define SAU_SFSR_AUVIOL_Pos 3U
1735 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos)
1737 #define SAU_SFSR_INVER_Pos 2U
1738 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos)
1740 #define SAU_SFSR_INVIS_Pos 1U
1741 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos)
1743 #define SAU_SFSR_INVEP_Pos 0U
1744 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/)
1746 
1747 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1748 
1749 
1760 typedef struct
1761 {
1762  uint32_t RESERVED0[1U];
1763  __IOM uint32_t FPCCR;
1764  __IOM uint32_t FPCAR;
1765  __IOM uint32_t FPDSCR;
1766  __IM uint32_t MVFR0;
1767  __IM uint32_t MVFR1;
1768 } FPU_Type;
1769 
1770 /* Floating-Point Context Control Register Definitions */
1771 #define FPU_FPCCR_ASPEN_Pos 31U
1772 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1774 #define FPU_FPCCR_LSPEN_Pos 30U
1775 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1777 #define FPU_FPCCR_LSPENS_Pos 29U
1778 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos)
1780 #define FPU_FPCCR_CLRONRET_Pos 28U
1781 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos)
1783 #define FPU_FPCCR_CLRONRETS_Pos 27U
1784 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos)
1786 #define FPU_FPCCR_TS_Pos 26U
1787 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos)
1789 #define FPU_FPCCR_UFRDY_Pos 10U
1790 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos)
1792 #define FPU_FPCCR_SPLIMVIOL_Pos 9U
1793 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos)
1795 #define FPU_FPCCR_MONRDY_Pos 8U
1796 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1798 #define FPU_FPCCR_SFRDY_Pos 7U
1799 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos)
1801 #define FPU_FPCCR_BFRDY_Pos 6U
1802 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1804 #define FPU_FPCCR_MMRDY_Pos 5U
1805 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1807 #define FPU_FPCCR_HFRDY_Pos 4U
1808 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1810 #define FPU_FPCCR_THREAD_Pos 3U
1811 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1813 #define FPU_FPCCR_S_Pos 2U
1814 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos)
1816 #define FPU_FPCCR_USER_Pos 1U
1817 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1819 #define FPU_FPCCR_LSPACT_Pos 0U
1820 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
1822 /* Floating-Point Context Address Register Definitions */
1823 #define FPU_FPCAR_ADDRESS_Pos 3U
1824 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1826 /* Floating-Point Default Status Control Register Definitions */
1827 #define FPU_FPDSCR_AHP_Pos 26U
1828 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1830 #define FPU_FPDSCR_DN_Pos 25U
1831 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1833 #define FPU_FPDSCR_FZ_Pos 24U
1834 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1836 #define FPU_FPDSCR_RMode_Pos 22U
1837 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1839 /* Media and FP Feature Register 0 Definitions */
1840 #define FPU_MVFR0_FP_rounding_modes_Pos 28U
1841 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1843 #define FPU_MVFR0_Short_vectors_Pos 24U
1844 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1846 #define FPU_MVFR0_Square_root_Pos 20U
1847 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1849 #define FPU_MVFR0_Divide_Pos 16U
1850 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1852 #define FPU_MVFR0_FP_excep_trapping_Pos 12U
1853 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1855 #define FPU_MVFR0_Double_precision_Pos 8U
1856 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1858 #define FPU_MVFR0_Single_precision_Pos 4U
1859 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1861 #define FPU_MVFR0_A_SIMD_registers_Pos 0U
1862 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
1864 /* Media and FP Feature Register 1 Definitions */
1865 #define FPU_MVFR1_FP_fused_MAC_Pos 28U
1866 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1868 #define FPU_MVFR1_FP_HPFP_Pos 24U
1869 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1871 #define FPU_MVFR1_D_NaN_mode_Pos 4U
1872 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1874 #define FPU_MVFR1_FtZ_mode_Pos 0U
1875 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
1877 
1890 typedef struct
1891 {
1892  __IOM uint32_t DHCSR;
1893  __OM uint32_t DCRSR;
1894  __IOM uint32_t DCRDR;
1895  __IOM uint32_t DEMCR;
1896  uint32_t RESERVED4[1U];
1897  __IOM uint32_t DAUTHCTRL;
1898  __IOM uint32_t DSCSR;
1899 } CoreDebug_Type;
1900 
1901 /* Debug Halting Control and Status Register Definitions */
1902 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1903 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1905 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U
1906 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos)
1908 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1909 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1911 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1912 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1914 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1915 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1917 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1918 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1920 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1921 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1923 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1924 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1926 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1927 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1929 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1930 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1932 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1933 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1935 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1936 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1938 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1939 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1941 /* Debug Core Register Selector Register Definitions */
1942 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1943 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1945 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1946 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1948 /* Debug Exception and Monitor Control Register Definitions */
1949 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1950 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1952 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1953 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1955 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1956 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1958 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1959 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1961 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1962 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1964 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1965 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1967 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1968 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1970 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1971 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1973 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1974 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1976 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1977 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1979 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1980 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1982 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1983 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1985 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1986 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1988 /* Debug Authentication Control Register Definitions */
1989 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U
1990 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos)
1992 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U
1993 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos)
1995 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U
1996 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos)
1998 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U
1999 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/)
2001 /* Debug Security Control and Status Register Definitions */
2002 #define CoreDebug_DSCSR_CDS_Pos 16U
2003 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos)
2005 #define CoreDebug_DSCSR_SBRSEL_Pos 1U
2006 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos)
2008 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U
2009 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/)
2011 
2027 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
2028 
2035 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
2036 
2047 /* Memory mapping of Core Hardware */
2048  #define SCS_BASE (0xE000E000UL)
2049  #define ITM_BASE (0xE0000000UL)
2050  #define DWT_BASE (0xE0001000UL)
2051  #define TPI_BASE (0xE0040000UL)
2052  #define CoreDebug_BASE (0xE000EDF0UL)
2053  #define SysTick_BASE (SCS_BASE + 0x0010UL)
2054  #define NVIC_BASE (SCS_BASE + 0x0100UL)
2055  #define SCB_BASE (SCS_BASE + 0x0D00UL)
2057  #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
2058  #define SCB ((SCB_Type *) SCB_BASE )
2059  #define SysTick ((SysTick_Type *) SysTick_BASE )
2060  #define NVIC ((NVIC_Type *) NVIC_BASE )
2061  #define ITM ((ITM_Type *) ITM_BASE )
2062  #define DWT ((DWT_Type *) DWT_BASE )
2063  #define TPI ((TPI_Type *) TPI_BASE )
2064  #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE )
2066  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2067  #define MPU_BASE (SCS_BASE + 0x0D90UL)
2068  #define MPU ((MPU_Type *) MPU_BASE )
2069  #endif
2070 
2071  #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2072  #define SAU_BASE (SCS_BASE + 0x0DD0UL)
2073  #define SAU ((SAU_Type *) SAU_BASE )
2074  #endif
2075 
2076  #define FPU_BASE (SCS_BASE + 0x0F30UL)
2077  #define FPU ((FPU_Type *) FPU_BASE )
2079 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2080  #define SCS_BASE_NS (0xE002E000UL)
2081  #define CoreDebug_BASE_NS (0xE002EDF0UL)
2082  #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL)
2083  #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL)
2084  #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL)
2086  #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS )
2087  #define SCB_NS ((SCB_Type *) SCB_BASE_NS )
2088  #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS )
2089  #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS )
2090  #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS)
2092  #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2093  #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL)
2094  #define MPU_NS ((MPU_Type *) MPU_BASE_NS )
2095  #endif
2096 
2097  #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL)
2098  #define FPU_NS ((FPU_Type *) FPU_BASE_NS )
2100 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2101 
2105 /*******************************************************************************
2106  * Hardware Abstraction Layer
2107  Core Function Interface contains:
2108  - Core NVIC Functions
2109  - Core SysTick Functions
2110  - Core Debug Functions
2111  - Core Register Access Functions
2112  ******************************************************************************/
2119 /* ########################## NVIC functions #################################### */
2127 #ifdef CMSIS_NVIC_VIRTUAL
2128  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2129  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2130  #endif
2131  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2132 #else
2133  #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2134  #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2135  #define NVIC_EnableIRQ __NVIC_EnableIRQ
2136  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2137  #define NVIC_DisableIRQ __NVIC_DisableIRQ
2138  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2139  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2140  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2141  #define NVIC_GetActive __NVIC_GetActive
2142  #define NVIC_SetPriority __NVIC_SetPriority
2143  #define NVIC_GetPriority __NVIC_GetPriority
2144  #define NVIC_SystemReset __NVIC_SystemReset
2145 #endif /* CMSIS_NVIC_VIRTUAL */
2146 
2147 #ifdef CMSIS_VECTAB_VIRTUAL
2148  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2149  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2150  #endif
2151  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2152 #else
2153  #define NVIC_SetVector __NVIC_SetVector
2154  #define NVIC_GetVector __NVIC_GetVector
2155 #endif /* (CMSIS_VECTAB_VIRTUAL) */
2156 
2157 #define NVIC_USER_IRQ_OFFSET 16
2158 
2159 
2160 /* Special LR values for Secure/Non-Secure call handling and exception handling */
2161 
2162 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
2163 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
2164 
2165 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
2166 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
2167 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
2168 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
2169 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
2170 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
2171 #define EXC_RETURN_SPSEL (0x00000002UL) /* bit [1] stack pointer used to restore context: 0=MSP 1=PSP */
2172 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
2173 
2174 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
2175 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
2176 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2177 #else
2178 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
2179 #endif
2180 
2181 
2191 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2192 {
2193  uint32_t reg_value;
2194  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2195 
2196  reg_value = SCB->AIRCR; /* read old register configuration */
2197  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2198  reg_value = (reg_value |
2199  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2200  (PriorityGroupTmp << 8U) ); /* Insert write key and priority group */
2201  SCB->AIRCR = reg_value;
2202 }
2203 
2204 
2210 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2211 {
2212  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2213 }
2214 
2215 
2222 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2223 {
2224  if ((int32_t)(IRQn) >= 0)
2225  {
2226  NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2227  }
2228 }
2229 
2230 
2239 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2240 {
2241  if ((int32_t)(IRQn) >= 0)
2242  {
2243  return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2244  }
2245  else
2246  {
2247  return(0U);
2248  }
2249 }
2250 
2251 
2258 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2259 {
2260  if ((int32_t)(IRQn) >= 0)
2261  {
2262  NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2263  __DSB();
2264  __ISB();
2265  }
2266 }
2267 
2268 
2277 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2278 {
2279  if ((int32_t)(IRQn) >= 0)
2280  {
2281  return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2282  }
2283  else
2284  {
2285  return(0U);
2286  }
2287 }
2288 
2289 
2296 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2297 {
2298  if ((int32_t)(IRQn) >= 0)
2299  {
2300  NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2301  }
2302 }
2303 
2304 
2311 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2312 {
2313  if ((int32_t)(IRQn) >= 0)
2314  {
2315  NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2316  }
2317 }
2318 
2319 
2328 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2329 {
2330  if ((int32_t)(IRQn) >= 0)
2331  {
2332  return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2333  }
2334  else
2335  {
2336  return(0U);
2337  }
2338 }
2339 
2340 
2341 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2342 
2350 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2351 {
2352  if ((int32_t)(IRQn) >= 0)
2353  {
2354  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2355  }
2356  else
2357  {
2358  return(0U);
2359  }
2360 }
2361 
2362 
2371 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2372 {
2373  if ((int32_t)(IRQn) >= 0)
2374  {
2375  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2376  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2377  }
2378  else
2379  {
2380  return(0U);
2381  }
2382 }
2383 
2384 
2393 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2394 {
2395  if ((int32_t)(IRQn) >= 0)
2396  {
2397  NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2398  return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2399  }
2400  else
2401  {
2402  return(0U);
2403  }
2404 }
2405 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2406 
2407 
2417 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2418 {
2419  if ((int32_t)(IRQn) >= 0)
2420  {
2421  NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2422  }
2423  else
2424  {
2425  SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2426  }
2427 }
2428 
2429 
2439 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2440 {
2441 
2442  if ((int32_t)(IRQn) >= 0)
2443  {
2444  return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2445  }
2446  else
2447  {
2448  return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2449  }
2450 }
2451 
2452 
2464 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2465 {
2466  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2467  uint32_t PreemptPriorityBits;
2468  uint32_t SubPriorityBits;
2469 
2470  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2471  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2472 
2473  return (
2474  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2475  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2476  );
2477 }
2478 
2479 
2491 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2492 {
2493  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2494  uint32_t PreemptPriorityBits;
2495  uint32_t SubPriorityBits;
2496 
2497  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2498  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2499 
2500  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2501  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2502 }
2503 
2504 
2514 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2515 {
2516  uint32_t *vectors = (uint32_t *)SCB->VTOR;
2517  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2518 }
2519 
2520 
2529 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2530 {
2531  uint32_t *vectors = (uint32_t *)SCB->VTOR;
2532  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2533 }
2534 
2535 
2540 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2541 {
2542  __DSB(); /* Ensure all outstanding memory accesses included
2543  buffered write are completed before reset */
2544  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2545  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2546  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2547  __DSB(); /* Ensure completion of memory access */
2548 
2549  for(;;) /* wait until reset */
2550  {
2551  __NOP();
2552  }
2553 }
2554 
2555 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2556 
2565 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2566 {
2567  uint32_t reg_value;
2568  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2569 
2570  reg_value = SCB_NS->AIRCR; /* read old register configuration */
2571  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2572  reg_value = (reg_value |
2573  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2574  (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2575  SCB_NS->AIRCR = reg_value;
2576 }
2577 
2578 
2584 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2585 {
2586  return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2587 }
2588 
2589 
2596 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2597 {
2598  if ((int32_t)(IRQn) >= 0)
2599  {
2600  NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2601  }
2602 }
2603 
2604 
2613 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2614 {
2615  if ((int32_t)(IRQn) >= 0)
2616  {
2617  return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2618  }
2619  else
2620  {
2621  return(0U);
2622  }
2623 }
2624 
2625 
2632 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2633 {
2634  if ((int32_t)(IRQn) >= 0)
2635  {
2636  NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2637  }
2638 }
2639 
2640 
2649 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2650 {
2651  if ((int32_t)(IRQn) >= 0)
2652  {
2653  return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2654  }
2655  else
2656  {
2657  return(0U);
2658  }
2659 }
2660 
2661 
2668 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2669 {
2670  if ((int32_t)(IRQn) >= 0)
2671  {
2672  NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2673  }
2674 }
2675 
2676 
2683 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2684 {
2685  if ((int32_t)(IRQn) >= 0)
2686  {
2687  NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2688  }
2689 }
2690 
2691 
2700 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2701 {
2702  if ((int32_t)(IRQn) >= 0)
2703  {
2704  return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2705  }
2706  else
2707  {
2708  return(0U);
2709  }
2710 }
2711 
2712 
2722 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2723 {
2724  if ((int32_t)(IRQn) >= 0)
2725  {
2726  NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2727  }
2728  else
2729  {
2730  SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2731  }
2732 }
2733 
2734 
2743 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2744 {
2745 
2746  if ((int32_t)(IRQn) >= 0)
2747  {
2748  return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2749  }
2750  else
2751  {
2752  return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2753  }
2754 }
2755 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2756 
2759 /* ########################## MPU functions #################################### */
2760 
2761 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2762 
2763 #include "mpu_armv8.h"
2764 
2765 #endif
2766 
2767 /* ########################## FPU functions #################################### */
2783 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2784 {
2785  uint32_t mvfr0;
2786 
2787  mvfr0 = FPU->MVFR0;
2788  if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2789  {
2790  return 2U; /* Double + Single precision FPU */
2791  }
2792  else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2793  {
2794  return 1U; /* Single precision FPU */
2795  }
2796  else
2797  {
2798  return 0U; /* No FPU */
2799  }
2800 }
2801 
2802 
2807 /* ########################## SAU functions #################################### */
2815 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2816 
2821 __STATIC_INLINE void TZ_SAU_Enable(void)
2822 {
2823  SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2824 }
2825 
2826 
2827 
2832 __STATIC_INLINE void TZ_SAU_Disable(void)
2833 {
2834  SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2835 }
2836 
2837 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2838 
2844 /* ################################## SysTick function ############################################ */
2852 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2853 
2865 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2866 {
2867  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2868  {
2869  return (1UL); /* Reload value impossible */
2870  }
2871 
2872  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2873  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2874  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2875  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2876  SysTick_CTRL_TICKINT_Msk |
2877  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2878  return (0UL); /* Function successful */
2879 }
2880 
2881 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2882 
2894 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
2895 {
2896  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2897  {
2898  return (1UL); /* Reload value impossible */
2899  }
2900 
2901  SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2902  TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2903  SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
2904  SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2905  SysTick_CTRL_TICKINT_Msk |
2906  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2907  return (0UL); /* Function successful */
2908 }
2909 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2910 
2911 #endif
2912 
2917 /* ##################################### Debug In/Output function ########################################### */
2925 extern volatile int32_t ITM_RxBuffer;
2926 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
2937 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2938 {
2939  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2940  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2941  {
2942  while (ITM->PORT[0U].u32 == 0UL)
2943  {
2944  __NOP();
2945  }
2946  ITM->PORT[0U].u8 = (uint8_t)ch;
2947  }
2948  return (ch);
2949 }
2950 
2951 
2958 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2959 {
2960  int32_t ch = -1; /* no character available */
2961 
2962  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2963  {
2964  ch = ITM_RxBuffer;
2965  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2966  }
2967 
2968  return (ch);
2969 }
2970 
2971 
2978 __STATIC_INLINE int32_t ITM_CheckChar (void)
2979 {
2980 
2981  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2982  {
2983  return (0); /* no character available */
2984  }
2985  else
2986  {
2987  return (1); /* character available */
2988  }
2989 }
2990 
2996 #ifdef __cplusplus
2997 }
2998 #endif
2999 
3000 #endif /* __CORE_CM33_H_DEPENDANT */
3001 
3002 #endif /* __CMSIS_GENERIC */
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv8mbl.h:1269
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv8mbl.h:1523
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv8mbl.h:1791
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_armv8mml.h:2903
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm33.h:612
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv8mbl.h:351
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm33.h:1047
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_armv8mbl.h:381
ITM
#define ITM
Definition: core_cm33.h:2061
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_armv8mbl.h:610
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv8mbl.h:1496
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_cm33.h:2926
SysTick_IRQn
Definition: stm32f103xb.h:80
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:877
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_armv8mbl.h:1358
__NOP
#define __NOP
No Operation.
Definition: cmsis_armcc.h:387
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv8mbl.h:1326
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv8mbl.h:1341
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm33.h:1050
SCB
#define SCB
Definition: core_cm33.h:2058
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_armv8mbl.h:558
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_armv8mbl.h:988
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_armv8mbl.h:233
cmsis_version.h
CMSIS Core(M) Version definitions.
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm33.h:613
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv8mbl.h:1252
FPU_MVFR0_Double_precision_Msk
#define FPU_MVFR0_Double_precision_Msk
Definition: core_cm33.h:1856
FPU
#define FPU
Definition: core_cm33.h:2077
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition: core_armv8mml.h:1685
SysTick
#define SysTick
Definition: core_cm33.h:2059
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm33.h:628
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv8mbl.h:1547
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_armv8mbl.h:320
__NVIC_SetPriorityGrouping
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_armv8mml.h:2116
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_armv8mbl.h:725
NVIC
#define NVIC
Definition: core_cm33.h:2060
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm33.h:1057
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_armv8mml.h:1009
IRQn_Type
IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f103xb.h:69
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv8mbl.h:263
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_armv8mml.h:2883
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:866
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv8mbl.h:281
FPU_MVFR0_Single_precision_Msk
#define FPU_MVFR0_Single_precision_Msk
Definition: core_cm33.h:1859
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv8mbl.h:1288
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm33.h:1053
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv8mbl.h:1566
cmsis_compiler.h
CMSIS compiler generic header file.
__NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_armv8mml.h:2135
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: stm32f103xb.h:52
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_cm33.h:1164
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm33.h:634
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_armv8mml.h:1086
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv8mbl.h:1581
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv8mbl.h:1447
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv8mbl.h:1307
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv8mbl.h:1471
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm33.h:627
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