DWT_Type Struct Reference

Structure type to access the Data Watchpoint and Trace Register (DWT). More...

#include <core_armv8mbl.h>

Public Attributes
__IOM uint32_t	CTRL
uint32_t	RESERVED0 [6U]
__IM uint32_t	PCSR
__IOM uint32_t	COMP0
uint32_t	RESERVED1 [1U]
__IOM uint32_t	FUNCTION0
uint32_t	RESERVED2 [1U]
__IOM uint32_t	COMP1
uint32_t	RESERVED3 [1U]
__IOM uint32_t	FUNCTION1
uint32_t	RESERVED4 [1U]
__IOM uint32_t	COMP2
uint32_t	RESERVED5 [1U]
__IOM uint32_t	FUNCTION2
uint32_t	RESERVED6 [1U]
__IOM uint32_t	COMP3
uint32_t	RESERVED7 [1U]
__IOM uint32_t	FUNCTION3
uint32_t	RESERVED8 [1U]
__IOM uint32_t	COMP4
uint32_t	RESERVED9 [1U]
__IOM uint32_t	FUNCTION4
uint32_t	RESERVED10 [1U]
__IOM uint32_t	COMP5
uint32_t	RESERVED11 [1U]
__IOM uint32_t	FUNCTION5
uint32_t	RESERVED12 [1U]
__IOM uint32_t	COMP6
uint32_t	RESERVED13 [1U]
__IOM uint32_t	FUNCTION6
uint32_t	RESERVED14 [1U]
__IOM uint32_t	COMP7
uint32_t	RESERVED15 [1U]
__IOM uint32_t	FUNCTION7
uint32_t	RESERVED16 [1U]
__IOM uint32_t	COMP8
uint32_t	RESERVED17 [1U]
__IOM uint32_t	FUNCTION8
uint32_t	RESERVED18 [1U]
__IOM uint32_t	COMP9
uint32_t	RESERVED19 [1U]
__IOM uint32_t	FUNCTION9
uint32_t	RESERVED20 [1U]
__IOM uint32_t	COMP10
uint32_t	RESERVED21 [1U]
__IOM uint32_t	FUNCTION10
uint32_t	RESERVED22 [1U]
__IOM uint32_t	COMP11
uint32_t	RESERVED23 [1U]
__IOM uint32_t	FUNCTION11
uint32_t	RESERVED24 [1U]
__IOM uint32_t	COMP12
uint32_t	RESERVED25 [1U]
__IOM uint32_t	FUNCTION12
uint32_t	RESERVED26 [1U]
__IOM uint32_t	COMP13
uint32_t	RESERVED27 [1U]
__IOM uint32_t	FUNCTION13
uint32_t	RESERVED28 [1U]
__IOM uint32_t	COMP14
uint32_t	RESERVED29 [1U]
__IOM uint32_t	FUNCTION14
uint32_t	RESERVED30 [1U]
__IOM uint32_t	COMP15
uint32_t	RESERVED31 [1U]
__IOM uint32_t	FUNCTION15
__IOM uint32_t	CYCCNT
__IOM uint32_t	CPICNT
__IOM uint32_t	EXCCNT
__IOM uint32_t	SLEEPCNT
__IOM uint32_t	LSUCNT
__IOM uint32_t	FOLDCNT
uint32_t	RESERVED32 [934U]
__IM uint32_t	LSR
uint32_t	RESERVED33 [1U]
__IM uint32_t	DEVARCH
__IOM uint32_t	MASK0
__IOM uint32_t	MASK1
__IOM uint32_t	MASK2
__IOM uint32_t	MASK3
__OM uint32_t	LAR

Detailed Description

Structure type to access the Data Watchpoint and Trace Register (DWT).

Member Data Documentation

COMP0

__IOM uint32_t DWT_Type::COMP0

Offset: 0x020 (R/W) Comparator Register 0

COMP1

__IOM uint32_t DWT_Type::COMP1

Offset: 0x030 (R/W) Comparator Register 1

COMP10

__IOM uint32_t DWT_Type::COMP10

Offset: 0x0C0 (R/W) Comparator Register 10

COMP11

__IOM uint32_t DWT_Type::COMP11

Offset: 0x0D0 (R/W) Comparator Register 11

COMP12

__IOM uint32_t DWT_Type::COMP12

Offset: 0x0E0 (R/W) Comparator Register 12

COMP13

__IOM uint32_t DWT_Type::COMP13

Offset: 0x0F0 (R/W) Comparator Register 13

COMP14

__IOM uint32_t DWT_Type::COMP14

Offset: 0x100 (R/W) Comparator Register 14

COMP15

__IOM uint32_t DWT_Type::COMP15

Offset: 0x110 (R/W) Comparator Register 15

COMP2

__IOM uint32_t DWT_Type::COMP2

Offset: 0x040 (R/W) Comparator Register 2

COMP3

__IOM uint32_t DWT_Type::COMP3

Offset: 0x050 (R/W) Comparator Register 3

COMP4

__IOM uint32_t DWT_Type::COMP4

Offset: 0x060 (R/W) Comparator Register 4

COMP5

__IOM uint32_t DWT_Type::COMP5

Offset: 0x070 (R/W) Comparator Register 5

COMP6

__IOM uint32_t DWT_Type::COMP6

Offset: 0x080 (R/W) Comparator Register 6

COMP7

__IOM uint32_t DWT_Type::COMP7

Offset: 0x090 (R/W) Comparator Register 7

COMP8

__IOM uint32_t DWT_Type::COMP8

Offset: 0x0A0 (R/W) Comparator Register 8

COMP9

__IOM uint32_t DWT_Type::COMP9

Offset: 0x0B0 (R/W) Comparator Register 9

CPICNT

__IOM uint32_t DWT_Type::CPICNT

Offset: 0x008 (R/W) CPI Count Register

CTRL

__IOM uint32_t DWT_Type::CTRL

Offset: 0x000 (R/W) Control Register

CYCCNT

__IOM uint32_t DWT_Type::CYCCNT

Offset: 0x004 (R/W) Cycle Count Register

DEVARCH

__IM uint32_t DWT_Type::DEVARCH

Offset: 0xFBC (R/ ) Device Architecture Register

EXCCNT

__IOM uint32_t DWT_Type::EXCCNT

Offset: 0x00C (R/W) Exception Overhead Count Register

FOLDCNT

__IOM uint32_t DWT_Type::FOLDCNT

Offset: 0x018 (R/W) Folded-instruction Count Register

FUNCTION0

__IOM uint32_t DWT_Type::FUNCTION0

Offset: 0x028 (R/W) Function Register 0

FUNCTION1

__IOM uint32_t DWT_Type::FUNCTION1

Offset: 0x038 (R/W) Function Register 1

FUNCTION10

__IOM uint32_t DWT_Type::FUNCTION10

Offset: 0x0C8 (R/W) Function Register 10

FUNCTION11

__IOM uint32_t DWT_Type::FUNCTION11

Offset: 0x0D8 (R/W) Function Register 11

FUNCTION12

__IOM uint32_t DWT_Type::FUNCTION12

Offset: 0x0E8 (R/W) Function Register 12

FUNCTION13

__IOM uint32_t DWT_Type::FUNCTION13

Offset: 0x0F8 (R/W) Function Register 13

FUNCTION14

__IOM uint32_t DWT_Type::FUNCTION14

Offset: 0x108 (R/W) Function Register 14

FUNCTION15

__IOM uint32_t DWT_Type::FUNCTION15

Offset: 0x118 (R/W) Function Register 15

FUNCTION2

__IOM uint32_t DWT_Type::FUNCTION2

Offset: 0x048 (R/W) Function Register 2

FUNCTION3

__IOM uint32_t DWT_Type::FUNCTION3

Offset: 0x058 (R/W) Function Register 3

FUNCTION4

__IOM uint32_t DWT_Type::FUNCTION4

Offset: 0x068 (R/W) Function Register 4

FUNCTION5

__IOM uint32_t DWT_Type::FUNCTION5

Offset: 0x078 (R/W) Function Register 5

FUNCTION6

__IOM uint32_t DWT_Type::FUNCTION6

Offset: 0x088 (R/W) Function Register 6

FUNCTION7

__IOM uint32_t DWT_Type::FUNCTION7

Offset: 0x098 (R/W) Function Register 7

FUNCTION8

__IOM uint32_t DWT_Type::FUNCTION8

Offset: 0x0A8 (R/W) Function Register 8

FUNCTION9

__IOM uint32_t DWT_Type::FUNCTION9

Offset: 0x0B8 (R/W) Function Register 9

LAR

__OM uint32_t DWT_Type::LAR

Offset: 0xFB0 ( W) Lock Access Register

LSR

__IM uint32_t DWT_Type::LSR

Offset: 0xFB4 (R ) Lock Status Register

LSUCNT

__IOM uint32_t DWT_Type::LSUCNT

Offset: 0x014 (R/W) LSU Count Register

MASK0

__IOM uint32_t DWT_Type::MASK0

Offset: 0x024 (R/W) Mask Register 0

MASK1

__IOM uint32_t DWT_Type::MASK1

Offset: 0x034 (R/W) Mask Register 1

MASK2

__IOM uint32_t DWT_Type::MASK2

Offset: 0x044 (R/W) Mask Register 2

MASK3

__IOM uint32_t DWT_Type::MASK3

Offset: 0x054 (R/W) Mask Register 3

PCSR

__IM uint32_t DWT_Type::PCSR

Offset: 0x01C (R/ ) Program Counter Sample Register

SLEEPCNT

__IOM uint32_t DWT_Type::SLEEPCNT

Offset: 0x010 (R/W) Sleep Count Register

---

The documentation for this struct was generated from the following files:

• test/STM32TestProject/Drivers/CMSIS/Include/core_armv8mbl.h
• test/STM32TestProject/Drivers/CMSIS/Include/core_armv8mml.h
• test/STM32TestProject/Drivers/CMSIS/Include/core_cm23.h
• test/STM32TestProject/Drivers/CMSIS/Include/core_cm3.h
• test/STM32TestProject/Drivers/CMSIS/Include/core_cm33.h
• test/STM32TestProject/Drivers/CMSIS/Include/core_cm4.h
• test/STM32TestProject/Drivers/CMSIS/Include/core_cm7.h
• test/STM32TestProject/Drivers/CMSIS/Include/core_sc300.h