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core_cm4.h
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1 /**************************************************************************/
7 /*
8  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #endif
30 
31 #ifndef __CORE_CM4_H_GENERIC
32 #define __CORE_CM4_H_GENERIC
33 
34 #include <stdint.h>
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif
39 
55 /*******************************************************************************
56  * CMSIS definitions
57  ******************************************************************************/
63 #include "cmsis_version.h"
64 
65 /* CMSIS CM4 definitions */
66 #define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN)
67 #define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB)
68 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
69  __CM4_CMSIS_VERSION_SUB )
71 #define __CORTEX_M (4U)
76 #if defined ( __CC_ARM )
77  #if defined __TARGET_FPU_VFP
78  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
79  #define __FPU_USED 1U
80  #else
81  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
82  #define __FPU_USED 0U
83  #endif
84  #else
85  #define __FPU_USED 0U
86  #endif
87 
88 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
89  #if defined __ARM_PCS_VFP
90  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
91  #define __FPU_USED 1U
92  #else
93  #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
94  #define __FPU_USED 0U
95  #endif
96  #else
97  #define __FPU_USED 0U
98  #endif
99 
100 #elif defined ( __GNUC__ )
101  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
102  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
103  #define __FPU_USED 1U
104  #else
105  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106  #define __FPU_USED 0U
107  #endif
108  #else
109  #define __FPU_USED 0U
110  #endif
111 
112 #elif defined ( __ICCARM__ )
113  #if defined __ARMVFP__
114  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
115  #define __FPU_USED 1U
116  #else
117  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118  #define __FPU_USED 0U
119  #endif
120  #else
121  #define __FPU_USED 0U
122  #endif
123 
124 #elif defined ( __TI_ARM__ )
125  #if defined __TI_VFP_SUPPORT__
126  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
127  #define __FPU_USED 1U
128  #else
129  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130  #define __FPU_USED 0U
131  #endif
132  #else
133  #define __FPU_USED 0U
134  #endif
135 
136 #elif defined ( __TASKING__ )
137  #if defined __FPU_VFP__
138  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
139  #define __FPU_USED 1U
140  #else
141  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
142  #define __FPU_USED 0U
143  #endif
144  #else
145  #define __FPU_USED 0U
146  #endif
147 
148 #elif defined ( __CSMC__ )
149  #if ( __CSMC__ & 0x400U)
150  #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
151  #define __FPU_USED 1U
152  #else
153  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154  #define __FPU_USED 0U
155  #endif
156  #else
157  #define __FPU_USED 0U
158  #endif
159 
160 #endif
161 
162 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
163 
164 
165 #ifdef __cplusplus
166 }
167 #endif
168 
169 #endif /* __CORE_CM4_H_GENERIC */
170 
171 #ifndef __CMSIS_GENERIC
172 
173 #ifndef __CORE_CM4_H_DEPENDANT
174 #define __CORE_CM4_H_DEPENDANT
175 
176 #ifdef __cplusplus
177  extern "C" {
178 #endif
179 
180 /* check device defines and use defaults */
181 #if defined __CHECK_DEVICE_DEFINES
182  #ifndef __CM4_REV
183  #define __CM4_REV 0x0000U
184  #warning "__CM4_REV not defined in device header file; using default!"
185  #endif
186 
187  #ifndef __FPU_PRESENT
188  #define __FPU_PRESENT 0U
189  #warning "__FPU_PRESENT not defined in device header file; using default!"
190  #endif
191 
192  #ifndef __MPU_PRESENT
193  #define __MPU_PRESENT 0U
194  #warning "__MPU_PRESENT not defined in device header file; using default!"
195  #endif
196 
197  #ifndef __NVIC_PRIO_BITS
198  #define __NVIC_PRIO_BITS 3U
199  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
200  #endif
201 
202  #ifndef __Vendor_SysTickConfig
203  #define __Vendor_SysTickConfig 0U
204  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
205  #endif
206 #endif
207 
208 /* IO definitions (access restrictions to peripheral registers) */
216 #ifdef __cplusplus
217  #define __I volatile
218 #else
219  #define __I volatile const
220 #endif
221 #define __O volatile
222 #define __IO volatile
224 /* following defines should be used for structure members */
225 #define __IM volatile const
226 #define __OM volatile
227 #define __IOM volatile
229 
233 /*******************************************************************************
234  * Register Abstraction
235  Core Register contain:
236  - Core Register
237  - Core NVIC Register
238  - Core SCB Register
239  - Core SysTick Register
240  - Core Debug Register
241  - Core MPU Register
242  - Core FPU Register
243  ******************************************************************************/
244 
259 typedef union
260 {
261  struct
262  {
263  uint32_t _reserved0:16;
264  uint32_t GE:4;
265  uint32_t _reserved1:7;
266  uint32_t Q:1;
267  uint32_t V:1;
268  uint32_t C:1;
269  uint32_t Z:1;
270  uint32_t N:1;
271  } b;
272  uint32_t w;
273 } APSR_Type;
274 
275 /* APSR Register Definitions */
276 #define APSR_N_Pos 31U
277 #define APSR_N_Msk (1UL << APSR_N_Pos)
279 #define APSR_Z_Pos 30U
280 #define APSR_Z_Msk (1UL << APSR_Z_Pos)
282 #define APSR_C_Pos 29U
283 #define APSR_C_Msk (1UL << APSR_C_Pos)
285 #define APSR_V_Pos 28U
286 #define APSR_V_Msk (1UL << APSR_V_Pos)
288 #define APSR_Q_Pos 27U
289 #define APSR_Q_Msk (1UL << APSR_Q_Pos)
291 #define APSR_GE_Pos 16U
292 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos)
298 typedef union
299 {
300  struct
301  {
302  uint32_t ISR:9;
303  uint32_t _reserved0:23;
304  } b;
305  uint32_t w;
306 } IPSR_Type;
307 
308 /* IPSR Register Definitions */
309 #define IPSR_ISR_Pos 0U
310 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/)
316 typedef union
317 {
318  struct
319  {
320  uint32_t ISR:9;
321  uint32_t _reserved0:1;
322  uint32_t ICI_IT_1:6;
323  uint32_t GE:4;
324  uint32_t _reserved1:4;
325  uint32_t T:1;
326  uint32_t ICI_IT_2:2;
327  uint32_t Q:1;
328  uint32_t V:1;
329  uint32_t C:1;
330  uint32_t Z:1;
331  uint32_t N:1;
332  } b;
333  uint32_t w;
334 } xPSR_Type;
335 
336 /* xPSR Register Definitions */
337 #define xPSR_N_Pos 31U
338 #define xPSR_N_Msk (1UL << xPSR_N_Pos)
340 #define xPSR_Z_Pos 30U
341 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos)
343 #define xPSR_C_Pos 29U
344 #define xPSR_C_Msk (1UL << xPSR_C_Pos)
346 #define xPSR_V_Pos 28U
347 #define xPSR_V_Msk (1UL << xPSR_V_Pos)
349 #define xPSR_Q_Pos 27U
350 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos)
352 #define xPSR_ICI_IT_2_Pos 25U
353 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos)
355 #define xPSR_T_Pos 24U
356 #define xPSR_T_Msk (1UL << xPSR_T_Pos)
358 #define xPSR_GE_Pos 16U
359 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos)
361 #define xPSR_ICI_IT_1_Pos 10U
362 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos)
364 #define xPSR_ISR_Pos 0U
365 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/)
371 typedef union
372 {
373  struct
374  {
375  uint32_t nPRIV:1;
376  uint32_t SPSEL:1;
377  uint32_t FPCA:1;
378  uint32_t _reserved0:29;
379  } b;
380  uint32_t w;
381 } CONTROL_Type;
382 
383 /* CONTROL Register Definitions */
384 #define CONTROL_FPCA_Pos 2U
385 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos)
387 #define CONTROL_SPSEL_Pos 1U
388 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos)
390 #define CONTROL_nPRIV_Pos 0U
391 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/)
393 
406 typedef struct
407 {
408  __IOM uint32_t ISER[8U];
409  uint32_t RESERVED0[24U];
410  __IOM uint32_t ICER[8U];
411  uint32_t RSERVED1[24U];
412  __IOM uint32_t ISPR[8U];
413  uint32_t RESERVED2[24U];
414  __IOM uint32_t ICPR[8U];
415  uint32_t RESERVED3[24U];
416  __IOM uint32_t IABR[8U];
417  uint32_t RESERVED4[56U];
418  __IOM uint8_t IP[240U];
419  uint32_t RESERVED5[644U];
420  __OM uint32_t STIR;
421 } NVIC_Type;
422 
423 /* Software Triggered Interrupt Register Definitions */
424 #define NVIC_STIR_INTID_Pos 0U
425 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)
427 
440 typedef struct
441 {
442  __IM uint32_t CPUID;
443  __IOM uint32_t ICSR;
444  __IOM uint32_t VTOR;
445  __IOM uint32_t AIRCR;
446  __IOM uint32_t SCR;
447  __IOM uint32_t CCR;
448  __IOM uint8_t SHP[12U];
449  __IOM uint32_t SHCSR;
450  __IOM uint32_t CFSR;
451  __IOM uint32_t HFSR;
452  __IOM uint32_t DFSR;
453  __IOM uint32_t MMFAR;
454  __IOM uint32_t BFAR;
455  __IOM uint32_t AFSR;
456  __IM uint32_t PFR[2U];
457  __IM uint32_t DFR;
458  __IM uint32_t ADR;
459  __IM uint32_t MMFR[4U];
460  __IM uint32_t ISAR[5U];
461  uint32_t RESERVED0[5U];
462  __IOM uint32_t CPACR;
463 } SCB_Type;
464 
465 /* SCB CPUID Register Definitions */
466 #define SCB_CPUID_IMPLEMENTER_Pos 24U
467 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
469 #define SCB_CPUID_VARIANT_Pos 20U
470 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos)
472 #define SCB_CPUID_ARCHITECTURE_Pos 16U
473 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
475 #define SCB_CPUID_PARTNO_Pos 4U
476 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos)
478 #define SCB_CPUID_REVISION_Pos 0U
479 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)
481 /* SCB Interrupt Control State Register Definitions */
482 #define SCB_ICSR_NMIPENDSET_Pos 31U
483 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos)
485 #define SCB_ICSR_PENDSVSET_Pos 28U
486 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos)
488 #define SCB_ICSR_PENDSVCLR_Pos 27U
489 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos)
491 #define SCB_ICSR_PENDSTSET_Pos 26U
492 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos)
494 #define SCB_ICSR_PENDSTCLR_Pos 25U
495 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos)
497 #define SCB_ICSR_ISRPREEMPT_Pos 23U
498 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos)
500 #define SCB_ICSR_ISRPENDING_Pos 22U
501 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos)
503 #define SCB_ICSR_VECTPENDING_Pos 12U
504 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
506 #define SCB_ICSR_RETTOBASE_Pos 11U
507 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos)
509 #define SCB_ICSR_VECTACTIVE_Pos 0U
510 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)
512 /* SCB Vector Table Offset Register Definitions */
513 #define SCB_VTOR_TBLOFF_Pos 7U
514 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
516 /* SCB Application Interrupt and Reset Control Register Definitions */
517 #define SCB_AIRCR_VECTKEY_Pos 16U
518 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
520 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U
521 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
523 #define SCB_AIRCR_ENDIANESS_Pos 15U
524 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos)
526 #define SCB_AIRCR_PRIGROUP_Pos 8U
527 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos)
529 #define SCB_AIRCR_SYSRESETREQ_Pos 2U
530 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
532 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U
533 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
535 #define SCB_AIRCR_VECTRESET_Pos 0U
536 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)
538 /* SCB System Control Register Definitions */
539 #define SCB_SCR_SEVONPEND_Pos 4U
540 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos)
542 #define SCB_SCR_SLEEPDEEP_Pos 2U
543 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos)
545 #define SCB_SCR_SLEEPONEXIT_Pos 1U
546 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos)
548 /* SCB Configuration Control Register Definitions */
549 #define SCB_CCR_STKALIGN_Pos 9U
550 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos)
552 #define SCB_CCR_BFHFNMIGN_Pos 8U
553 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos)
555 #define SCB_CCR_DIV_0_TRP_Pos 4U
556 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos)
558 #define SCB_CCR_UNALIGN_TRP_Pos 3U
559 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos)
561 #define SCB_CCR_USERSETMPEND_Pos 1U
562 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos)
564 #define SCB_CCR_NONBASETHRDENA_Pos 0U
565 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)
567 /* SCB System Handler Control and State Register Definitions */
568 #define SCB_SHCSR_USGFAULTENA_Pos 18U
569 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos)
571 #define SCB_SHCSR_BUSFAULTENA_Pos 17U
572 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
574 #define SCB_SHCSR_MEMFAULTENA_Pos 16U
575 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
577 #define SCB_SHCSR_SVCALLPENDED_Pos 15U
578 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
580 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U
581 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
583 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U
584 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
586 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U
587 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
589 #define SCB_SHCSR_SYSTICKACT_Pos 11U
590 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos)
592 #define SCB_SHCSR_PENDSVACT_Pos 10U
593 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos)
595 #define SCB_SHCSR_MONITORACT_Pos 8U
596 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos)
598 #define SCB_SHCSR_SVCALLACT_Pos 7U
599 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos)
601 #define SCB_SHCSR_USGFAULTACT_Pos 3U
602 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos)
604 #define SCB_SHCSR_BUSFAULTACT_Pos 1U
605 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
607 #define SCB_SHCSR_MEMFAULTACT_Pos 0U
608 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)
610 /* SCB Configurable Fault Status Register Definitions */
611 #define SCB_CFSR_USGFAULTSR_Pos 16U
612 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
614 #define SCB_CFSR_BUSFAULTSR_Pos 8U
615 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
617 #define SCB_CFSR_MEMFAULTSR_Pos 0U
618 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)
620 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
621 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
622 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos)
624 #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U)
625 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos)
627 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
628 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos)
630 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
631 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos)
633 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
634 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos)
636 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
637 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
639 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
640 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U)
641 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos)
643 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U)
644 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos)
646 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U)
647 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos)
649 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U)
650 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos)
652 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U)
653 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos)
655 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U)
656 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos)
658 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U)
659 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos)
661 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
662 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U)
663 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos)
665 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U)
666 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos)
668 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U)
669 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos)
671 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U)
672 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos)
674 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U)
675 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos)
677 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U)
678 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos)
680 /* SCB Hard Fault Status Register Definitions */
681 #define SCB_HFSR_DEBUGEVT_Pos 31U
682 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos)
684 #define SCB_HFSR_FORCED_Pos 30U
685 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos)
687 #define SCB_HFSR_VECTTBL_Pos 1U
688 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos)
690 /* SCB Debug Fault Status Register Definitions */
691 #define SCB_DFSR_EXTERNAL_Pos 4U
692 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos)
694 #define SCB_DFSR_VCATCH_Pos 3U
695 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos)
697 #define SCB_DFSR_DWTTRAP_Pos 2U
698 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos)
700 #define SCB_DFSR_BKPT_Pos 1U
701 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos)
703 #define SCB_DFSR_HALTED_Pos 0U
704 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/)
706 
719 typedef struct
720 {
721  uint32_t RESERVED0[1U];
722  __IM uint32_t ICTR;
723  __IOM uint32_t ACTLR;
724 } SCnSCB_Type;
725 
726 /* Interrupt Controller Type Register Definitions */
727 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U
728 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)
730 /* Auxiliary Control Register Definitions */
731 #define SCnSCB_ACTLR_DISOOFP_Pos 9U
732 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos)
734 #define SCnSCB_ACTLR_DISFPCA_Pos 8U
735 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos)
737 #define SCnSCB_ACTLR_DISFOLD_Pos 2U
738 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
740 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U
741 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
743 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U
744 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)
746 
759 typedef struct
760 {
761  __IOM uint32_t CTRL;
762  __IOM uint32_t LOAD;
763  __IOM uint32_t VAL;
764  __IM uint32_t CALIB;
765 } SysTick_Type;
766 
767 /* SysTick Control / Status Register Definitions */
768 #define SysTick_CTRL_COUNTFLAG_Pos 16U
769 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos)
771 #define SysTick_CTRL_CLKSOURCE_Pos 2U
772 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos)
774 #define SysTick_CTRL_TICKINT_Pos 1U
775 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos)
777 #define SysTick_CTRL_ENABLE_Pos 0U
778 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)
780 /* SysTick Reload Register Definitions */
781 #define SysTick_LOAD_RELOAD_Pos 0U
782 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)
784 /* SysTick Current Register Definitions */
785 #define SysTick_VAL_CURRENT_Pos 0U
786 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)
788 /* SysTick Calibration Register Definitions */
789 #define SysTick_CALIB_NOREF_Pos 31U
790 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos)
792 #define SysTick_CALIB_SKEW_Pos 30U
793 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos)
795 #define SysTick_CALIB_TENMS_Pos 0U
796 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)
798 
811 typedef struct
812 {
813  __OM union
814  {
815  __OM uint8_t u8;
816  __OM uint16_t u16;
817  __OM uint32_t u32;
818  } PORT [32U];
819  uint32_t RESERVED0[864U];
820  __IOM uint32_t TER;
821  uint32_t RESERVED1[15U];
822  __IOM uint32_t TPR;
823  uint32_t RESERVED2[15U];
824  __IOM uint32_t TCR;
825  uint32_t RESERVED3[29U];
826  __OM uint32_t IWR;
827  __IM uint32_t IRR;
828  __IOM uint32_t IMCR;
829  uint32_t RESERVED4[43U];
830  __OM uint32_t LAR;
831  __IM uint32_t LSR;
832  uint32_t RESERVED5[6U];
833  __IM uint32_t PID4;
834  __IM uint32_t PID5;
835  __IM uint32_t PID6;
836  __IM uint32_t PID7;
837  __IM uint32_t PID0;
838  __IM uint32_t PID1;
839  __IM uint32_t PID2;
840  __IM uint32_t PID3;
841  __IM uint32_t CID0;
842  __IM uint32_t CID1;
843  __IM uint32_t CID2;
844  __IM uint32_t CID3;
845 } ITM_Type;
846 
847 /* ITM Trace Privilege Register Definitions */
848 #define ITM_TPR_PRIVMASK_Pos 0U
849 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/)
851 /* ITM Trace Control Register Definitions */
852 #define ITM_TCR_BUSY_Pos 23U
853 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos)
855 #define ITM_TCR_TraceBusID_Pos 16U
856 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos)
858 #define ITM_TCR_GTSFREQ_Pos 10U
859 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos)
861 #define ITM_TCR_TSPrescale_Pos 8U
862 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos)
864 #define ITM_TCR_SWOENA_Pos 4U
865 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos)
867 #define ITM_TCR_DWTENA_Pos 3U
868 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos)
870 #define ITM_TCR_SYNCENA_Pos 2U
871 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos)
873 #define ITM_TCR_TSENA_Pos 1U
874 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos)
876 #define ITM_TCR_ITMENA_Pos 0U
877 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/)
879 /* ITM Integration Write Register Definitions */
880 #define ITM_IWR_ATVALIDM_Pos 0U
881 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)
883 /* ITM Integration Read Register Definitions */
884 #define ITM_IRR_ATREADYM_Pos 0U
885 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/)
887 /* ITM Integration Mode Control Register Definitions */
888 #define ITM_IMCR_INTEGRATION_Pos 0U
889 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)
891 /* ITM Lock Status Register Definitions */
892 #define ITM_LSR_ByteAcc_Pos 2U
893 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos)
895 #define ITM_LSR_Access_Pos 1U
896 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos)
898 #define ITM_LSR_Present_Pos 0U
899 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/)
901  /* end of group CMSIS_ITM */
902 
903 
914 typedef struct
915 {
916  __IOM uint32_t CTRL;
917  __IOM uint32_t CYCCNT;
918  __IOM uint32_t CPICNT;
919  __IOM uint32_t EXCCNT;
920  __IOM uint32_t SLEEPCNT;
921  __IOM uint32_t LSUCNT;
922  __IOM uint32_t FOLDCNT;
923  __IM uint32_t PCSR;
924  __IOM uint32_t COMP0;
925  __IOM uint32_t MASK0;
926  __IOM uint32_t FUNCTION0;
927  uint32_t RESERVED0[1U];
928  __IOM uint32_t COMP1;
929  __IOM uint32_t MASK1;
930  __IOM uint32_t FUNCTION1;
931  uint32_t RESERVED1[1U];
932  __IOM uint32_t COMP2;
933  __IOM uint32_t MASK2;
934  __IOM uint32_t FUNCTION2;
935  uint32_t RESERVED2[1U];
936  __IOM uint32_t COMP3;
937  __IOM uint32_t MASK3;
938  __IOM uint32_t FUNCTION3;
939 } DWT_Type;
940 
941 /* DWT Control Register Definitions */
942 #define DWT_CTRL_NUMCOMP_Pos 28U
943 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos)
945 #define DWT_CTRL_NOTRCPKT_Pos 27U
946 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos)
948 #define DWT_CTRL_NOEXTTRIG_Pos 26U
949 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)
951 #define DWT_CTRL_NOCYCCNT_Pos 25U
952 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos)
954 #define DWT_CTRL_NOPRFCNT_Pos 24U
955 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos)
957 #define DWT_CTRL_CYCEVTENA_Pos 22U
958 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos)
960 #define DWT_CTRL_FOLDEVTENA_Pos 21U
961 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)
963 #define DWT_CTRL_LSUEVTENA_Pos 20U
964 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos)
966 #define DWT_CTRL_SLEEPEVTENA_Pos 19U
967 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)
969 #define DWT_CTRL_EXCEVTENA_Pos 18U
970 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos)
972 #define DWT_CTRL_CPIEVTENA_Pos 17U
973 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos)
975 #define DWT_CTRL_EXCTRCENA_Pos 16U
976 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos)
978 #define DWT_CTRL_PCSAMPLENA_Pos 12U
979 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)
981 #define DWT_CTRL_SYNCTAP_Pos 10U
982 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos)
984 #define DWT_CTRL_CYCTAP_Pos 9U
985 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos)
987 #define DWT_CTRL_POSTINIT_Pos 5U
988 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos)
990 #define DWT_CTRL_POSTPRESET_Pos 1U
991 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos)
993 #define DWT_CTRL_CYCCNTENA_Pos 0U
994 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)
996 /* DWT CPI Count Register Definitions */
997 #define DWT_CPICNT_CPICNT_Pos 0U
998 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)
1000 /* DWT Exception Overhead Count Register Definitions */
1001 #define DWT_EXCCNT_EXCCNT_Pos 0U
1002 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)
1004 /* DWT Sleep Count Register Definitions */
1005 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U
1006 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)
1008 /* DWT LSU Count Register Definitions */
1009 #define DWT_LSUCNT_LSUCNT_Pos 0U
1010 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)
1012 /* DWT Folded-instruction Count Register Definitions */
1013 #define DWT_FOLDCNT_FOLDCNT_Pos 0U
1014 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)
1016 /* DWT Comparator Mask Register Definitions */
1017 #define DWT_MASK_MASK_Pos 0U
1018 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/)
1020 /* DWT Comparator Function Register Definitions */
1021 #define DWT_FUNCTION_MATCHED_Pos 24U
1022 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos)
1024 #define DWT_FUNCTION_DATAVADDR1_Pos 16U
1025 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)
1027 #define DWT_FUNCTION_DATAVADDR0_Pos 12U
1028 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)
1030 #define DWT_FUNCTION_DATAVSIZE_Pos 10U
1031 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)
1033 #define DWT_FUNCTION_LNK1ENA_Pos 9U
1034 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)
1036 #define DWT_FUNCTION_DATAVMATCH_Pos 8U
1037 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)
1039 #define DWT_FUNCTION_CYCMATCH_Pos 7U
1040 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)
1042 #define DWT_FUNCTION_EMITRANGE_Pos 5U
1043 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)
1045 #define DWT_FUNCTION_FUNCTION_Pos 0U
1046 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)
1048  /* end of group CMSIS_DWT */
1049 
1050 
1061 typedef struct
1062 {
1063  __IM uint32_t SSPSR;
1064  __IOM uint32_t CSPSR;
1065  uint32_t RESERVED0[2U];
1066  __IOM uint32_t ACPR;
1067  uint32_t RESERVED1[55U];
1068  __IOM uint32_t SPPR;
1069  uint32_t RESERVED2[131U];
1070  __IM uint32_t FFSR;
1071  __IOM uint32_t FFCR;
1072  __IM uint32_t FSCR;
1073  uint32_t RESERVED3[759U];
1074  __IM uint32_t TRIGGER;
1075  __IM uint32_t FIFO0;
1076  __IM uint32_t ITATBCTR2;
1077  uint32_t RESERVED4[1U];
1078  __IM uint32_t ITATBCTR0;
1079  __IM uint32_t FIFO1;
1080  __IOM uint32_t ITCTRL;
1081  uint32_t RESERVED5[39U];
1082  __IOM uint32_t CLAIMSET;
1083  __IOM uint32_t CLAIMCLR;
1084  uint32_t RESERVED7[8U];
1085  __IM uint32_t DEVID;
1086  __IM uint32_t DEVTYPE;
1087 } TPI_Type;
1088 
1089 /* TPI Asynchronous Clock Prescaler Register Definitions */
1090 #define TPI_ACPR_PRESCALER_Pos 0U
1091 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)
1093 /* TPI Selected Pin Protocol Register Definitions */
1094 #define TPI_SPPR_TXMODE_Pos 0U
1095 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)
1097 /* TPI Formatter and Flush Status Register Definitions */
1098 #define TPI_FFSR_FtNonStop_Pos 3U
1099 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)
1101 #define TPI_FFSR_TCPresent_Pos 2U
1102 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)
1104 #define TPI_FFSR_FtStopped_Pos 1U
1105 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)
1107 #define TPI_FFSR_FlInProg_Pos 0U
1108 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)
1110 /* TPI Formatter and Flush Control Register Definitions */
1111 #define TPI_FFCR_TrigIn_Pos 8U
1112 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)
1114 #define TPI_FFCR_EnFCont_Pos 1U
1115 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)
1117 /* TPI TRIGGER Register Definitions */
1118 #define TPI_TRIGGER_TRIGGER_Pos 0U
1119 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)
1121 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1122 #define TPI_FIFO0_ITM_ATVALID_Pos 29U
1123 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)
1125 #define TPI_FIFO0_ITM_bytecount_Pos 27U
1126 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)
1128 #define TPI_FIFO0_ETM_ATVALID_Pos 26U
1129 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)
1131 #define TPI_FIFO0_ETM_bytecount_Pos 24U
1132 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)
1134 #define TPI_FIFO0_ETM2_Pos 16U
1135 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)
1137 #define TPI_FIFO0_ETM1_Pos 8U
1138 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)
1140 #define TPI_FIFO0_ETM0_Pos 0U
1141 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)
1143 /* TPI ITATBCTR2 Register Definitions */
1144 #define TPI_ITATBCTR2_ATREADY2_Pos 0U
1145 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/)
1147 #define TPI_ITATBCTR2_ATREADY1_Pos 0U
1148 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/)
1150 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1151 #define TPI_FIFO1_ITM_ATVALID_Pos 29U
1152 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)
1154 #define TPI_FIFO1_ITM_bytecount_Pos 27U
1155 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)
1157 #define TPI_FIFO1_ETM_ATVALID_Pos 26U
1158 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)
1160 #define TPI_FIFO1_ETM_bytecount_Pos 24U
1161 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)
1163 #define TPI_FIFO1_ITM2_Pos 16U
1164 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)
1166 #define TPI_FIFO1_ITM1_Pos 8U
1167 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)
1169 #define TPI_FIFO1_ITM0_Pos 0U
1170 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)
1172 /* TPI ITATBCTR0 Register Definitions */
1173 #define TPI_ITATBCTR0_ATREADY2_Pos 0U
1174 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/)
1176 #define TPI_ITATBCTR0_ATREADY1_Pos 0U
1177 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/)
1179 /* TPI Integration Mode Control Register Definitions */
1180 #define TPI_ITCTRL_Mode_Pos 0U
1181 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)
1183 /* TPI DEVID Register Definitions */
1184 #define TPI_DEVID_NRZVALID_Pos 11U
1185 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)
1187 #define TPI_DEVID_MANCVALID_Pos 10U
1188 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)
1190 #define TPI_DEVID_PTINVALID_Pos 9U
1191 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)
1193 #define TPI_DEVID_MinBufSz_Pos 6U
1194 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)
1196 #define TPI_DEVID_AsynClkIn_Pos 5U
1197 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)
1199 #define TPI_DEVID_NrTraceInput_Pos 0U
1200 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)
1202 /* TPI DEVTYPE Register Definitions */
1203 #define TPI_DEVTYPE_SubType_Pos 4U
1204 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)
1206 #define TPI_DEVTYPE_MajorType_Pos 0U
1207 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)
1209  /* end of group CMSIS_TPI */
1210 
1211 
1212 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1213 
1223 typedef struct
1224 {
1225  __IM uint32_t TYPE;
1226  __IOM uint32_t CTRL;
1227  __IOM uint32_t RNR;
1228  __IOM uint32_t RBAR;
1229  __IOM uint32_t RASR;
1230  __IOM uint32_t RBAR_A1;
1231  __IOM uint32_t RASR_A1;
1232  __IOM uint32_t RBAR_A2;
1233  __IOM uint32_t RASR_A2;
1234  __IOM uint32_t RBAR_A3;
1235  __IOM uint32_t RASR_A3;
1236 } MPU_Type;
1237 
1238 #define MPU_TYPE_RALIASES 4U
1239 
1240 /* MPU Type Register Definitions */
1241 #define MPU_TYPE_IREGION_Pos 16U
1242 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos)
1244 #define MPU_TYPE_DREGION_Pos 8U
1245 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos)
1247 #define MPU_TYPE_SEPARATE_Pos 0U
1248 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)
1250 /* MPU Control Register Definitions */
1251 #define MPU_CTRL_PRIVDEFENA_Pos 2U
1252 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos)
1254 #define MPU_CTRL_HFNMIENA_Pos 1U
1255 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos)
1257 #define MPU_CTRL_ENABLE_Pos 0U
1258 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/)
1260 /* MPU Region Number Register Definitions */
1261 #define MPU_RNR_REGION_Pos 0U
1262 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/)
1264 /* MPU Region Base Address Register Definitions */
1265 #define MPU_RBAR_ADDR_Pos 5U
1266 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
1268 #define MPU_RBAR_VALID_Pos 4U
1269 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos)
1271 #define MPU_RBAR_REGION_Pos 0U
1272 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/)
1274 /* MPU Region Attribute and Size Register Definitions */
1275 #define MPU_RASR_ATTRS_Pos 16U
1276 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos)
1278 #define MPU_RASR_XN_Pos 28U
1279 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos)
1281 #define MPU_RASR_AP_Pos 24U
1282 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos)
1284 #define MPU_RASR_TEX_Pos 19U
1285 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos)
1287 #define MPU_RASR_S_Pos 18U
1288 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos)
1290 #define MPU_RASR_C_Pos 17U
1291 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos)
1293 #define MPU_RASR_B_Pos 16U
1294 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos)
1296 #define MPU_RASR_SRD_Pos 8U
1297 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos)
1299 #define MPU_RASR_SIZE_Pos 1U
1300 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos)
1302 #define MPU_RASR_ENABLE_Pos 0U
1303 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/)
1305 
1306 #endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */
1307 
1308 
1319 typedef struct
1320 {
1321  uint32_t RESERVED0[1U];
1322  __IOM uint32_t FPCCR;
1323  __IOM uint32_t FPCAR;
1324  __IOM uint32_t FPDSCR;
1325  __IM uint32_t MVFR0;
1326  __IM uint32_t MVFR1;
1327 } FPU_Type;
1328 
1329 /* Floating-Point Context Control Register Definitions */
1330 #define FPU_FPCCR_ASPEN_Pos 31U
1331 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos)
1333 #define FPU_FPCCR_LSPEN_Pos 30U
1334 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos)
1336 #define FPU_FPCCR_MONRDY_Pos 8U
1337 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos)
1339 #define FPU_FPCCR_BFRDY_Pos 6U
1340 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos)
1342 #define FPU_FPCCR_MMRDY_Pos 5U
1343 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos)
1345 #define FPU_FPCCR_HFRDY_Pos 4U
1346 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos)
1348 #define FPU_FPCCR_THREAD_Pos 3U
1349 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos)
1351 #define FPU_FPCCR_USER_Pos 1U
1352 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos)
1354 #define FPU_FPCCR_LSPACT_Pos 0U
1355 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)
1357 /* Floating-Point Context Address Register Definitions */
1358 #define FPU_FPCAR_ADDRESS_Pos 3U
1359 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)
1361 /* Floating-Point Default Status Control Register Definitions */
1362 #define FPU_FPDSCR_AHP_Pos 26U
1363 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos)
1365 #define FPU_FPDSCR_DN_Pos 25U
1366 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos)
1368 #define FPU_FPDSCR_FZ_Pos 24U
1369 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos)
1371 #define FPU_FPDSCR_RMode_Pos 22U
1372 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos)
1374 /* Media and FP Feature Register 0 Definitions */
1375 #define FPU_MVFR0_FP_rounding_modes_Pos 28U
1376 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)
1378 #define FPU_MVFR0_Short_vectors_Pos 24U
1379 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos)
1381 #define FPU_MVFR0_Square_root_Pos 20U
1382 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos)
1384 #define FPU_MVFR0_Divide_Pos 16U
1385 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos)
1387 #define FPU_MVFR0_FP_excep_trapping_Pos 12U
1388 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)
1390 #define FPU_MVFR0_Double_precision_Pos 8U
1391 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos)
1393 #define FPU_MVFR0_Single_precision_Pos 4U
1394 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos)
1396 #define FPU_MVFR0_A_SIMD_registers_Pos 0U
1397 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)
1399 /* Media and FP Feature Register 1 Definitions */
1400 #define FPU_MVFR1_FP_fused_MAC_Pos 28U
1401 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)
1403 #define FPU_MVFR1_FP_HPFP_Pos 24U
1404 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos)
1406 #define FPU_MVFR1_D_NaN_mode_Pos 4U
1407 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)
1409 #define FPU_MVFR1_FtZ_mode_Pos 0U
1410 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)
1412 
1425 typedef struct
1426 {
1427  __IOM uint32_t DHCSR;
1428  __OM uint32_t DCRSR;
1429  __IOM uint32_t DCRDR;
1430  __IOM uint32_t DEMCR;
1431 } CoreDebug_Type;
1432 
1433 /* Debug Halting Control and Status Register Definitions */
1434 #define CoreDebug_DHCSR_DBGKEY_Pos 16U
1435 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
1437 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U
1438 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
1440 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U
1441 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
1443 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U
1444 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
1446 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U
1447 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
1449 #define CoreDebug_DHCSR_S_HALT_Pos 17U
1450 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos)
1452 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U
1453 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
1455 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U
1456 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
1458 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U
1459 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
1461 #define CoreDebug_DHCSR_C_STEP_Pos 2U
1462 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos)
1464 #define CoreDebug_DHCSR_C_HALT_Pos 1U
1465 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos)
1467 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U
1468 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)
1470 /* Debug Core Register Selector Register Definitions */
1471 #define CoreDebug_DCRSR_REGWnR_Pos 16U
1472 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos)
1474 #define CoreDebug_DCRSR_REGSEL_Pos 0U
1475 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)
1477 /* Debug Exception and Monitor Control Register Definitions */
1478 #define CoreDebug_DEMCR_TRCENA_Pos 24U
1479 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos)
1481 #define CoreDebug_DEMCR_MON_REQ_Pos 19U
1482 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
1484 #define CoreDebug_DEMCR_MON_STEP_Pos 18U
1485 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
1487 #define CoreDebug_DEMCR_MON_PEND_Pos 17U
1488 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
1490 #define CoreDebug_DEMCR_MON_EN_Pos 16U
1491 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos)
1493 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U
1494 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
1496 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U
1497 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
1499 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U
1500 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
1502 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U
1503 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
1505 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U
1506 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
1508 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U
1509 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
1511 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U
1512 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
1514 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U
1515 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)
1517 
1533 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1534 
1541 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1542 
1553 /* Memory mapping of Core Hardware */
1554 #define SCS_BASE (0xE000E000UL)
1555 #define ITM_BASE (0xE0000000UL)
1556 #define DWT_BASE (0xE0001000UL)
1557 #define TPI_BASE (0xE0040000UL)
1558 #define CoreDebug_BASE (0xE000EDF0UL)
1559 #define SysTick_BASE (SCS_BASE + 0x0010UL)
1560 #define NVIC_BASE (SCS_BASE + 0x0100UL)
1561 #define SCB_BASE (SCS_BASE + 0x0D00UL)
1563 #define SCnSCB ((SCnSCB_Type *) SCS_BASE )
1564 #define SCB ((SCB_Type *) SCB_BASE )
1565 #define SysTick ((SysTick_Type *) SysTick_BASE )
1566 #define NVIC ((NVIC_Type *) NVIC_BASE )
1567 #define ITM ((ITM_Type *) ITM_BASE )
1568 #define DWT ((DWT_Type *) DWT_BASE )
1569 #define TPI ((TPI_Type *) TPI_BASE )
1570 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE)
1572 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1573  #define MPU_BASE (SCS_BASE + 0x0D90UL)
1574  #define MPU ((MPU_Type *) MPU_BASE )
1575 #endif
1576 
1577 #define FPU_BASE (SCS_BASE + 0x0F30UL)
1578 #define FPU ((FPU_Type *) FPU_BASE )
1580 
1584 /*******************************************************************************
1585  * Hardware Abstraction Layer
1586  Core Function Interface contains:
1587  - Core NVIC Functions
1588  - Core SysTick Functions
1589  - Core Debug Functions
1590  - Core Register Access Functions
1591  ******************************************************************************/
1592 
1598 /* ########################## NVIC functions #################################### */
1606 #ifdef CMSIS_NVIC_VIRTUAL
1607  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1608  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1609  #endif
1610  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1611 #else
1612  #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1613  #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1614  #define NVIC_EnableIRQ __NVIC_EnableIRQ
1615  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1616  #define NVIC_DisableIRQ __NVIC_DisableIRQ
1617  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1618  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1619  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1620  #define NVIC_GetActive __NVIC_GetActive
1621  #define NVIC_SetPriority __NVIC_SetPriority
1622  #define NVIC_GetPriority __NVIC_GetPriority
1623  #define NVIC_SystemReset __NVIC_SystemReset
1624 #endif /* CMSIS_NVIC_VIRTUAL */
1625 
1626 #ifdef CMSIS_VECTAB_VIRTUAL
1627  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1628  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1629  #endif
1630  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1631 #else
1632  #define NVIC_SetVector __NVIC_SetVector
1633  #define NVIC_GetVector __NVIC_GetVector
1634 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1635 
1636 #define NVIC_USER_IRQ_OFFSET 16
1637 
1638 
1639 /* The following EXC_RETURN values are saved the LR on exception entry */
1640 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
1641 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
1642 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
1643 #define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */
1644 #define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */
1645 #define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */
1646 
1647 
1657 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1658 {
1659  uint32_t reg_value;
1660  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1661 
1662  reg_value = SCB->AIRCR; /* read old register configuration */
1663  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1664  reg_value = (reg_value |
1665  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1666  (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
1667  SCB->AIRCR = reg_value;
1668 }
1669 
1670 
1676 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1677 {
1678  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1679 }
1680 
1681 
1688 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1689 {
1690  if ((int32_t)(IRQn) >= 0)
1691  {
1692  NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1693  }
1694 }
1695 
1696 
1705 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1706 {
1707  if ((int32_t)(IRQn) >= 0)
1708  {
1709  return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1710  }
1711  else
1712  {
1713  return(0U);
1714  }
1715 }
1716 
1717 
1724 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1725 {
1726  if ((int32_t)(IRQn) >= 0)
1727  {
1728  NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1729  __DSB();
1730  __ISB();
1731  }
1732 }
1733 
1734 
1743 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1744 {
1745  if ((int32_t)(IRQn) >= 0)
1746  {
1747  return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1748  }
1749  else
1750  {
1751  return(0U);
1752  }
1753 }
1754 
1755 
1762 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1763 {
1764  if ((int32_t)(IRQn) >= 0)
1765  {
1766  NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1767  }
1768 }
1769 
1770 
1777 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1778 {
1779  if ((int32_t)(IRQn) >= 0)
1780  {
1781  NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1782  }
1783 }
1784 
1785 
1794 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1795 {
1796  if ((int32_t)(IRQn) >= 0)
1797  {
1798  return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1799  }
1800  else
1801  {
1802  return(0U);
1803  }
1804 }
1805 
1806 
1816 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1817 {
1818  if ((int32_t)(IRQn) >= 0)
1819  {
1820  NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1821  }
1822  else
1823  {
1824  SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1825  }
1826 }
1827 
1828 
1838 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1839 {
1840 
1841  if ((int32_t)(IRQn) >= 0)
1842  {
1843  return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1844  }
1845  else
1846  {
1847  return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1848  }
1849 }
1850 
1851 
1863 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1864 {
1865  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1866  uint32_t PreemptPriorityBits;
1867  uint32_t SubPriorityBits;
1868 
1869  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1870  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1871 
1872  return (
1873  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1874  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1875  );
1876 }
1877 
1878 
1890 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1891 {
1892  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1893  uint32_t PreemptPriorityBits;
1894  uint32_t SubPriorityBits;
1895 
1896  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1897  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1898 
1899  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1900  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1901 }
1902 
1903 
1913 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1914 {
1915  uint32_t *vectors = (uint32_t *)SCB->VTOR;
1916  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1917 }
1918 
1919 
1928 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1929 {
1930  uint32_t *vectors = (uint32_t *)SCB->VTOR;
1931  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1932 }
1933 
1934 
1939 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1940 {
1941  __DSB(); /* Ensure all outstanding memory accesses included
1942  buffered write are completed before reset */
1943  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1944  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1945  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1946  __DSB(); /* Ensure completion of memory access */
1947 
1948  for(;;) /* wait until reset */
1949  {
1950  __NOP();
1951  }
1952 }
1953 
1956 /* ########################## MPU functions #################################### */
1957 
1958 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1959 
1960 #include "mpu_armv7.h"
1961 
1962 #endif
1963 
1964 
1965 /* ########################## FPU functions #################################### */
1981 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1982 {
1983  uint32_t mvfr0;
1984 
1985  mvfr0 = FPU->MVFR0;
1986  if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
1987  {
1988  return 1U; /* Single precision FPU */
1989  }
1990  else
1991  {
1992  return 0U; /* No FPU */
1993  }
1994 }
1995 
1996 
2001 /* ################################## SysTick function ############################################ */
2009 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2010 
2022 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2023 {
2024  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2025  {
2026  return (1UL); /* Reload value impossible */
2027  }
2028 
2029  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2030  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2031  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2032  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2033  SysTick_CTRL_TICKINT_Msk |
2034  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2035  return (0UL); /* Function successful */
2036 }
2037 
2038 #endif
2039 
2044 /* ##################################### Debug In/Output function ########################################### */
2052 extern volatile int32_t ITM_RxBuffer;
2053 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)
2064 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
2065 {
2066  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
2067  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
2068  {
2069  while (ITM->PORT[0U].u32 == 0UL)
2070  {
2071  __NOP();
2072  }
2073  ITM->PORT[0U].u8 = (uint8_t)ch;
2074  }
2075  return (ch);
2076 }
2077 
2078 
2085 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
2086 {
2087  int32_t ch = -1; /* no character available */
2088 
2089  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
2090  {
2091  ch = ITM_RxBuffer;
2092  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
2093  }
2094 
2095  return (ch);
2096 }
2097 
2098 
2105 __STATIC_INLINE int32_t ITM_CheckChar (void)
2106 {
2107 
2108  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
2109  {
2110  return (0); /* no character available */
2111  }
2112  else
2113  {
2114  return (1); /* character available */
2115  }
2116 }
2117 
2123 #ifdef __cplusplus
2124 }
2125 #endif
2126 
2127 #endif /* __CORE_CM4_H_DEPENDANT */
2128 
2129 #endif /* __CMSIS_GENERIC */
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv8mbl.h:1269
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv8mbl.h:1523
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv8mbl.h:1791
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_armv8mml.h:2903
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm4.h:517
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv8mbl.h:351
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm4.h:772
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_armv8mbl.h:381
ITM
#define ITM
Definition: core_cm4.h:1567
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_armv8mbl.h:610
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv8mbl.h:1496
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_cm4.h:2053
SysTick_IRQn
Definition: stm32f103xb.h:80
__DSB
__STATIC_FORCEINLINE void __DSB(void)
Data Synchronization Barrier.
Definition: cmsis_gcc.h:877
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_armv8mbl.h:1358
__NOP
#define __NOP
No Operation.
Definition: cmsis_armcc.h:387
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv8mbl.h:1326
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv8mbl.h:1341
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm4.h:775
SCB
#define SCB
Definition: core_cm4.h:1564
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_armv8mbl.h:558
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_armv8mbl.h:988
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_armv8mbl.h:233
cmsis_version.h
CMSIS Core(M) Version definitions.
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm4.h:518
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv8mbl.h:1252
FPU_MVFR0_Double_precision_Msk
#define FPU_MVFR0_Double_precision_Msk
Definition: core_cm4.h:1391
FPU
#define FPU
Definition: core_cm4.h:1578
FPU_Type
Structure type to access the Floating Point Unit (FPU).
Definition: core_armv8mml.h:1685
SysTick
#define SysTick
Definition: core_cm4.h:1565
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm4.h:527
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv8mbl.h:1547
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_armv8mbl.h:320
__NVIC_SetPriorityGrouping
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_armv8mml.h:2116
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_armv8mbl.h:725
NVIC
#define NVIC
Definition: core_cm4.h:1566
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm4.h:782
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_armv8mml.h:1009
IRQn_Type
IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f103xb.h:69
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv8mbl.h:263
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_armv8mml.h:2883
__ISB
__STATIC_FORCEINLINE void __ISB(void)
Instruction Synchronization Barrier.
Definition: cmsis_gcc.h:866
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv8mbl.h:281
FPU_MVFR0_Single_precision_Msk
#define FPU_MVFR0_Single_precision_Msk
Definition: core_cm4.h:1394
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv8mbl.h:1288
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm4.h:778
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv8mbl.h:1566
cmsis_compiler.h
CMSIS compiler generic header file.
__NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_armv8mml.h:2135
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: stm32f103xb.h:52
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_cm4.h:877
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm4.h:530
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_armv8mml.h:1086
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv8mbl.h:1581
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv8mbl.h:1447
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv8mbl.h:1307
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv8mbl.h:1471
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm4.h:526
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