PLL Configuration

Collaboration diagram for PLL Configuration:

Macros
#define	__HAL_RCC_PLL_ENABLE()   (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
	Macro to enable the main PLL. More...
#define	__HAL_RCC_PLL_DISABLE()   (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
	Macro to disable the main PLL. More...
#define	__HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)   MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
	Macro to configure the main PLL clock source and multiplication factors. More...
#define	__HAL_RCC_GET_PLL_OSCSOURCE()   ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
	Get oscillator clock selected as PLL input clock. More...

Detailed Description

Macro Definition Documentation

__HAL_RCC_GET_PLL_OSCSOURCE

#define __HAL_RCC_GET_PLL_OSCSOURCE

(

)

((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))

Get oscillator clock selected as PLL input clock.

Return values

The	clock source used for PLL entry. The returned value can be one of the following: RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock

__HAL_RCC_PLL_CONFIG

#define __HAL_RCC_PLL_CONFIG	(		__RCC_PLLSOURCE__,
			__PLLMUL__
	)		MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))

Macro to configure the main PLL clock source and multiplication factors.

Note

This function must be used only when the main PLL is disabled.

Parameters

<strong>RCC_PLLSOURCE</strong>

specifies the PLL entry clock source. This parameter can be one of the following values: RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry

<strong>PLLMUL</strong>

specifies the multiplication factor for PLL VCO output clock This parameter can be one of the following values: RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10 RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11 RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13 RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14 RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15 RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9

__HAL_RCC_PLL_DISABLE

#define __HAL_RCC_PLL_DISABLE

(

)

(*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)

Macro to disable the main PLL.

Note

The main PLL can not be disabled if it is used as system clock source

__HAL_RCC_PLL_ENABLE

#define __HAL_RCC_PLL_ENABLE

(

)

(*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)

Macro to enable the main PLL.

Note

After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.

The main PLL is disabled by hardware when entering STOP and STANDBY modes.